# $Id: README.txt 318 2010-07-23 18:28:40Z mueller $
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# $Id: README.txt 341 2010-11-27 23:05:43Z mueller $
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Release notes for w11a
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Release notes for w11a
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Table of content:
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Table of content:
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1. Documentation
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1. Documentation
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2. Files
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2. Files
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3. Change Log
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3. Change Log
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1. Documentation ----------------------------------------------------------
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1. Documentation ----------------------------------------------------------
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More detailed information on installation, build and test can be found
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More detailed information on installation, build and test can be found
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in the doc directory, specifically
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in the doc directory, specifically
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* README.txt: release notes
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* README.txt: release notes
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* INSTALL.txt: installation and building test benches and systems
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* INSTALL.txt: installation and building test benches and systems
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* w11a_tb_guide.txt: running test benches
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* w11a_tb_guide.txt: running test benches
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* w11a_os_guide.txt: booting operating systems
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* w11a_os_guide.txt: booting operating systems
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* w11a_known_issues.txt: known differences, limitations and issues
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* w11a_known_issues.txt: known differences, limitations and issues
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2. Files ------------------------------------------------------------------
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2. Files ------------------------------------------------------------------
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doc Documentation
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doc Documentation
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rtl VHDL sources
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rtl VHDL sources
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rtl/bplib - board and component support libs
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rtl/bplib - board and component support libs
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rtl/bplib/issi - for ISSI parts
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rtl/bplib/issi - for ISSI parts
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rtl/bplib/micron - for Micron parts
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rtl/bplib/micron - for Micron parts
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rtl/bplib/nexys2 - for Digilent Nexsy2 board
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rtl/bplib/nexys2 - for Digilent Nexsy2 board
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rtl/bplib/s3board - for Digilent S3BOARD
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rtl/bplib/s3board - for Digilent S3BOARD
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rtl/ibus - ibus devices (UNIBUS peripherals)
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rtl/ibus - ibus devices (UNIBUS peripherals)
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rtl/sys_gen - top level designs
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rtl/sys_gen - top level designs
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rtl/sys_gen/w11a - top level designs for w11a SoC
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rtl/sys_gen/w11a - top level designs for w11a SoC
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rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
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rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
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rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
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rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
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rtl/vlib - VHDL component libs
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rtl/vlib - VHDL component libs
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rtl/vlib/comlib - communication
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rtl/vlib/comlib - communication
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rtl/vlib/genlib - general
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rtl/vlib/genlib - general
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rtl/vlib/memlib - memory
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rtl/vlib/memlib - memory
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rtl/vlib/rri - remote-register-interface
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rtl/vlib/rri - remote-register-interface
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rtl/vlib/serport - serial port (UART)
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rtl/vlib/serport - serial port (UART)
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rtl/vlib/simlib - simulation helper lib
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rtl/vlib/simlib - simulation helper lib
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rtl/vlib/xlib - Xilinx specific components
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rtl/vlib/xlib - Xilinx specific components
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rtl/w11a - w11a core
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rtl/w11a - w11a core
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tools helper programs
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tools helper programs
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tools/bin - scripts and binaries
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tools/bin - scripts and binaries
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3. Change Log -------------------------------------------------------------
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3. Change Log -------------------------------------------------------------
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- trunk (current development snapshot) -----------------------
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- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51)
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indentical to w11a_V0.5
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- Changes
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- module renames:
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- in future 'box' is used for large autonomous blocks, therefore use
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the term unit for purely sequential logic modules:
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pdp11_abox -> pdp11_ounit
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pdp11_dbox -> pdp11_aunit
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pdp11_lbox -> pdp11_lunit
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pdp11_mbox -> pdp11_munit
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- signal renames:
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- renamed RRI_LAM -> RB_LAM in all ibus devices
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- renamed CLK -> I_CLK50 in all top level nexys2 and s3board designs
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- migrate to ibus protocol verion 2
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- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
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- basic ibus transaction now takes 2 cycles, one for address select, one
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for data exchange. This avoids too long logic paths in ibus sector.
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- New features
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- ibus
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- added ib_sres_or_mon to check for miss-behaving ibus devices
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- added ib_sel to encapsulate address select logic
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- nexys2 systems
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- now DCM derived system clock supported
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- sys_gen/w11a/nexys2
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- sys_w11a_n2 now runs with 58 MHz clksys
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- Bug fixes
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- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
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- w11a_V0.5 (2010-07-23) -------------------------------------
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- w11a_V0.5 (2010-07-23) -------------------------------------
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Initial release with
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Initial release with
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- w11a CPU core
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- w11a CPU core
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- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
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- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
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- just for fun: iist (not fully implemented and tested yet)
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- just for fun: iist (not fully implemented and tested yet)
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- two complete system configurations with
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- two complete system configurations with
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- for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3
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- for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3
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- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2
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- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2
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