$Id: README.txt 811 2016-10-03 07:24:02Z mueller $
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$Id: README.txt 811 2016-10-03 07:24:02Z mueller $
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Release notes for w11a
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Release notes for w11a
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Table of content:
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Table of content:
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1. Documentation
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1. Documentation
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2. Change Log
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2. Change Log
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1. Documentation -------------------------------------------------------------
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1. Documentation -------------------------------------------------------------
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More detailed information on installation, build and test can be found
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More detailed information on installation, build and test can be found
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in the doc directory, specifically
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in the doc directory, specifically
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* README.txt: release notes
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* README.txt: release notes
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* README_known_issues.txt: known issues
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* README_known_issues.txt: known issues
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* INSTALL.txt: installation and building test benches and systems
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* INSTALL.txt: installation and building test benches and systems
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* FILES.txt: short description of the directory layout, what is where ?
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* FILES.txt: short description of the directory layout, what is where ?
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* w11a_tb_guide.txt: running test benches
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* w11a_tb_guide.txt: running test benches
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* w11a_os_guide.txt: booting operating systems
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* w11a_os_guide.txt: booting operating systems
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* w11a_known_issues.txt: known differences, limitations and issues
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* w11a_known_issues.txt: known differences, limitations and issues
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2. Change Log ----------------------------------------------------------------
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2. Change Log ----------------------------------------------------------------
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- trunk (2016-10-02: svn rev 37(oc) 811(wfjm); untagged w11a_V0.74) +++++++++
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- trunk (2016-10-02: svn rev 37(oc) 811(wfjm); untagged w11a_V0.74) +++++++++
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- Preface
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- Preface
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- the current version of the memory controller for the micron mt45w8mw16b
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- the current version of the memory controller for the micron mt45w8mw16b
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'cellular ram' used on nexys2, nexys3, and nexys4 uses the asynchronous
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'cellular ram' used on nexys2, nexys3, and nexys4 uses the asynchronous
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access mode. The device supports a 'page mode' to speed up read access to
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access mode. The device supports a 'page mode' to speed up read access to
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subsequent addresses. Even though prepared in the controller logic this
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subsequent addresses. Even though prepared in the controller logic this
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feature was simply forgotten. This is now properly implemented and
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feature was simply forgotten. This is now properly implemented and
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results in a bit faster cache line load times. The overall performance
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results in a bit faster cache line load times. The overall performance
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of a w11a design is measurably, but marginally better.
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of a w11a design is measurably, but marginally better.
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- many unit tests still used a ISE environment. All board independent
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- many unit tests still used a ISE environment. All board independent
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tests were converted now to a vivado environment, only tests which
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tests were converted now to a vivado environment, only tests which
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really depend a FPGA not supported by vivado stay with ISE.
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really depend a FPGA not supported by vivado stay with ISE.
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- a total of 82 unit or system tests are currently available. Many of them
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- a total of 82 unit or system tests are currently available. Many of them
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can be executed by different simulation engines, ghdl or the ISE/vivado
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can be executed by different simulation engines, ghdl or the ISE/vivado
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build-in simulators, and for different stages of the implementation flow,
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build-in simulators, and for different stages of the implementation flow,
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from initial behavioral simulation over post-synthesis functional to final
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from initial behavioral simulation over post-synthesis functional to final
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post-routing timing simulation. This results in a large number of possible
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post-routing timing simulation. This results in a large number of possible
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tests. All test benches are all self-checking, but the execution of them
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tests. All test benches are all self-checking, but the execution of them
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was so far not sufficiently automatized.
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was so far not sufficiently automatized.
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This was addressed with 'tbrun', a test bench driver, which obtains a
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This was addressed with 'tbrun', a test bench driver, which obtains a
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list of all available test benches from configuration files, selects
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list of all available test benches from configuration files, selects
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a subset given by selection criteria, and executes them. It can handle
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a subset given by selection criteria, and executes them. It can handle
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the parallel execution of tests so multi-core systems can be very
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the parallel execution of tests so multi-core systems can be very
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easily exploited. Running all tests is now a single shell command.
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easily exploited. Running all tests is now a single shell command.
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- a new tool 'tbfilt' simplifies the logic of self-checking test benches
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- a new tool 'tbfilt' simplifies the logic of self-checking test benches
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and can also be used as a tool to analyze the full log files produced
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and can also be used as a tool to analyze the full log files produced
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by the test benches
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by the test benches
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- several test benches have been added to this release, most notably the
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- several test benches have been added to this release, most notably the
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memory tester sys_tst_sram_* which was originally developed to verify
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memory tester sys_tst_sram_* which was originally developed to verify
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the s3board SRAM controller and later ported to verify the nexys* CRAM
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the s3board SRAM controller and later ported to verify the nexys* CRAM
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controller.
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controller.
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- the system test benches with SRAM and CRAM now include the PCB trace
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- the system test benches with SRAM and CRAM now include the PCB trace
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delay between FPGA and memory chip. The new entity simbididly models a
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delay between FPGA and memory chip. The new entity simbididly models a
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bi-directional bus delay.
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bi-directional bus delay.
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- so far test benches ended by stopping the clock, all processes were
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- so far test benches ended by stopping the clock, all processes were
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written such that they enter a permanent wait, which causes the simulation
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written such that they enter a permanent wait, which causes the simulation
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to stop. Worked for fine behavioral simulations, but fails when Xilinx
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to stop. Worked for fine behavioral simulations, but fails when Xilinx
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MMCMs are involved in post-synthesis simulations. The UNISIM models
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MMCMs are involved in post-synthesis simulations. The UNISIM models
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apparently have timed waits. The test benches were modified to stop via a
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apparently have timed waits. The test benches were modified to stop via a
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report with severity failure, the test environment detects this specific
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report with severity failure, the test environment detects this specific
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assertion/report failure and accepts it as successful termination of
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assertion/report failure and accepts it as successful termination of
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the simulation.
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the simulation.
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- the configuration of the board switches in system test benches was done
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- the configuration of the board switches in system test benches was done
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in a sub-optimal way which could lead to startup problems. tbrun_tbwrri
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in a sub-optimal way which could lead to startup problems. tbrun_tbwrri
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uses now a different mechanism which ensures that all board and test
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uses now a different mechanism which ensures that all board and test
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bench configuration is done in the first ns of the simulation and has
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bench configuration is done in the first ns of the simulation and has
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thus completed well before all other activities.
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thus completed well before all other activities.
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- finally a caveat: post-synthesis simulations work fine with ISE, but
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- finally a caveat: post-synthesis simulations work fine with ISE, but
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currently not with vivado, even in case of almost identical designs,
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currently not with vivado, even in case of almost identical designs,
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like sys_tst_rlink_n3 vs sys_tst_rlink_n4. Is under investigation.
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like sys_tst_rlink_n3 vs sys_tst_rlink_n4. Is under investigation.
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- Summary
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- Summary
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- upgraded CRAM controller, now with 'page mode' support
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- upgraded CRAM controller, now with 'page mode' support
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- new test bench driver tbrun, give automatized test bench execution
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- new test bench driver tbrun, give automatized test bench execution
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- New features
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- New features
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- new modules
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- new modules
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- rtl/bplib/issi/tb/* - added unit test for is61lv25616al model
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- rtl/bplib/issi/tb/* - added unit test for is61lv25616al model
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- rtl/bplib/micron/tb/* - added unit test for mt45w8mw16b model
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- rtl/bplib/micron/tb/* - added unit test for mt45w8mw16b model
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- rtl/sys_gen/tst_serloop - add serloop2 (2 clock) designs for n3,n4
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- rtl/sys_gen/tst_serloop - add serloop2 (2 clock) designs for n3,n4
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- nexys3/sys_tst_serloop2_n3.vhd
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- nexys3/sys_tst_serloop2_n3.vhd
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- nexys4/sys_tst_serloop2_n4.vhd
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- nexys4/sys_tst_serloop2_n4.vhd
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- rtl/sys_gen/tst_sram - add sram test design for
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- rtl/sys_gen/tst_sram - add sram test design for
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- nexys2/*
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- nexys2/*
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- nexys3/*
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- nexys3/*
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- nexys4/*
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- nexys4/*
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- s3board/*
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- s3board/*
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- rtl/vlib/genlib/tb
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- rtl/vlib/genlib/tb
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- clkdivce_tb.vhd - copy for tb usage of clkdivce
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- clkdivce_tb.vhd - copy for tb usage of clkdivce
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- rtl/vlib/rlink/tb
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- rtl/vlib/rlink/tb
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- rlink_tba.vhd - rlink test bench adapter
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- rlink_tba.vhd - rlink test bench adapter
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- tb_rlink_tba.vhd - test bench for rbus devices
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- tb_rlink_tba.vhd - test bench for rbus devices
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- tbd_tba_ttcombo.vhd - tba tester for ttcombo
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- tbd_tba_ttcombo.vhd - tba tester for ttcombo
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- rtl/vlib/simlib
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- rtl/vlib/simlib
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- simbididly.vhd - bi-di bus delay model
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- simbididly.vhd - bi-di bus delay model
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- rtl/vlib/xlib
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- rtl/vlib/xlib
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- gsr_pulse.vhd - pulse GSR at startup
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- gsr_pulse.vhd - pulse GSR at startup
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- gsr_pulse_dummy.vhd - no-action dummy (for bsim models)
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- gsr_pulse_dummy.vhd - no-action dummy (for bsim models)
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- rtl/w11a/tb
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- rtl/w11a/tb
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- tb_rlink_tba_pdp11core.vhd - tba tester for w11a
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- tb_rlink_tba_pdp11core.vhd - tba tester for w11a
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- new files
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- new files
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- doc/man/man1 - added tbrun,tbfilt man pages
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- doc/man/man1 - added tbrun,tbfilt man pages
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- */tbrun.yml - test bench descriptors for tbrun
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- */tbrun.yml - test bench descriptors for tbrun
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- rtl/sys_gen/w11a/tb
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- rtl/sys_gen/w11a/tb
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- tb_w11a_mem70*.dat - stim files for additional tests
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- tb_w11a_mem70*.dat - stim files for additional tests
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- rtl/w11a/tb
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- rtl/w11a/tb
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- tb_pdp11core_ubmap.dat - stim files for additional test
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- tb_pdp11core_ubmap.dat - stim files for additional test
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- tools/bin
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- tools/bin
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- njobihtm - determine #jobs
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- njobihtm - determine #jobs
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- tbfilt - test bench output filter
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- tbfilt - test bench output filter
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- tbrun - test bench driver
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- tbrun - test bench driver
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- ticonv_rri - converts old 'mode rri' for ti_rri
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- ticonv_rri - converts old 'mode rri' for ti_rri
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- tools/tcl/tst_sram/*.tcl - support for sys_tst_sram
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- tools/tcl/tst_sram/*.tcl - support for sys_tst_sram
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- Changes
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- Changes
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- rtl/bplib
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- rtl/bplib
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- arty/tb/tb_arty.vhd - add gsr_pulse (provisional....)
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- arty/tb/tb_arty.vhd - add gsr_pulse (provisional....)
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- */tb/tb_*.vhd - tbcore_rlink without CLK_STOP now
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- */tb/tb_*.vhd - tbcore_rlink without CLK_STOP now
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- fx2lib/tb/fx2_2fifo_core.vhd - proc_ifclk: remove clock stop
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- fx2lib/tb/fx2_2fifo_core.vhd - proc_ifclk: remove clock stop
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- nexys2/tb/tb_nexys2_core.vhd - use simbididly
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- nexys2/tb/tb_nexys2_core.vhd - use simbididly
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- nexys3/tb/tb_nexys3_core.vhd - use simbididly
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- nexys3/tb/tb_nexys3_core.vhd - use simbididly
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- nexys4/tb/tb_nexys4_cram.vhd - use simbididly
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- nexys4/tb/tb_nexys4_cram.vhd - use simbididly
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- nxcramlib
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- nxcramlib
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- nx_cram_memctl_as.vhd - add page mode support
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- nx_cram_memctl_as.vhd - add page mode support
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- nxcramlib.vhd - add cram_*delay functions
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- nxcramlib.vhd - add cram_*delay functions
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- s3board
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- s3board
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- s3_sram_memctl.vhd - drop "KEEP" for data (better for dbg)
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- s3_sram_memctl.vhd - drop "KEEP" for data (better for dbg)
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- tb/tb_s3board_core.vhd - use simbididly
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- tb/tb_s3board_core.vhd - use simbididly
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- rtl/make_ise
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- rtl/make_ise
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- generic_ghdl.mk - ghdl_clean: remove also gcov files
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- generic_ghdl.mk - ghdl_clean: remove also gcov files
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- rtl/make_viv
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- rtl/make_viv
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- generic_ghdl.mk - ghdl_clean: remove also gcov files
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- generic_ghdl.mk - ghdl_clean: remove also gcov files
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- generic_vivado.mk - viv_clean: rm only vivado logs
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- generic_vivado.mk - viv_clean: rm only vivado logs
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- generic_xsim.mk - xsim work dir now xsim..
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- generic_xsim.mk - xsim work dir now xsim..
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- rtl/sys_gen/tst_serloop
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- rtl/sys_gen/tst_serloop
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- */tb/tb_tst_serloop*.vhd - remove CLK_STOP logic
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- */tb/tb_tst_serloop*.vhd - remove CLK_STOP logic
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- tb/tb_tst_serloop.vhd - remove CLK_STOP logic
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- tb/tb_tst_serloop.vhd - remove CLK_STOP logic
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- rtl/sys_gen/w11a/nexys*
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- rtl/sys_gen/w11a/nexys*
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- sys_conf.vhd - use cram_*delay functions
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- sys_conf.vhd - use cram_*delay functions
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- rtl/vlib/rlink
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- rtl/vlib/rlink
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- rlink_core.vhd - remove 'assert false' from report stmts
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- rlink_core.vhd - remove 'assert false' from report stmts
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- tb/tb_rlink.vhd - use clkdivce_tb
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- tb/tb_rlink.vhd - use clkdivce_tb
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- tbcore/tbcore_rlink.vhd - conf: add .wait, CONF_DONE; drop CLK_STOP
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- tbcore/tbcore_rlink.vhd - conf: add .wait, CONF_DONE; drop CLK_STOP
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- rtl/vlib/simlib
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- rtl/vlib/simlib
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- simbus.vhd - rename SB_CLKSTOP > SB_SIMSTOP
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- simbus.vhd - rename SB_CLKSTOP > SB_SIMSTOP
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- simclk.vhd - CLK_STOP now optional port
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- simclk.vhd - CLK_STOP now optional port
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- rtl/vlib/xlib
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- rtl/vlib/xlib
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- */s*_cmt_sfs_*.vhd - remove 'assert false' from report stmts
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- */s*_cmt_sfs_*.vhd - remove 'assert false' from report stmts
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- tools/bin
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- tools/bin
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- tbrun_tbwrri - add --r(l|b)mon,(b|s)wait; configure
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- tbrun_tbwrri - add --r(l|b)mon,(b|s)wait; configure
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now via _conf={...}
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now via _conf={...}
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- tbw - use {} as delimiter for immediate mode
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- tbw - use {} as delimiter for immediate mode
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- vbomconv - add VBOMCONV_GHDL_OPTS and .._GHDL_GCOV
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- vbomconv - add VBOMCONV_GHDL_OPTS and .._GHDL_GCOV
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- xise_ghdl_* - add ghdlopts as 1st option; def is -O2
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- xise_ghdl_* - add ghdlopts as 1st option; def is -O2
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- removed files
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- removed files
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- tools/bin/ghdl_assert_filter - obsolete (use tbfilt now)
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- tools/bin/ghdl_assert_filter - obsolete (use tbfilt now)
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- renames
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- renames
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- rtl/make_viv/viv_*.tcl -> tools/vivado - separate make and tools
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- rtl/make_viv/viv_*.tcl -> tools/vivado - separate make and tools
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- Bug fixes
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- Bug fixes
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- tools/bin
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- tools/bin
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- tbw - xsim: append -R to ARGV (was prepended...)
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- tbw - xsim: append -R to ARGV (was prepended...)
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- xtwi - add ":." to PATH even under BARE_PATH
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- xtwi - add ":." to PATH even under BARE_PATH
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- Known issues
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- Known issues
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- all issues: see README_known_issues.txt
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- all issues: see README_known_issues.txt
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- no resolved or new issues in this release
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- no resolved or new issues in this release
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- trunk (2016-06-26: svn rev 36(oc) 779(wfjm); untagged w11a_V0.73) +++++++++
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- trunk (2016-06-26: svn rev 36(oc) 779(wfjm); untagged w11a_V0.73) +++++++++
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- Preface
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- Preface
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- the 'basic vivado support' added with V0.64 was a minimal effort port of
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- the 'basic vivado support' added with V0.64 was a minimal effort port of
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the code base used under ISE, leading to sub-optimal results under vivado.
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the code base used under ISE, leading to sub-optimal results under vivado.
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- the FSM inference under vivado is quirky and has several issues. The
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- the FSM inference under vivado is quirky and has several issues. The
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most essential one prevented re-coding with 'one_hot' encoding, which
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most essential one prevented re-coding with 'one_hot' encoding, which
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lead to high logic depth and low clock rates. Proper work-arounds were
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lead to high logic depth and low clock rates. Proper work-arounds were
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applied to almost all FSMs, now vivado infers all (but one) properly
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applied to almost all FSMs, now vivado infers all (but one) properly
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and re-codes them as 'one_hot'. That is especially important for the
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and re-codes them as 'one_hot'. That is especially important for the
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pdp11_sequencer, which has 113 states. The sys_w11a_n4 system can now
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pdp11_sequencer, which has 113 states. The sys_w11a_n4 system can now
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run with up to 90 MHz (was 75-80 MHz before).
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run with up to 90 MHz (was 75-80 MHz before).
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- due to a remaining synthesis issue the dmscnt and dmcmon debug units
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- due to a remaining synthesis issue the dmscnt and dmcmon debug units
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are currently disabled for Artix based systems (see issue V0.73-3).
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are currently disabled for Artix based systems (see issue V0.73-3).
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- memory inference is now used for all distributed and block rams under
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- memory inference is now used for all distributed and block rams under
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vivado. The memory generators in memlib are still used under ISE
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vivado. The memory generators in memlib are still used under ISE
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Note: they were initially setup to work around ISE synthesis issues.
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Note: they were initially setup to work around ISE synthesis issues.
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- vivado synthesis and implementation use now 'explore' type flows for
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- vivado synthesis and implementation use now 'explore' type flows for
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optimal timing performance.
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optimal timing performance.
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- the two clock dram based fifo was re-written (as fifo_2c_dram2) to allow
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- the two clock dram based fifo was re-written (as fifo_2c_dram2) to allow
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proper usage of vivado constraints (e.g. scoped xdc).
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proper usage of vivado constraints (e.g. scoped xdc).
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- vivado is now the prime platform for all further development
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- vivado is now the prime platform for all further development
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- the component test benches run now by default under Vivado with an
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- the component test benches run now by default under Vivado with an
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Artix-7 as default target. The makefiles for ISE with a Spartan-6 target
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Artix-7 as default target. The makefiles for ISE with a Spartan-6 target
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are available as 'Makefile.ise' and via the 'makeise' command.
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are available as 'Makefile.ise' and via the 'makeise' command.
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- a message filter (xviv_msg_filter) has been developed which lists only
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- a message filter (xviv_msg_filter) has been developed which lists only
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the unexpected message of a synthesis or implementation run. Filter
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the unexpected message of a synthesis or implementation run. Filter
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rule sets (.vmfset files) are available for all designs.
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rule sets (.vmfset files) are available for all designs.
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- full support for the vivado simuator 'xsim' has been added, there are
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- full support for the vivado simuator 'xsim' has been added, there are
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make targets to build a behavioral simulation as well as post-synthesis,
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make targets to build a behavioral simulation as well as post-synthesis,
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post-optimize, and post-routing functional and timing models. All these
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post-optimize, and post-routing functional and timing models. All these
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models are now created in separate sub-directories and can now co-exist.
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models are now created in separate sub-directories and can now co-exist.
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However see issues V.073-1 and 0.73-2 for severe caveats on xsim.
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However see issues V.073-1 and 0.73-2 for severe caveats on xsim.
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- vivado write_vhdl generates code which violates a vhdl language rule.
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- vivado write_vhdl generates code which violates a vhdl language rule.
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Attributes of port signals are declared in the wrong place. xsim and
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Attributes of port signals are declared in the wrong place. xsim and
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other simulators accept this, but ghdl doesn't. As a work-around the
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other simulators accept this, but ghdl doesn't. As a work-around the
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generated code is cleaned up by a filter (see xviv_sim_vhdl_cleanup).
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generated code is cleaned up by a filter (see xviv_sim_vhdl_cleanup).
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- additional rlink devices
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- additional rlink devices
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- the XADC block, available on all 7Series FPGAs, is now accessible via
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- the XADC block, available on all 7Series FPGAs, is now accessible via
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rlink on all Arty, Basys3 and Nexys4 designs. Especially useful on the
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rlink on all Arty, Basys3 and Nexys4 designs. Especially useful on the
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Arty board because on this board also the currents are monitored.
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Arty board because on this board also the currents are monitored.
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- the USR_ACCESS register, available on all 7Series FPGAs, is now readable
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- the USR_ACCESS register, available on all 7Series FPGAs, is now readable
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via rlink on all Arty, Basys3 and Nexys4 designs. The vivado build flow
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via rlink on all Arty, Basys3 and Nexys4 designs. The vivado build flow
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initializes this register with the build timestamp. This allows to
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initializes this register with the build timestamp. This allows to
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verify the build time of a design at run time.
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verify the build time of a design at run time.
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- the cache used by the w11a (pdp11_cache) was initialy developed with the
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- the cache used by the w11a (pdp11_cache) was initialy developed with the
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tight block ram resources of the early Spartan-3 systems in mind. It had
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tight block ram resources of the early Spartan-3 systems in mind. It had
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8 kByte and used 5 BRAMs of size 18 kBit. With very little changes the
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8 kByte and used 5 BRAMs of size 18 kBit. With very little changes the
|
implenenation is now parametrized, and can generate also 16,32, 64 and
|
implenenation is now parametrized, and can generate also 16,32, 64 and
|
even 128 kByte caches which also use the 36 kBit BRAMs on the Artix.
|
even 128 kByte caches which also use the 36 kBit BRAMs on the Artix.
|
There is a trade-off between cache sizes and clock rate due to routing
|
There is a trade-off between cache sizes and clock rate due to routing
|
delays to the BRAM blocks. The w11a on the nexys4 runs with 16 kByte
|
delays to the BRAM blocks. The w11a on the nexys4 runs with 16 kByte
|
cache and 90 MHz clock or with 64 kByte cache and 80 MHz. For practical
|
cache and 90 MHz clock or with 64 kByte cache and 80 MHz. For practical
|
work loads, like a kernel compile, the 64 kByte configuration is better
|
work loads, like a kernel compile, the 64 kByte configuration is better
|
and thus the default.
|
and thus the default.
|
|
|
- resolved known issue V0.64-7: was caused by a combination of issues
|
- resolved known issue V0.64-7: was caused by a combination of issues
|
and is now resolved by a combination of measures: add portsel logic for
|
and is now resolved by a combination of measures: add portsel logic for
|
arty tb, proper portsel setup, configurable timeout, and finally proper
|
arty tb, proper portsel setup, configurable timeout, and finally proper
|
timeout setting.
|
timeout setting.
|
- resolved known issue V0.64-3: So far the arty, basys3 and nexys4 serial
|
- resolved known issue V0.64-3: So far the arty, basys3 and nexys4 serial
|
port, based on a FTDI FT2232, was often operated at 10 MBaud. This rate
|
port, based on a FTDI FT2232, was often operated at 10 MBaud. This rate
|
is in fact not supported by FTDI, the chip will use 8 instead of 10 MBaud.
|
is in fact not supported by FTDI, the chip will use 8 instead of 10 MBaud.
|
Due to auto-bauding, which simly adapts to the actual baud rate, this went
|
Due to auto-bauding, which simly adapts to the actual baud rate, this went
|
undetected for some time. Now all designs use a serport block clocked with
|
undetected for some time. Now all designs use a serport block clocked with
|
120 MHz and can be operated with 12 MBaud.
|
120 MHz and can be operated with 12 MBaud.
|
|
|
- Summary
|
- Summary
|
- new reference system: switched to Vivado 2016.2 (from 2015.4)
|
- new reference system: switched to Vivado 2016.2 (from 2015.4)
|
- code base cleaned-up for vivado, fsm now inferred
|
- code base cleaned-up for vivado, fsm now inferred
|
- xsim support complete (but many issues to be resolved yet)
|
- xsim support complete (but many issues to be resolved yet)
|
- added configurable w11a cache
|
- added configurable w11a cache
|
- removed some never documented and now strategically obsolete designs:
|
- removed some never documented and now strategically obsolete designs:
|
- sys_tst_fx2loop (for nexys2 and nexys3)
|
- sys_tst_fx2loop (for nexys2 and nexys3)
|
- sys_tst_rlink_cuff_ic3 (a three channel variant of the fx2 interface)
|
- sys_tst_rlink_cuff_ic3 (a three channel variant of the fx2 interface)
|
|
|
- New features
|
- New features
|
- new modules
|
- new modules
|
- rtl/vlib
|
- rtl/vlib
|
- generic_clk_100mhz.xdc - generic 100 MHz on CLK constraint (for tbs)
|
- generic_clk_100mhz.xdc - generic 100 MHz on CLK constraint (for tbs)
|
- rtl/vlib/cdclib - new directory for clock domain crossing
|
- rtl/vlib/cdclib - new directory for clock domain crossing
|
- cdc_pulse.vhd - cdc for a pulse (moved in from genlib)
|
- cdc_pulse.vhd - cdc for a pulse (moved in from genlib)
|
- cdc_signal_s1.vhd - cdc for a signal, 2 stage
|
- cdc_signal_s1.vhd - cdc for a signal, 2 stage
|
- cdc_vector_s0.vhd - cdc for a vector, 1 stage
|
- cdc_vector_s0.vhd - cdc for a vector, 1 stage
|
- rtl/vlib/memlib
|
- rtl/vlib/memlib
|
- fifo_2c_dram2.vhd - re-write of fifo_2c_dram to allow
|
- fifo_2c_dram2.vhd - re-write of fifo_2c_dram to allow
|
proper usage of vivado constraints
|
proper usage of vivado constraints
|
- rtl/vlib/rbus
|
- rtl/vlib/rbus
|
- rb_sres_or_6.vhd - rbus result or, 6 input
|
- rb_sres_or_6.vhd - rbus result or, 6 input
|
- rbd_usracc.vhd - return usr_access register
|
- rbd_usracc.vhd - return usr_access register
|
- rtl/vlib/rlink
|
- rtl/vlib/rlink
|
- rlink_sp2c.vhd - rlink_core8 + serport_2clock2 combo
|
- rlink_sp2c.vhd - rlink_core8 + serport_2clock2 combo
|
- rtl/vlib/serport
|
- rtl/vlib/serport
|
- serport_2clock2.vhd - like serport_2clock, use fifo_2c_dram2
|
- serport_2clock2.vhd - like serport_2clock, use fifo_2c_dram2
|
- rtl/vlib/xlib
|
- rtl/vlib/xlib
|
- usr_access_unisim.vhd - Wrapper for USR_ACCESS* entities
|
- usr_access_unisim.vhd - Wrapper for USR_ACCESS* entities
|
- new files
|
- new files
|
- tools/bin
|
- tools/bin
|
- xise_msg_summary - list all filtered ISE messages
|
- xise_msg_summary - list all filtered ISE messages
|
- xviv_msg_filter - message filter for vivado
|
- xviv_msg_filter - message filter for vivado
|
- xviv_msg_summary - list all filtered vivado messages
|
- xviv_msg_summary - list all filtered vivado messages
|
- xviv_sim_vhdl_cleanup - cleanup vivado generated vhdl for ghdl
|
- xviv_sim_vhdl_cleanup - cleanup vivado generated vhdl for ghdl
|
- makeise - wrapper for make -f Makefile.ise
|
- makeise - wrapper for make -f Makefile.ise
|
- tools/tcl/rbtest
|
- tools/tcl/rbtest
|
- test_flow.tcl - test back pressure and flow control
|
- test_flow.tcl - test back pressure and flow control
|
|
|
- Changes
|
- Changes
|
- rtl/bplib/*/*_pins.xdc - add BITSTREAM.CONFIG.USR_ACCESS setup
|
- rtl/bplib/*/*_pins.xdc - add BITSTREAM.CONFIG.USR_ACCESS setup
|
- rtl/bplib/*/tb/tb_*.vbom - use -UUT attribute
|
- rtl/bplib/*/tb/tb_*.vbom - use -UUT attribute
|
- rtl/sys_gen/*/*/tb/tb_*.vbom - use -UUT attribute
|
- rtl/sys_gen/*/*/tb/tb_*.vbom - use -UUT attribute
|
- rtl/make_ise
|
- rtl/make_ise
|
- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
|
- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
|
- generic_xflow.mk - use .imfset for ISE message rules
|
- generic_xflow.mk - use .imfset for ISE message rules
|
- rtl/make_viv
|
- rtl/make_viv
|
- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
|
- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
|
- generic_vivado.mk - add [sorep]sim.v and %.vivado targets
|
- generic_vivado.mk - add [sorep]sim.v and %.vivado targets
|
- vmfset support, use xviv_sim_vhdl_cleanup
|
- vmfset support, use xviv_sim_vhdl_cleanup
|
- generic_xsim.mk - [rep]sim models; use xsim.?sim as workdir
|
- generic_xsim.mk - [rep]sim models; use xsim.?sim as workdir
|
- viv_tools_build.tcl - use explore flows; prj,opt,pla modes
|
- viv_tools_build.tcl - use explore flows; prj,opt,pla modes
|
- viv_tools_config.tcl - add USR_ACCESS readback
|
- viv_tools_config.tcl - add USR_ACCESS readback
|
- viv_tools_model.tcl - add [sor]sim_vhdl [sorepd]sim_veri modes
|
- viv_tools_model.tcl - add [sor]sim_vhdl [sorepd]sim_veri modes
|
- rtl/sys_gen/*/* (all rlink based designs)
|
- rtl/sys_gen/*/* (all rlink based designs)
|
- sys_*.vhd - define rlink SYSID
|
- sys_*.vhd - define rlink SYSID
|
- rtl/sys_gen/*/* (all rlink and 7series based designs)
|
- rtl/sys_gen/*/* (all rlink and 7series based designs)
|
- sys_*.vhd - add rbd_usracc, use serport_2clock2
|
- sys_*.vhd - add rbd_usracc, use serport_2clock2
|
- sys_conf.vhd - use PLL for clkser_gentype
|
- sys_conf.vhd - use PLL for clkser_gentype
|
- rtl/sys_gen/w11a/*
|
- rtl/sys_gen/w11a/*
|
- sys_conf.vhd - add sys_conf_cache_twidth
|
- sys_conf.vhd - add sys_conf_cache_twidth
|
- rtl/sys_gen/tst_serloop/nexys4
|
- rtl/sys_gen/tst_serloop/nexys4
|
- sys_tst_serloop1_n4.vhd - clock now from cmt and configurable
|
- sys_tst_serloop1_n4.vhd - clock now from cmt and configurable
|
- rtl/sys_gen/tst_serloop/tb
|
- rtl/sys_gen/tst_serloop/tb
|
- tb_tst_serloop.vhd - use serport_(uart_rxtx|xontx)_tb
|
- tb_tst_serloop.vhd - use serport_(uart_rxtx|xontx)_tb
|
- rtl/vlib/*/tb/tb_*.vbom - use -UUT attribute
|
- rtl/vlib/*/tb/tb_*.vbom - use -UUT attribute
|
- rtl/vlib/*/tb/tbd_*.vbom - use generic_clk_100mhz.xdc
|
- rtl/vlib/*/tb/tbd_*.vbom - use generic_clk_100mhz.xdc
|
- rtl/vlib/comlib/comlib.vhd - leave return type unconstraint
|
- rtl/vlib/comlib/comlib.vhd - leave return type unconstraint
|
- rtl/vlib/simlib/simlib.vhd - add writetimens()
|
- rtl/vlib/simlib/simlib.vhd - add writetimens()
|
- rtl/w11a
|
- rtl/w11a
|
- pdp11_bram_memctl.vhd - use memory inference now
|
- pdp11_bram_memctl.vhd - use memory inference now
|
- pdp11_cache.vhd - now configurable size (8,16,32,64,128 kB)
|
- pdp11_cache.vhd - now configurable size (8,16,32,64,128 kB)
|
- pdp11_sequencer.vhd - proc_snum conditional (vivado fsm fix)
|
- pdp11_sequencer.vhd - proc_snum conditional (vivado fsm fix)
|
- rtl/*/*.vbom - use memory inference for vivado
|
- rtl/*/*.vbom - use memory inference for vivado
|
- rtl/*/*.vhd - workarounds and fixes to many FSMs
|
- rtl/*/*.vhd - workarounds and fixes to many FSMs
|
- tools/bin
|
- tools/bin
|
- tbrun_tbw - use _bsim.log for behavioral sim log
|
- tbrun_tbw - use _bsim.log for behavioral sim log
|
- tbrun_tbwrri - use _bsim.log for behavioral sim log
|
- tbrun_tbwrri - use _bsim.log for behavioral sim log
|
use 120 sec timeout for simulation
|
use 120 sec timeout for simulation
|
- tbw - add '-norun', -run now default
|
- tbw - add '-norun', -run now default
|
- ti_rri - add --tout option
|
- ti_rri - add --tout option
|
use 120 sec timeout for simulation
|
use 120 sec timeout for simulation
|
- vbomconv - add file properties (-UUT,-SCOPE_REF)
|
- vbomconv - add file properties (-UUT,-SCOPE_REF)
|
full xsim support now in -vsim_prj
|
full xsim support now in -vsim_prj
|
- tools/src/librlink
|
- tools/src/librlink
|
- RlinkConnect - add USR_ACCESS register support
|
- RlinkConnect - add USR_ACCESS register support
|
- tools/src/librlinktpp
|
- tools/src/librlinktpp
|
- RtclRlinkConnect - add USR_ACCESS, timeout access
|
- RtclRlinkConnect - add USR_ACCESS, timeout access
|
- tools/tcl/rbtest
|
- tools/tcl/rbtest
|
- test_data.tcl - add dinc register tests
|
- test_data.tcl - add dinc register tests
|
- tools/tcl/rlink
|
- tools/tcl/rlink
|
- util.tcl - add USR_ACCESS register support
|
- util.tcl - add USR_ACCESS register support
|
|
|
- removed designs
|
- removed designs
|
- rtl/sys_gen/tst_fx2loop/nexys*/*/sys_tst_fx2loop_*_n*
|
- rtl/sys_gen/tst_fx2loop/nexys*/*/sys_tst_fx2loop_*_n*
|
- rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2
|
- rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2
|
- renames
|
- renames
|
- *.mfset -> *.imfset - to be complementary to new .vmfset
|
- *.mfset -> *.imfset - to be complementary to new .vmfset
|
- Makefile -> Makefile.ise - old ISE makefiles in component areas
|
- Makefile -> Makefile.ise - old ISE makefiles in component areas
|
|
|
- Bug fixes
|
- Bug fixes
|
- rtl/bplib/arty/tb
|
- rtl/bplib/arty/tb
|
- tb_arty.vhd: - add portsel logic
|
- tb_arty.vhd: - add portsel logic
|
- rtl/bplib/sysmon
|
- rtl/bplib/sysmon
|
- sysmon_rbus_core.vhd - use s_init (and not s_idle) after RESET
|
- sysmon_rbus_core.vhd - use s_init (and not s_idle) after RESET
|
- rtl/vlib/xlib
|
- rtl/vlib/xlib
|
- s7_cmt_sfs_*.vhd - correct mmcm range check boundaries
|
- s7_cmt_sfs_*.vhd - correct mmcm range check boundaries
|
- tools/bin
|
- tools/bin
|
- ti_w11: - proper portsel oob for -fx
|
- ti_w11: - proper portsel oob for -fx
|
- tbrun_tbwrri: - proper portsel oob for -hxon
|
- tbrun_tbwrri: - proper portsel oob for -hxon
|
|
|
- Known issues
|
- Known issues
|
- all issues: see README_known_issues.txt
|
- all issues: see README_known_issues.txt
|
- resolved issues:
|
- resolved issues:
|
- V0.72-1: since vivado 2016.1 xelab builds models which use DPI in a
|
- V0.72-1: since vivado 2016.1 xelab builds models which use DPI in a
|
mixed vhdl-verilog language environment.
|
mixed vhdl-verilog language environment.
|
- V0.72-2: now full support to build behavioral as well as functional and
|
- V0.72-2: now full support to build behavioral as well as functional and
|
timing simulations with xsim. See V.073-1 and 0.73-2 for caveats.
|
timing simulations with xsim. See V.073-1 and 0.73-2 for caveats.
|
- V0.64-7: flow control issues with simulation models resolved
|
- V0.64-7: flow control issues with simulation models resolved
|
- V0.64-3: basys3, nexys4 and arty designs support now 12 MBaud.
|
- V0.64-3: basys3, nexys4 and arty designs support now 12 MBaud.
|
|
|
- new issues:
|
- new issues:
|
- V0.73-1: as of vivado 2016.2 xelab shows sometimes extremely long build
|
- V0.73-1: as of vivado 2016.2 xelab shows sometimes extremely long build
|
times, especially for generated post-synthesis vhdl models. But also
|
times, especially for generated post-synthesis vhdl models. But also
|
building a behavioral simulation for a w11a design can take 25 min.
|
building a behavioral simulation for a w11a design can take 25 min.
|
Even though post-synthesis or post-routing models are now generated
|
Even though post-synthesis or post-routing models are now generated
|
in verilog working with xsim is cumbersome and time consuming.
|
in verilog working with xsim is cumbersome and time consuming.
|
- V0.73-2: Many post-synthesis functional and especially post-routing
|
- V0.73-2: Many post-synthesis functional and especially post-routing
|
timing simulations currently fail due to startup and initialization
|
timing simulations currently fail due to startup and initialization
|
problems. Cause is MMCM/PLL startup, which is not properly reflected
|
problems. Cause is MMCM/PLL startup, which is not properly reflected
|
in the test bench. Will be resolved in an upcoming release.
|
in the test bench. Will be resolved in an upcoming release.
|
- V0.73-3: The 'state number generator' code in pdp11_sequencer causes
|
- V0.73-3: The 'state number generator' code in pdp11_sequencer causes
|
in vivado 2016.1 (and .2) that the main FSM isn't re-coded anymore,
|
in vivado 2016.1 (and .2) that the main FSM isn't re-coded anymore,
|
which has high impact on achievable clock rate. The two optional
|
which has high impact on achievable clock rate. The two optional
|
debug units depending on the state number, dmscnt and dmcmon, are
|
debug units depending on the state number, dmscnt and dmcmon, are
|
therefore currently deactivated in all Artix based systems (but are
|
therefore currently deactivated in all Artix based systems (but are
|
available on all Spartan based systems).
|
available on all Spartan based systems).
|
|
|
- trunk (2016-03-19: svn rev 35(oc) 746(wfjm); untagged w11a_V0.72) +++++++++
|
- trunk (2016-03-19: svn rev 35(oc) 746(wfjm); untagged w11a_V0.72) +++++++++
|
- Preface
|
- Preface
|
- The new low-cost Digilent Arty board is a very attractive platform.
|
- The new low-cost Digilent Arty board is a very attractive platform.
|
The DDR3 memory will take some time to integrate, in this release thus
|
The DDR3 memory will take some time to integrate, in this release thus
|
only designs using the BRAMs.
|
only designs using the BRAMs.
|
- added support for the Vivado simulator. Simple test benches work fine.
|
- added support for the Vivado simulator. Simple test benches work fine.
|
Rlink based test benches don't work due to a bug in Vivado 2015.4.
|
Rlink based test benches don't work due to a bug in Vivado 2015.4.
|
- A rather esoteric CPU bug was fixed in release V0.71 but forgotten to
|
- A rather esoteric CPU bug was fixed in release V0.71 but forgotten to
|
mention in the README. See ECO-027-trap_mmu.txt for details.
|
mention in the README. See ECO-027-trap_mmu.txt for details.
|
|
|
- Summary
|
- Summary
|
- added Arty support. The w11a design uses BRAMs as memory, like the
|
- added Arty support. The w11a design uses BRAMs as memory, like the
|
Basys3 version. This gives 176 KByte memory, not enough for 2.11BSD,
|
Basys3 version. This gives 176 KByte memory, not enough for 2.11BSD,
|
but for many other less demanding OS available for a PDP11.
|
but for many other less demanding OS available for a PDP11.
|
- added support for SYSMON/XADC (see README_xadc.txt)
|
- added support for SYSMON/XADC (see README_xadc.txt)
|
- Vivado flow is now default for test benches of components and all Artix
|
- Vivado flow is now default for test benches of components and all Artix
|
based systems. If applicable an ISE flow is available under Makefile.ise
|
based systems. If applicable an ISE flow is available under Makefile.ise
|
(resolves known issues V0.64-4 and V0.64-5).
|
(resolves known issues V0.64-4 and V0.64-5).
|
- re-factored tbcore_rlink to support DPI and VHPI
|
- re-factored tbcore_rlink to support DPI and VHPI
|
- Vivado supports with DPI (from SystemVerilog) a mechanism to call
|
- Vivado supports with DPI (from SystemVerilog) a mechanism to call
|
external C code. The rlink test bench code so far relies on VHPI, which
|
external C code. The rlink test bench code so far relies on VHPI, which
|
is supported by ghdl, but not by ISE ISim or Vivado xsim. The code was
|
is supported by ghdl, but not by ISE ISim or Vivado xsim. The code was
|
restructured and can use now DPI or VHPI to support both ghdl and
|
restructured and can use now DPI or VHPI to support both ghdl and
|
Vivado. Unfortunately has Vivado 2015.4 a bug, DPI doesn't work in a
|
Vivado. Unfortunately has Vivado 2015.4 a bug, DPI doesn't work in a
|
mixed vhdl-verilog language environment (see Known issues), so the
|
mixed vhdl-verilog language environment (see Known issues), so the
|
code base is there, but utilization will habe to wait.
|
code base is there, but utilization will habe to wait.
|
- Vivado synthesis by default keeps hierarchy. This leads to doubly defined
|
- Vivado synthesis by default keeps hierarchy. This leads to doubly defined
|
modules if a component is used in both test bench and unit under test.
|
modules if a component is used in both test bench and unit under test.
|
To avoid this copies of s7_cmt_sfs and some serport_* modules were
|
To avoid this copies of s7_cmt_sfs and some serport_* modules were
|
created and are now used in the test benches.
|
created and are now used in the test benches.
|
|
|
- New features
|
- New features
|
- new directory trees for
|
- new directory trees for
|
- rtl/bplib/arty - board support files for arty
|
- rtl/bplib/arty - board support files for arty
|
- rtl/bplib/sysmon - driver + rbus iface for SYSMON/XADC
|
- rtl/bplib/sysmon - driver + rbus iface for SYSMON/XADC
|
- rtl/vlib/rlink/tbcore - new location for rlink tb iface code
|
- rtl/vlib/rlink/tbcore - new location for rlink tb iface code
|
- tools/tcl/rbsysmon - sysmon/xadc support
|
- tools/tcl/rbsysmon - sysmon/xadc support
|
- new modules
|
- new modules
|
- rtl/bplib/bpgen
|
- rtl/bplib/bpgen
|
- rgbdrv_* - driver + rbus iface for 3 color RGBLED
|
- rgbdrv_* - driver + rbus iface for 3 color RGBLED
|
- rtl/vlib/rlink/tbcore
|
- rtl/vlib/rlink/tbcore
|
- rlink_cext_iface_dpi.sv - DPI based cext iface
|
- rlink_cext_iface_dpi.sv - DPI based cext iface
|
- rlink_cext_iface_vhpi.vhd - VHPI based cext iface
|
- rlink_cext_iface_vhpi.vhd - VHPI based cext iface
|
- rlink_cext_dpi.c - dpi to vhpi adapter
|
- rlink_cext_dpi.c - dpi to vhpi adapter
|
- rtl/vlib/serport/tb
|
- rtl/vlib/serport/tb
|
- serport_uart_*_tb - added copies for tb usage
|
- serport_uart_*_tb - added copies for tb usage
|
- rtl/vlib/xlib/tb
|
- rtl/vlib/xlib/tb
|
- s7_cmt_sfs_tb - added copy for tb usage
|
- s7_cmt_sfs_tb - added copy for tb usage
|
|
|
- new files
|
- new files
|
- doc/man/man1
|
- doc/man/man1
|
- tbrun_tbw.1 - man file for tbrun_tbw
|
- tbrun_tbw.1 - man file for tbrun_tbw
|
- tbrun_tbwrri.1 - man file for tbrun_tbwrri
|
- tbrun_tbwrri.1 - man file for tbrun_tbwrri
|
- new systems
|
- new systems
|
- rtl/sys_gen/tst_rlink - rlink tester
|
- rtl/sys_gen/tst_rlink - rlink tester
|
- arty/sys_tst_rlink_arty - for Arty
|
- arty/sys_tst_rlink_arty - for Arty
|
- rtl/sys_gen/w11a - w11a
|
- rtl/sys_gen/w11a - w11a
|
- arty_bram/sys_w11a_br_arty - for Arty (BRAM only, 176 MByte)
|
- arty_bram/sys_w11a_br_arty - for Arty (BRAM only, 176 MByte)
|
|
|
- Changes
|
- Changes
|
- */.cvsignore - all ignore files re-organized
|
- */.cvsignore - all ignore files re-organized
|
- */tb/Makefile - Vivado now default, keep Makefile.ise
|
- */tb/Makefile - Vivado now default, keep Makefile.ise
|
- rtl/bplib/*/tb/tb_*.vhd - use s7_cmt_sfs_tb and serport_master_tb
|
- rtl/bplib/*/tb/tb_*.vhd - use s7_cmt_sfs_tb and serport_master_tb
|
- rtl/vlib/comlib
|
- rtl/vlib/comlib
|
- comlib.vhd - add work-around for vivado 2015.4 issue
|
- comlib.vhd - add work-around for vivado 2015.4 issue
|
- rtl/vlib/rbus
|
- rtl/vlib/rbus
|
- rb_sres_or_mon - supports 6 inputs now
|
- rb_sres_or_mon - supports 6 inputs now
|
- rtl/vlib/serport
|
- rtl/vlib/serport
|
- serport_master - moved to tb, _tb appended to name
|
- serport_master - moved to tb, _tb appended to name
|
- rtl/vlib/rlink/tbcore
|
- rtl/vlib/rlink/tbcore
|
- tbcore_rlink - re-structured to use rlink_cext_iface
|
- tbcore_rlink - re-structured to use rlink_cext_iface
|
- rtl/sys_gen/...
|
- rtl/sys_gen/...
|
- sys_tst_rlink_b3 - hardwire XON=1, support XADC
|
- sys_tst_rlink_b3 - hardwire XON=1, support XADC
|
- sys_tst_rlink_n4 - support XADC and RGBLEDs
|
- sys_tst_rlink_n4 - support XADC and RGBLEDs
|
- sys_w11a_b3 - hardwire XON=1, support XADC; 72 MHz now
|
- sys_w11a_b3 - hardwire XON=1, support XADC; 72 MHz now
|
- sys_w11a_n4 - support XADC
|
- sys_w11a_n4 - support XADC
|
- tools/bin
|
- tools/bin
|
- tbrun_tbw - add vivado xsim and Makefile.ise support
|
- tbrun_tbw - add vivado xsim and Makefile.ise support
|
- tbrun_tbwrri - use --sxon and --hxon instead of --xon
|
- tbrun_tbwrri - use --sxon and --hxon instead of --xon
|
- tbw - add XSim support
|
- tbw - add XSim support
|
- ti_w11 - add arty support, add -fx
|
- ti_w11 - add arty support, add -fx
|
- vbomconv - add [ise,viv]; add @uut tag handling;
|
- vbomconv - add [ise,viv]; add @uut tag handling;
|
add preliminary --(vsyn|vsim)_export;
|
add preliminary --(vsyn|vsim)_export;
|
add vivado xsim support;
|
add vivado xsim support;
|
- xtwi,xtwv - add BARE_PATH to provide clean environment
|
- xtwi,xtwv - add BARE_PATH to provide clean environment
|
|
|
- Bug fixes
|
- Bug fixes
|
- tools/tcl/rutil
|
- tools/tcl/rutil
|
- regdsc.tcl - regdsc: fix variable name in error msg
|
- regdsc.tcl - regdsc: fix variable name in error msg
|
|
|
- Known issues
|
- Known issues
|
- all issues: see README_known_issues.txt
|
- all issues: see README_known_issues.txt
|
- resolved issues:
|
- resolved issues:
|
- V0.64-4: support added for Vivado xsim. See however issue V0.72-1+2.
|
- V0.64-4: support added for Vivado xsim. See however issue V0.72-1+2.
|
- V0.64-5: w11a_tb_guide.txt covers xsim tests too.
|
- V0.64-5: w11a_tb_guide.txt covers xsim tests too.
|
|
|
- new issues:
|
- new issues:
|
- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied
|
- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied
|
vhdl-verilog language environment. This prevents currently to
|
vhdl-verilog language environment. This prevents currently to
|
build a xsim simulation model for rlink based test benches.
|
build a xsim simulation model for rlink based test benches.
|
- V0.72-2: xsim simulations with timing annotation not yet available.
|
- V0.72-2: xsim simulations with timing annotation not yet available.
|
|
|
- trunk (2015-12-30: svn rev 34(oc) 722(wfjm); untagged w11a_V0.71) +++++++++
|
- trunk (2015-12-30: svn rev 34(oc) 722(wfjm); untagged w11a_V0.71) +++++++++
|
- Preface
|
- Preface
|
- the w11a so far lacked any 'hardware debugger' support, which made the
|
- the w11a so far lacked any 'hardware debugger' support, which made the
|
debugging of CPU core issues a bit tedious. This release added a first
|
debugging of CPU core issues a bit tedious. This release added a first
|
implementation of CPU debugger and monitoring features
|
implementation of CPU debugger and monitoring features
|
- dmhbpt: hardware break point unit. Allows to set multiple break points
|
- dmhbpt: hardware break point unit. Allows to set multiple break points
|
on instruction fetches (thus code break points) and on data
|
on instruction fetches (thus code break points) and on data
|
reads/writes (thus data access break points). The number of
|
reads/writes (thus data access break points). The number of
|
breakpoints is configurable between 0 and 4, in current
|
breakpoints is configurable between 0 and 4, in current
|
designs 2 are available
|
designs 2 are available
|
- dmcmon: CPU state monitor. A buffer of configurable size which holds
|
- dmcmon: CPU state monitor. A buffer of configurable size which holds
|
a wide range of information on execution of the most recent
|
a wide range of information on execution of the most recent
|
instructions. Tracing can be a instruction as well as on
|
instructions. Tracing can be a instruction as well as on
|
micro cycle level.
|
micro cycle level.
|
- dmscnt: micro state counter. A counter array which allows to monitor
|
- dmscnt: micro state counter. A counter array which allows to monitor
|
in which micro state the CPU time is spend, separated for
|
in which micro state the CPU time is spend, separated for
|
kernel and supervisor/user mode.
|
kernel and supervisor/user mode.
|
These three units together with the already existing ibus monitor allow
|
These three units together with the already existing ibus monitor allow
|
a very detailed and specific monitoring and debugging of the CPU.
|
a very detailed and specific monitoring and debugging of the CPU.
|
|
|
The w11a CPU core is not functionally modified in this release, the only
|
The w11a CPU core is not functionally modified in this release, the only
|
exception is the suspend logic needed to implement hardware break points.
|
exception is the suspend logic needed to implement hardware break points.
|
Both the hardware break point and the instruction level tracing in dmcmon
|
Both the hardware break point and the instruction level tracing in dmcmon
|
require a clean definition of instruction boundaries, which the current
|
require a clean definition of instruction boundaries, which the current
|
w11a core does not provide in some cases. This leads to imprecise
|
w11a core does not provide in some cases. This leads to imprecise
|
breakpoints (CPU executes one additional instruction) and incomplete
|
breakpoints (CPU executes one additional instruction) and incomplete
|
dmcmon traces (at instruction level when exceptions are taken).
|
dmcmon traces (at instruction level when exceptions are taken).
|
|
|
The w11a core will be modified in the next release to handle the above
|
The w11a core will be modified in the next release to handle the above
|
mentioned conditions properly. The dmhbpt and dmcmon will be fully
|
mentioned conditions properly. The dmhbpt and dmcmon will be fully
|
documented when the w11a core changes are done, they work as expected
|
documented when the w11a core changes are done, they work as expected
|
under all conditions, and the full back end integration is completed.
|
under all conditions, and the full back end integration is completed.
|
|
|
- bottom line is that this release has little added value for normal w11
|
- bottom line is that this release has little added value for normal w11
|
usage. It is technically necessary to separate the addition of all
|
usage. It is technically necessary to separate the addition of all
|
the debug units and modification of the CPU core into two releases.
|
the debug units and modification of the CPU core into two releases.
|
|
|
- Summary
|
- Summary
|
- new reference system
|
- new reference system
|
- switched to Vivado 2015.4 (from 2014.4)
|
- switched to Vivado 2015.4 (from 2014.4)
|
Note: 2015.4 has WebPACK support for Logic Analyser and HLS. Both are
|
Note: 2015.4 has WebPACK support for Logic Analyser and HLS. Both are
|
not used so far, but the logic analyser may come in handy soon.
|
not used so far, but the logic analyser may come in handy soon.
|
- switched to tcl8.6 (from tcl8.5)
|
- switched to tcl8.6 (from tcl8.5)
|
Note: tcl8.6 is default tcl in Ubuntu 2014.04LTS, but up to now the
|
Note: tcl8.6 is default tcl in Ubuntu 2014.04LTS, but up to now the
|
tclshcpp helper was linked against tcl8.5. So far no tcl8.6
|
tclshcpp helper was linked against tcl8.5. So far no tcl8.6
|
langauge features are used, but may be in future.
|
langauge features are used, but may be in future.
|
|
|
- New features
|
- New features
|
- new modules
|
- new modules
|
- rtl/w11a
|
- rtl/w11a
|
- pdp11_dmcmon - pdp11: debug&moni: cpu monitor
|
- pdp11_dmcmon - pdp11: debug&moni: cpu monitor
|
- pdp11_dmhbpt - pdp11: debug&moni: hardware breakpoint
|
- pdp11_dmhbpt - pdp11: debug&moni: hardware breakpoint
|
- pdp11_dmhbpt_unit - pdp11: dmhbpt - individual unit
|
- pdp11_dmhbpt_unit - pdp11: dmhbpt - individual unit
|
- pdp11_dmscnt - pdp11: debug&moni: state counter
|
- pdp11_dmscnt - pdp11: debug&moni: state counter
|
- new files
|
- new files
|
- tools/bin
|
- tools/bin
|
- dmscntanal - analyze dmscnt data
|
- dmscntanal - analyze dmscnt data
|
- dmscntconv - convert dmscnt data
|
- dmscntconv - convert dmscnt data
|
- tools/asm-11/lib
|
- tools/asm-11/lib
|
- defs_mmu.mac - definitions for mmu registers
|
- defs_mmu.mac - definitions for mmu registers
|
- defs_nzvc.mac - definitions for condition code combos
|
- defs_nzvc.mac - definitions for condition code combos
|
- defs_reg70.mac - definitions for 11/70 CPU registers
|
- defs_reg70.mac - definitions for 11/70 CPU registers
|
- tcode_std_base.mac - Default tcode base code for simple tests
|
- tcode_std_base.mac - Default tcode base code for simple tests
|
- tcode_std_start.mac - Default tcode startup code
|
- tcode_std_start.mac - Default tcode startup code
|
- vec_devcatch.mac - vector catcher for device interrupts
|
- vec_devcatch.mac - vector catcher for device interrupts
|
- vec_devcatch_reset.mac - re-write vector catcher
|
- vec_devcatch_reset.mac - re-write vector catcher
|
- tools/tbench
|
- tools/tbench
|
- w11a_cmon - directory with dmcmon tests
|
- w11a_cmon - directory with dmcmon tests
|
- w11a_hbpt - directory with dmhbpt tests
|
- w11a_hbpt - directory with dmhbpt tests
|
- tools/tcl
|
- tools/tcl
|
- ibd_(dl|lp|pc|rk|rl)11 - directory with register regdsc's
|
- ibd_(dl|lp|pc|rk|rl)11 - directory with register regdsc's
|
- tools/tcl/rutil
|
- tools/tcl/rutil
|
- fileio.tcl - new tofile and fromfile procs
|
- fileio.tcl - new tofile and fromfile procs
|
- tools/tcl/rw11
|
- tools/tcl/rw11
|
- dmcmon.tcl - support code for dmcmon
|
- dmcmon.tcl - support code for dmcmon
|
- dmhbpt.tcl - support code for dmhbpt
|
- dmhbpt.tcl - support code for dmhbpt
|
- dmscnt.tcl - support code for dmscnt
|
- dmscnt.tcl - support code for dmscnt
|
- shell.tcl - new w11a tcl shell
|
- shell.tcl - new w11a tcl shell
|
- shell_egd.tcl - code for e,g,d commands
|
- shell_egd.tcl - code for e,g,d commands
|
- tools/tcl/rw11util
|
- tools/tcl/rw11util
|
- regmap.tcl - support for 'map of regdsc' definitions
|
- regmap.tcl - support for 'map of regdsc' definitions
|
|
|
- Changes
|
- Changes
|
- rtl/vlib/rlink
|
- rtl/vlib/rlink
|
- rlink_core.vhd - add proc_sres: strip 'x' from RB_SRES.dout
|
- rlink_core.vhd - add proc_sres: strip 'x' from RB_SRES.dout
|
- rtl/vlib/rlink/tb
|
- rtl/vlib/rlink/tb
|
- tbcore_rlink - drive SB_CNTL from start to avoid 'U'
|
- tbcore_rlink - drive SB_CNTL from start to avoid 'U'
|
- rtl/w11a
|
- rtl/w11a
|
- pdp11 - add defs for pdp11_dm(scnt|hbpt|cmon)
|
- pdp11 - add defs for pdp11_dm(scnt|hbpt|cmon)
|
- pdp11_* - add support for pdp11_dm(scnt|hbpt|cmon)
|
- pdp11_* - add support for pdp11_dm(scnt|hbpt|cmon)
|
- rtl/sys_gen/w11a/*
|
- rtl/sys_gen/w11a/*
|
- sys_conf - add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
|
- sys_conf - add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
|
- rtl/sys_gen/w11a/*/tb
|
- rtl/sys_gen/w11a/*/tb
|
- sys_conf_sim - add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
|
- sys_conf_sim - add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
|
- tools/bin/
|
- tools/bin/
|
- ti_w11 - add -ghw option
|
- ti_w11 - add -ghw option
|
- tmuconv - fix '.' handling for br/sob instructions
|
- tmuconv - fix '.' handling for br/sob instructions
|
correct xor (now r,dst, and not src,r)
|
correct xor (now r,dst, and not src,r)
|
- tools/tcl/rutil
|
- tools/tcl/rutil
|
- regdsc.tcl - add regbldkv,reggetkv
|
- regdsc.tcl - add regbldkv,reggetkv
|
- util.tcl - rename optlist2arr->args2opts, new logic
|
- util.tcl - rename optlist2arr->args2opts, new logic
|
- tools/tcl/rw11
|
- tools/tcl/rw11
|
- asm.tcl - new arg list format in asm(run|treg|tmem)
|
- asm.tcl - new arg list format in asm(run|treg|tmem)
|
- dasm.tcl - add dasm_inst2txt
|
- dasm.tcl - add dasm_inst2txt
|
- tools/tcl/ibd_ibmon
|
- tools/tcl/ibd_ibmon
|
- util.tcl - add symbolic register dump
|
- util.tcl - add symbolic register dump
|
|
|
- Bug fixes
|
- Bug fixes
|
- rtl/bplib/micron
|
- rtl/bplib/micron
|
- mt45w8mw16b - fix issue when 1st access is to addr 0
|
- mt45w8mw16b - fix issue when 1st access is to addr 0
|
- rtl/bplib/nxcramlib
|
- rtl/bplib/nxcramlib
|
- nx_cram_memctl_as - always define imem_oe in do_dispatch()
|
- nx_cram_memctl_as - always define imem_oe in do_dispatch()
|
- rtl/ibus
|
- rtl/ibus
|
- ibdr_tm11 - add missing BESET to sensitivity list
|
- ibdr_tm11 - add missing BESET to sensitivity list
|
- rtl/w11a
|
- rtl/w11a
|
- pdp11_sequencer - proper trap_mmu and trap_ysv handling
|
- pdp11_sequencer - proper trap_mmu and trap_ysv handling
|
- tools/bin
|
- tools/bin
|
- asm-11 - fix '.' handling in instructions
|
- asm-11 - fix '.' handling in instructions
|
|
|
- Known issues
|
- Known issues
|
- all issues: see README_known_issues.txt
|
- all issues: see README_known_issues.txt
|
|
|
- w11a_V0.7 (2015-06-21) +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
- w11a_V0.7 (2015-06-21) +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
cummulative summary of key changes from w11a_V0.6 to w11a_V0.7
|
cummulative summary of key changes from w11a_V0.6 to w11a_V0.7
|
- Bugfix for DIV instruction (in w11a_V0.61, see ECO-026-div.txt)
|
- Bugfix for DIV instruction (in w11a_V0.61, see ECO-026-div.txt)
|
- revised rbus protocol V4 (in w11a_V0.62, see README_Rlink_V4.txt)
|
- revised rbus protocol V4 (in w11a_V0.62, see README_Rlink_V4.txt)
|
- add basic Vivado support (in w11a_V0.64)
|
- add basic Vivado support (in w11a_V0.64)
|
- add Nexys4 and Basys3 port of w11a (in w11a_V0.64)
|
- add Nexys4 and Basys3 port of w11a (in w11a_V0.64)
|
- add RL11/RL02 disk support (in w11a_V0.64)
|
- add RL11/RL02 disk support (in w11a_V0.64)
|
- add RH70+RP/RM disk support (in w11a_V0.65)
|
- add RH70+RP/RM disk support (in w11a_V0.65)
|
- add TM11/TY10 tape support (in w11a_V0.66)
|
- add TM11/TY10 tape support (in w11a_V0.66)
|
- reference system now ISE 14.7, Vivado 2014.4; Ubuntu 14.04 64 bit, ghdl 0.31
|
- reference system now ISE 14.7, Vivado 2014.4; Ubuntu 14.04 64 bit, ghdl 0.31
|
|
|
for details see README-w11a_V.60-w11a_V0.70.txt
|
for details see README-w11a_V.60-w11a_V0.70.txt
|
|
|
- w11a_V0.6 (2014-06-06) +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
- w11a_V0.6 (2014-06-06) +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
cummulative summary of key changes from w11a_V0.5 to w11a_V0.6
|
cummulative summary of key changes from w11a_V0.5 to w11a_V0.6
|
- revised ibus protocol V2 (in w11a_V0.51)
|
- revised ibus protocol V2 (in w11a_V0.51)
|
- revised rbus protocol V3 (in w11a_V0.52)
|
- revised rbus protocol V3 (in w11a_V0.52)
|
- backend server rewritten in C++ and Tcl (in w11a_V0.53 and w11a_V0.562)
|
- backend server rewritten in C++ and Tcl (in w11a_V0.53 and w11a_V0.562)
|
- add Nexys3 port of w11a (in w11a_V0.54)
|
- add Nexys3 port of w11a (in w11a_V0.54)
|
- add Cypress FX2 support (in w11a_V0.56 and w11a_V0.57)
|
- add Cypress FX2 support (in w11a_V0.56 and w11a_V0.57)
|
- added LP11,PC11 support (in w11a_V0.58)
|
- added LP11,PC11 support (in w11a_V0.58)
|
- reference system now ISE 14.7 and Ubuntu 12.04 64 bit, ghdl 0.31
|
- reference system now ISE 14.7 and Ubuntu 12.04 64 bit, ghdl 0.31
|
- many code cleanups; use numeric_std
|
- many code cleanups; use numeric_std
|
- many documentation improvements
|
- many documentation improvements
|
- development status upgraded to beta (from alpha)
|
- development status upgraded to beta (from alpha)
|
|
|
for details see README-w11a_V.50-w11a_V0.60.txt
|
for details see README-w11a_V.50-w11a_V0.60.txt
|
|
|
- w11a_V0.5 (2010-07-23) +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
- w11a_V0.5 (2010-07-23) +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
Initial release with
|
Initial release with
|
- w11a CPU core
|
- w11a CPU core
|
- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
|
- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
|
- just for fun: iist (not fully implemented and tested yet)
|
- just for fun: iist (not fully implemented and tested yet)
|
- two complete system configurations with
|
- two complete system configurations with
|
- for a Digilent S3board rtl/sys_gen/w11a/s3board/sys_w11a_s3
|
- for a Digilent S3board rtl/sys_gen/w11a/s3board/sys_w11a_s3
|
- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2
|
- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2
|
|
|
