-- $Id: pdp11_dmscnt.vhd 784 2016-07-09 22:17:01Z mueller $
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-- $Id: pdp11_dmscnt.vhd 784 2016-07-09 22:17:01Z mueller $
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--
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--
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-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: pdp11_dmscnt - syn
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-- Module Name: pdp11_dmscnt - syn
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-- Description: pdp11: debug&moni: state counter
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-- Description: pdp11: debug&moni: state counter
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--
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--
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
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-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-06-26 695 14.7 131013 xc6slx16-2 91 107 0 41 s 5.4
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-- 2015-06-26 695 14.7 131013 xc6slx16-2 91 107 0 41 s 5.4
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--
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--
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-- Revision History: -
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-- Revision History: -
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
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-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
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-- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt;
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-- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt;
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-- 2015-07-19 702 1.0 Initial version
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-- 2015-07-19 702 1.0 Initial version
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-- 2015-06-26 695 1.0 First draft
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-- 2015-06-26 695 1.0 First draft
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- rbus registers:
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-- rbus registers:
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--
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--
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-- Addr Bits Name r/w/f Function
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-- Addr Bits Name r/w/f Function
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--
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--
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-- 00 cntl r/w/- control
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-- 00 cntl r/w/- control
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-- 01 clr r/w/- if 1 starts mem clear
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-- 01 clr r/w/- if 1 starts mem clear
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-- 00 ena r/w/- if 1 enables counting
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-- 00 ena r/w/- if 1 enables counting
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-- 01 addr r/w/- memory address
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-- 01 addr r/w/- memory address
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-- 10:02 laddr r/w/- line address (state number)
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-- 10:02 laddr r/w/- line address (state number)
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-- 01:00 waddr r/-/- word address (cleared on write)
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-- 01:00 waddr r/-/- word address (cleared on write)
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-- 10 15:00 data r/-/- memory data
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-- 10 15:00 data r/-/- memory data
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.rblib.all;
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use work.rblib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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entity pdp11_dmscnt is -- debug&moni: state counter
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entity pdp11_dmscnt is -- debug&moni: state counter
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generic (
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generic (
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RB_ADDR : slv16 := slv(to_unsigned(16#0040#,16)));
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RB_ADDR : slv16 := slv(to_unsigned(16#0040#,16)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_SRES : out rb_sres_type; -- rbus: response
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DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
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DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
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DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
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DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
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DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
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DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
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);
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);
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end pdp11_dmscnt;
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end pdp11_dmscnt;
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architecture syn of pdp11_dmscnt is
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architecture syn of pdp11_dmscnt is
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constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
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constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
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constant rbaddr_addr : slv2 := "01"; -- addr address offset
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constant rbaddr_addr : slv2 := "01"; -- addr address offset
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constant rbaddr_data : slv2 := "10"; -- data address offset
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constant rbaddr_data : slv2 := "10"; -- data address offset
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constant cntl_rbf_clr : integer := 1;
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constant cntl_rbf_clr : integer := 1;
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constant cntl_rbf_ena : integer := 0;
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constant cntl_rbf_ena : integer := 0;
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subtype addr_rbf_mem is integer range 10 downto 2;
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subtype addr_rbf_mem is integer range 10 downto 2;
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subtype addr_rbf_word is integer range 1 downto 0;
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subtype addr_rbf_word is integer range 1 downto 0;
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: rbus access or count
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s_idle, -- s_idle: rbus access or count
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s_mread -- s_mread: memory read
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s_mread -- s_mread: memory read
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);
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);
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type regs_type is record
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type regs_type is record
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state : state_type; -- state
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state : state_type; -- state
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rbsel : slbit; -- rbus select
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rbsel : slbit; -- rbus select
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clr : slbit; -- clr flag
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clr : slbit; -- clr flag
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ena0 : slbit; -- ena flag
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ena0 : slbit; -- ena flag
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ena1 : slbit; -- ena flag (delayed)
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ena1 : slbit; -- ena flag (delayed)
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snum0 : slv9; -- snum stage 0
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snum0 : slv9; -- snum stage 0
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snum1 : slv9; -- snum stage 1
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snum1 : slv9; -- snum stage 1
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same : slbit; -- same snum flag
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same : slbit; -- same snum flag
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laddr : slv9; -- line addr
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laddr : slv9; -- line addr
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waddr : slv2; -- word addr
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waddr : slv2; -- word addr
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scnt : slv(35 downto 0); -- scnt buffer
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scnt : slv(35 downto 0); -- scnt buffer
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mbuf : slv20; -- lsb memory buffer
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mbuf : slv20; -- lsb memory buffer
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle, -- state
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s_idle, -- state
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'0', -- rbsel
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'0', -- rbsel
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'0','0','0', -- clr,ena0,ena1
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'0','0','0', -- clr,ena0,ena1
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(others=>'0'), -- snum0
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(others=>'0'), -- snum0
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(others=>'0'), -- snum1
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(others=>'0'), -- snum1
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'0', -- same
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'0', -- same
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(others=>'0'), -- laddr
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(others=>'0'), -- laddr
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(others=>'0'), -- waddr
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(others=>'0'), -- waddr
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(others=>'0'), -- scnt
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(others=>'0'), -- scnt
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(others=>'0') -- mbuf
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(others=>'0') -- mbuf
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);
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);
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signal R_REGS : regs_type := regs_init;
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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signal CMEM_CEA : slbit := '0';
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signal CMEM_CEA : slbit := '0';
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signal CMEM_CEB : slbit := '0';
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signal CMEM_CEB : slbit := '0';
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signal CMEM_WEA : slbit := '0';
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signal CMEM_WEA : slbit := '0';
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signal CMEM_WEB : slbit := '0';
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signal CMEM_WEB : slbit := '0';
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signal CMEM_ADDRA : slv9 := (others=>'0');
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signal CMEM_ADDRA : slv9 := (others=>'0');
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signal CMEM_DIB : slv(35 downto 0) := (others=>'0');
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signal CMEM_DIB : slv(35 downto 0) := (others=>'0');
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signal CMEM_DOA : slv(35 downto 0) := (others=>'0');
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signal CMEM_DOA : slv(35 downto 0) := (others=>'0');
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constant cmem_data_zero : slv(35 downto 0) := (others=>'0');
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constant cmem_data_zero : slv(35 downto 0) := (others=>'0');
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begin
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begin
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CMEM : ram_2swsr_rfirst_gen
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CMEM : ram_2swsr_rfirst_gen
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generic map (
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generic map (
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AWIDTH => 9,
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AWIDTH => 9,
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DWIDTH => 36)
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DWIDTH => 36)
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port map (
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port map (
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CLKA => CLK,
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CLKA => CLK,
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CLKB => CLK,
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CLKB => CLK,
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ENA => CMEM_CEA,
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ENA => CMEM_CEA,
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ENB => CMEM_CEB,
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ENB => CMEM_CEB,
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WEA => CMEM_WEA,
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WEA => CMEM_WEA,
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WEB => CMEM_WEB,
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WEB => CMEM_WEB,
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ADDRA => CMEM_ADDRA,
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ADDRA => CMEM_ADDRA,
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ADDRB => R_REGS.snum1,
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ADDRB => R_REGS.snum1,
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DIA => cmem_data_zero,
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DIA => cmem_data_zero,
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DIB => CMEM_DIB,
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DIB => CMEM_DIB,
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DOA => CMEM_DOA,
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DOA => CMEM_DOA,
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DOB => open
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DOB => open
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
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proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
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DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
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DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
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DM_STAT_CO, CMEM_DOA)
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DM_STAT_CO, CMEM_DOA)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irb_ack : slbit := '0';
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variable irb_ack : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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variable irb_dout : slv16 := (others=>'0');
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variable irbena : slbit := '0';
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variable irbena : slbit := '0';
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variable icea : slbit := '0';
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variable icea : slbit := '0';
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variable iwea : slbit := '0';
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variable iwea : slbit := '0';
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variable iweb : slbit := '0';
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variable iweb : slbit := '0';
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variable iaddra : slv9 := (others=>'0');
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variable iaddra : slv9 := (others=>'0');
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variable iscnt0 : slv(35 downto 0) := (others=>'0');
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variable iscnt0 : slv(35 downto 0) := (others=>'0');
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variable iscnt1 : slv(35 downto 0) := (others=>'0');
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variable iscnt1 : slv(35 downto 0) := (others=>'0');
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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irb_ack := '0';
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irb_ack := '0';
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irb_busy := '0';
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irb_busy := '0';
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irb_err := '0';
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irb_err := '0';
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irb_dout := (others=>'0');
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irb_dout := (others=>'0');
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irbena := RB_MREQ.re or RB_MREQ.we;
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irbena := RB_MREQ.re or RB_MREQ.we;
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icea := '0';
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icea := '0';
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iwea := '0';
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iwea := '0';
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iweb := '0';
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iweb := '0';
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iaddra := r.snum0;
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iaddra := r.snum0;
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-- rbus address decoder
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-- rbus address decoder
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n.rbsel := '0';
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n.rbsel := '0';
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if RB_MREQ.aval='1' then
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if RB_MREQ.aval='1' then
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if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
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if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
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n.rbsel := '1';
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n.rbsel := '1';
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end if;
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end if;
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end if;
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end if;
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case r.state is
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case r.state is
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when s_idle => -- s_idle: rbus access or count ------
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when s_idle => -- s_idle: rbus access or count ------
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-- rbus transactions
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-- rbus transactions
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if r.rbsel = '1' then
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if r.rbsel = '1' then
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irb_ack := irbena; -- ack all accesses
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irb_ack := irbena; -- ack all accesses
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case RB_MREQ.addr(1 downto 0) is
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case RB_MREQ.addr(1 downto 0) is
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when rbaddr_cntl => -- cntl ------------------
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when rbaddr_cntl => -- cntl ------------------
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if RB_MREQ.we = '1' then
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if RB_MREQ.we = '1' then
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n.clr := RB_MREQ.din(cntl_rbf_clr);
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n.clr := RB_MREQ.din(cntl_rbf_clr);
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if RB_MREQ.din(cntl_rbf_clr) = '1' then -- if clr set
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if RB_MREQ.din(cntl_rbf_clr) = '1' then -- if clr set
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n.laddr := (others=>'0'); -- reset mem addr
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n.laddr := (others=>'0'); -- reset mem addr
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end if;
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end if;
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n.ena0 := RB_MREQ.din(cntl_rbf_ena);
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n.ena0 := RB_MREQ.din(cntl_rbf_ena);
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end if;
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end if;
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when rbaddr_addr => -- addr ------------------
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when rbaddr_addr => -- addr ------------------
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if RB_MREQ.we = '1' then
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if RB_MREQ.we = '1' then
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if r.clr = '1' then -- if clr active
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if r.clr = '1' then -- if clr active
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irb_err := '1'; -- block addr writes
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irb_err := '1'; -- block addr writes
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else -- otherwise
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else -- otherwise
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n.laddr := RB_MREQ.din(addr_rbf_mem); -- set mem addr
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n.laddr := RB_MREQ.din(addr_rbf_mem); -- set mem addr
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n.waddr := (others=>'0'); -- clr word addr
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n.waddr := (others=>'0'); -- clr word addr
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end if;
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end if;
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end if;
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end if;
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when rbaddr_data => -- data ------------------
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when rbaddr_data => -- data ------------------
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if RB_MREQ.we = '1' then -- writes not allowed
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if RB_MREQ.we = '1' then -- writes not allowed
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irb_err := '1';
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irb_err := '1';
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end if;
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end if;
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if RB_MREQ.re = '1' then
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if RB_MREQ.re = '1' then
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if r.clr = '1' then -- if clr active
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if r.clr = '1' then -- if clr active
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irb_err := '1'; -- block data reads
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irb_err := '1'; -- block data reads
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else -- otherwise
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else -- otherwise
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case r.waddr is -- handle word addr
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case r.waddr is -- handle word addr
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when "00" => -- 1st access
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when "00" => -- 1st access
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icea := '1'; -- enable mem read
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icea := '1'; -- enable mem read
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iaddra := r.laddr; -- of current line
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iaddra := r.laddr; -- of current line
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irb_busy := '1';
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irb_busy := '1';
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n.state := s_mread;
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n.state := s_mread;
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when "01" => -- 2nd part
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when "01" => -- 2nd part
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n.waddr := "10"; -- inc word addr
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n.waddr := "10"; -- inc word addr
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when "10" => -- 3rd part
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when "10" => -- 3rd part
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n.waddr := "00"; -- wrap to next line
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n.waddr := "00"; -- wrap to next line
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n.laddr := slv(unsigned(r.laddr) + 1);
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n.laddr := slv(unsigned(r.laddr) + 1);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
|
end if;
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end if;
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|
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when others => -- <> --------------------
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when others => -- <> --------------------
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irb_err := '1';
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irb_err := '1';
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end case;
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end case;
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end if;
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end if;
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|
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when s_mread => --s_mread: memory read ---------------
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when s_mread => --s_mread: memory read ---------------
|
irb_ack := irbena; -- ack access
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irb_ack := irbena; -- ack access
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n.waddr := "01"; -- inc word addr
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n.waddr := "01"; -- inc word addr
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n.mbuf := CMEM_DOA(35 downto 16); -- capture msb part
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n.mbuf := CMEM_DOA(35 downto 16); -- capture msb part
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n.state := s_idle;
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n.state := s_idle;
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when others => null;
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when others => null;
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|
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end case;
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end case;
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|
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-- rbus output driver
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-- rbus output driver
|
if r.rbsel = '1' then
|
if r.rbsel = '1' then
|
case RB_MREQ.addr(1 downto 0) is
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case RB_MREQ.addr(1 downto 0) is
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when rbaddr_cntl => -- cntl ------------------
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when rbaddr_cntl => -- cntl ------------------
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irb_dout(cntl_rbf_clr) := r.clr;
|
irb_dout(cntl_rbf_clr) := r.clr;
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irb_dout(cntl_rbf_ena) := r.ena0;
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irb_dout(cntl_rbf_ena) := r.ena0;
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when rbaddr_addr => -- addr ------------------
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when rbaddr_addr => -- addr ------------------
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irb_dout(addr_rbf_mem) := r.laddr;
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irb_dout(addr_rbf_mem) := r.laddr;
|
irb_dout(addr_rbf_word) := r.waddr;
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irb_dout(addr_rbf_word) := r.waddr;
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when rbaddr_data => -- data ------------------
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when rbaddr_data => -- data ------------------
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case r.waddr is
|
case r.waddr is
|
when "00" => irb_dout := CMEM_DOA(15 downto 0);
|
when "00" => irb_dout := CMEM_DOA(15 downto 0);
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when "01" => irb_dout := r.mbuf(15 downto 0);
|
when "01" => irb_dout := r.mbuf(15 downto 0);
|
when "10" => irb_dout(3 downto 0) := r.mbuf(19 downto 16);
|
when "10" => irb_dout(3 downto 0) := r.mbuf(19 downto 16);
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- latch state number
|
-- latch state number
|
-- 1 msb determined from cpu mode: 0 if kernel and 1 when user or super
|
-- 1 msb determined from cpu mode: 0 if kernel and 1 when user or super
|
-- 8 lsb taken from sequencer snum
|
-- 8 lsb taken from sequencer snum
|
n.snum0(8) := '0';
|
n.snum0(8) := '0';
|
if DM_STAT_DP.psw.cmode /= c_psw_kmode then
|
if DM_STAT_DP.psw.cmode /= c_psw_kmode then
|
n.snum0(8) := '1';
|
n.snum0(8) := '1';
|
end if;
|
end if;
|
n.snum0(7 downto 0) := DM_STAT_SE.snum;
|
n.snum0(7 downto 0) := DM_STAT_SE.snum;
|
n.snum1 := r.snum0;
|
n.snum1 := r.snum0;
|
|
|
-- incrementer pipeline
|
-- incrementer pipeline
|
n.same := '0';
|
n.same := '0';
|
if r.snum0=r.snum1 and r.ena1 ='1' then -- in same state ?
|
if r.snum0=r.snum1 and r.ena1 ='1' then -- in same state ?
|
n.same := '1'; -- don't read mem and remember
|
n.same := '1'; -- don't read mem and remember
|
else -- otherwise
|
else -- otherwise
|
icea := '1'; -- enable mem read
|
icea := '1'; -- enable mem read
|
end if;
|
end if;
|
|
|
-- increment state count
|
-- increment state count
|
if r.same = '0' then -- was mem read ?
|
if r.same = '0' then -- was mem read ?
|
iscnt0 := CMEM_DOA; -- take memory value
|
iscnt0 := CMEM_DOA; -- take memory value
|
else -- otherwise
|
else -- otherwise
|
iscnt0 := r.scnt; -- use scnt reg
|
iscnt0 := r.scnt; -- use scnt reg
|
end if;
|
end if;
|
iscnt1 := slv(unsigned(iscnt0) + 1); -- increment
|
iscnt1 := slv(unsigned(iscnt0) + 1); -- increment
|
n.scnt := iscnt1; -- and store
|
n.scnt := iscnt1; -- and store
|
|
|
-- finally setup memory access
|
-- finally setup memory access
|
n.ena1 := r.ena0;
|
n.ena1 := r.ena0;
|
if r.clr = '1' then -- mem clear action
|
if r.clr = '1' then -- mem clear action
|
icea := '1';
|
icea := '1';
|
iwea := '1';
|
iwea := '1';
|
iaddra := r.laddr;
|
iaddra := r.laddr;
|
n.laddr := slv(unsigned(r.laddr) + 1);
|
n.laddr := slv(unsigned(r.laddr) + 1);
|
if r.laddr = "111111111" then
|
if r.laddr = "111111111" then
|
n.clr := '0';
|
n.clr := '0';
|
end if;
|
end if;
|
elsif r.ena1 = '1' then -- state count action
|
elsif r.ena1 = '1' then -- state count action
|
iweb := '1';
|
iweb := '1';
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
CMEM_CEA <= icea;
|
CMEM_CEA <= icea;
|
CMEM_CEB <= iweb;
|
CMEM_CEB <= iweb;
|
CMEM_WEA <= iwea;
|
CMEM_WEA <= iwea;
|
CMEM_WEB <= iweb;
|
CMEM_WEB <= iweb;
|
CMEM_ADDRA <= iaddra;
|
CMEM_ADDRA <= iaddra;
|
CMEM_DIB <= iscnt1;
|
CMEM_DIB <= iscnt1;
|
|
|
RB_SRES.ack <= irb_ack;
|
RB_SRES.ack <= irb_ack;
|
RB_SRES.err <= irb_err;
|
RB_SRES.err <= irb_err;
|
RB_SRES.busy <= irb_busy;
|
RB_SRES.busy <= irb_busy;
|
RB_SRES.dout <= irb_dout;
|
RB_SRES.dout <= irb_dout;
|
|
|
end process proc_next;
|
end process proc_next;
|
|
|
end syn;
|
end syn;
|
|
|