-- $Id: tbd_tba_pdp11core.vhd 698 2015-07-05 21:20:18Z mueller $
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-- $Id: tbd_tba_pdp11core.vhd 698 2015-07-05 21:20:18Z mueller $
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--
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--
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-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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-- for complete details.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: tbd_tba_pdp11core - syn
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-- Module Name: tbd_tba_pdp11core - syn
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-- Description: tbd for testing pdp11_core_rbus plus ibdr_minisys
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-- Description: tbd for testing pdp11_core_rbus plus ibdr_minisys
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--
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--
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-- Dependencies: genlib/clkdivce
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-- Dependencies: genlib/clkdivce
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-- pdp11_core_rbus
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-- pdp11_core_rbus
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-- pdp11_core
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-- pdp11_core
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-- pdp11_bram
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-- pdp11_bram
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-- ibus/ibdr_minisys
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-- ibus/ibdr_minisys
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-- rbus/rb_sres_or_2
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-- rbus/rb_sres_or_2
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--
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--
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-- Test bench: tb_rlink_tba_pdp11core
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-- Test bench: tb_rlink_tba_pdp11core
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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--
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--
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
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-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
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-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
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-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
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-- 2011-11-18 427 1.4.1 now numeric_std clean
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-- 2011-11-18 427 1.4.1 now numeric_std clean
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-- 2010-12-30 351 1.4 renamed from tbd_pdp11core_rri; rbv3 port;
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-- 2010-12-30 351 1.4 renamed from tbd_pdp11core_rri; rbv3 port;
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-- 2010-10-23 335 1.3.2 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.3.2 rename RRI_LAM->RB_LAM;
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-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
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-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
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-- remove pdp11_ibdr_rri
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-- remove pdp11_ibdr_rri
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-- 2010-06-11 303 1.3 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.3 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-05-02 287 1.2.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- 2010-05-02 287 1.2.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
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-- 2010-05-01 285 1.2 port to rri V2 interface
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-- 2010-05-01 285 1.2 port to rri V2 interface
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-- 2009-07-12 233 1.1.4 adapt to ibdr_minisys interface changes
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-- 2009-07-12 233 1.1.4 adapt to ibdr_minisys interface changes
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-- 2008-08-22 161 1.1.3 use iblib, ibdlib
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-- 2008-08-22 161 1.1.3 use iblib, ibdlib
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-- 2008-04-18 136 1.1.2 add RESET for ibdr_minisys
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-- 2008-04-18 136 1.1.2 add RESET for ibdr_minisys
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-- 2008-02-23 118 1.1.1 use sys_conf for bram size
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-- 2008-02-23 118 1.1.1 use sys_conf for bram size
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-- 2008-02-17 117 1.1 adapt to em_ core interface; use pdp11_bram
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-- 2008-02-17 117 1.1 adapt to em_ core interface; use pdp11_bram
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-- 2008-01-20 113 1.0 Initial version (factored out from rrirp_pdp11core,
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-- 2008-01-20 113 1.0 Initial version (factored out from rrirp_pdp11core,
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-- add rri access to ibdr now)
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-- add rri access to ibdr now)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.genlib.all;
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use work.genlib.all;
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use work.iblib.all;
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use work.iblib.all;
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use work.ibdlib.all;
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use work.ibdlib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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use work.sys_conf.all;
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use work.sys_conf.all;
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use work.rblib.all;
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use work.rblib.all;
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entity tbd_tba_pdp11core is -- tbd pdp11_core_rbus plus ibdr_minisys
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entity tbd_tba_pdp11core is -- tbd pdp11_core_rbus plus ibdr_minisys
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-- implements rbtba_aif
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-- implements rbtba_aif
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ_aval : in slbit; -- rbus: request - aval
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RB_MREQ_aval : in slbit; -- rbus: request - aval
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RB_MREQ_re : in slbit; -- rbus: request - re
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RB_MREQ_re : in slbit; -- rbus: request - re
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RB_MREQ_we : in slbit; -- rbus: request - we
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RB_MREQ_we : in slbit; -- rbus: request - we
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RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
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RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
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RB_MREQ_addr : in slv16; -- rbus: request - addr
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RB_MREQ_addr : in slv16; -- rbus: request - addr
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RB_MREQ_din : in slv16; -- rbus: request - din
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RB_MREQ_din : in slv16; -- rbus: request - din
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RB_SRES_ack : out slbit; -- rbus: response - ack
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RB_SRES_ack : out slbit; -- rbus: response - ack
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RB_SRES_busy : out slbit; -- rbus: response - busy
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RB_SRES_busy : out slbit; -- rbus: response - busy
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RB_SRES_err : out slbit; -- rbus: response - err
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RB_SRES_err : out slbit; -- rbus: response - err
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RB_SRES_dout : out slv16; -- rbus: response - dout
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RB_SRES_dout : out slv16; -- rbus: response - dout
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RB_LAM : out slv16; -- rbus: look at me
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RB_LAM : out slv16; -- rbus: look at me
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RB_STAT : out slv4 -- rbus: status flags
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RB_STAT : out slv4 -- rbus: status flags
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);
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);
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end entity tbd_tba_pdp11core;
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end entity tbd_tba_pdp11core;
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architecture syn of tbd_tba_pdp11core is
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architecture syn of tbd_tba_pdp11core is
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signal CE_USEC : slbit := '0';
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signal CE_USEC : slbit := '0';
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signal GRESET : slbit := '0';
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signal GRESET : slbit := '0';
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signal CP_CNTL : cp_cntl_type := cp_cntl_init;
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signal CP_CNTL : cp_cntl_type := cp_cntl_init;
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signal CP_ADDR : cp_addr_type := cp_addr_init;
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signal CP_ADDR : cp_addr_type := cp_addr_init;
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signal CP_DIN : slv16 := (others=>'0');
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signal CP_DIN : slv16 := (others=>'0');
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signal CP_STAT : cp_stat_type := cp_stat_init;
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signal CP_STAT : cp_stat_type := cp_stat_init;
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signal CP_DOUT : slv16 := (others=>'0');
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signal CP_DOUT : slv16 := (others=>'0');
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_MREQ : rb_mreq_type := rb_mreq_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
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signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
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signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
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signal EI_PRI : slv3 := (others=>'0');
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signal EI_PRI : slv3 := (others=>'0');
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signal EI_VECT : slv9_2 := (others=>'0');
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signal EI_VECT : slv9_2 := (others=>'0');
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signal EI_ACKM : slbit := '0';
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signal EI_ACKM : slbit := '0';
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signal EM_MREQ : em_mreq_type := em_mreq_init;
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signal EM_MREQ : em_mreq_type := em_mreq_init;
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signal EM_SRES : em_sres_type := em_sres_init;
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signal EM_SRES : em_sres_type := em_sres_init;
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signal BRESET : slbit := '0';
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signal BRESET : slbit := '0';
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signal IB_MREQ : ib_mreq_type := ib_mreq_init;
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signal IB_MREQ : ib_mreq_type := ib_mreq_init;
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signal IB_SRES : ib_sres_type := ib_sres_init;
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signal IB_SRES : ib_sres_type := ib_sres_init;
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begin
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begin
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RB_MREQ.aval <= RB_MREQ_aval;
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RB_MREQ.aval <= RB_MREQ_aval;
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RB_MREQ.re <= RB_MREQ_re;
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RB_MREQ.re <= RB_MREQ_re;
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RB_MREQ.we <= RB_MREQ_we;
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RB_MREQ.we <= RB_MREQ_we;
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RB_MREQ.init <= RB_MREQ_initt;
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RB_MREQ.init <= RB_MREQ_initt;
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RB_MREQ.addr <= RB_MREQ_addr;
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RB_MREQ.addr <= RB_MREQ_addr;
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RB_MREQ.din <= RB_MREQ_din;
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RB_MREQ.din <= RB_MREQ_din;
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RB_SRES_ack <= RB_SRES.ack;
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RB_SRES_ack <= RB_SRES.ack;
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RB_SRES_busy <= RB_SRES.busy;
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RB_SRES_busy <= RB_SRES.busy;
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RB_SRES_err <= RB_SRES.err;
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RB_SRES_err <= RB_SRES.err;
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RB_SRES_dout <= RB_SRES.dout;
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RB_SRES_dout <= RB_SRES.dout;
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CLKDIV : clkdivce
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CLKDIV : clkdivce
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generic map (
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generic map (
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CDUWIDTH => 6,
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CDUWIDTH => 6,
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USECDIV => 50,
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USECDIV => 50,
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MSECDIV => 1000)
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MSECDIV => 1000)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => open
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CE_MSEC => open
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);
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);
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RB2CP : pdp11_core_rbus
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RB2CP : pdp11_core_rbus
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generic map (
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generic map (
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RB_ADDR_CORE => slv(to_unsigned(16#0000#,16)),
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RB_ADDR_CORE => slv(to_unsigned(16#0000#,16)),
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RB_ADDR_IBUS => slv(to_unsigned(16#4000#,16)))
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RB_ADDR_IBUS => slv(to_unsigned(16#4000#,16)))
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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RB_MREQ => RB_MREQ,
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RB_MREQ => RB_MREQ,
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RB_SRES => RB_SRES_CPU,
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RB_SRES => RB_SRES_CPU,
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RB_STAT => RB_STAT,
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RB_STAT => RB_STAT,
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RB_LAM => RB_LAM(0),
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RB_LAM => RB_LAM(0),
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GRESET => GRESET,
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GRESET => GRESET,
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CP_CNTL => CP_CNTL,
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CP_CNTL => CP_CNTL,
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CP_ADDR => CP_ADDR,
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CP_ADDR => CP_ADDR,
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CP_DIN => CP_DIN,
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CP_DIN => CP_DIN,
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CP_STAT => CP_STAT,
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CP_STAT => CP_STAT,
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CP_DOUT => CP_DOUT
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CP_DOUT => CP_DOUT
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);
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);
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W11A : pdp11_core
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W11A : pdp11_core
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => GRESET,
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RESET => GRESET,
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CP_CNTL => CP_CNTL,
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CP_CNTL => CP_CNTL,
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CP_ADDR => CP_ADDR,
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CP_ADDR => CP_ADDR,
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CP_DIN => CP_DIN,
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CP_DIN => CP_DIN,
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CP_STAT => CP_STAT,
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CP_STAT => CP_STAT,
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CP_DOUT => CP_DOUT,
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CP_DOUT => CP_DOUT,
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ESUSP_O => open,
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ESUSP_O => open,
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ESUSP_I => '0',
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ESUSP_I => '0',
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ITIMER => open,
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ITIMER => open,
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HBPT => '0',
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HBPT => '0',
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EI_PRI => EI_PRI,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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EI_VECT => EI_VECT,
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EI_ACKM => EI_ACKM,
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EI_ACKM => EI_ACKM,
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EM_MREQ => EM_MREQ,
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EM_MREQ => EM_MREQ,
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EM_SRES => EM_SRES,
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EM_SRES => EM_SRES,
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BRESET => BRESET,
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BRESET => BRESET,
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IB_MREQ_M => IB_MREQ,
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IB_MREQ_M => IB_MREQ,
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IB_SRES_M => IB_SRES
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IB_SRES_M => IB_SRES
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);
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);
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MEM : pdp11_bram
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MEM : pdp11_bram
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generic map (
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generic map (
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AWIDTH => sys_conf_bram_awidth)
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AWIDTH => sys_conf_bram_awidth)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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GRESET => GRESET,
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GRESET => GRESET,
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EM_MREQ => EM_MREQ,
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EM_MREQ => EM_MREQ,
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EM_SRES => EM_SRES
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EM_SRES => EM_SRES
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);
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);
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IBDR_SYS : ibdr_minisys
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IBDR_SYS : ibdr_minisys
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
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CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
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RESET => GRESET,
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RESET => GRESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RB_LAM => RB_LAM(15 downto 1),
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RB_LAM => RB_LAM(15 downto 1),
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES,
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IB_SRES => IB_SRES,
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EI_ACKM => EI_ACKM,
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EI_ACKM => EI_ACKM,
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EI_PRI => EI_PRI,
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EI_PRI => EI_PRI,
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EI_VECT => EI_VECT,
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EI_VECT => EI_VECT,
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DISPREG => open
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DISPREG => open
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);
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);
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RB_SRES_OR : rb_sres_or_2
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RB_SRES_OR : rb_sres_or_2
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port map (
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port map (
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RB_SRES_1 => RB_SRES_CPU,
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RB_SRES_1 => RB_SRES_CPU,
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RB_SRES_2 => RB_SRES_IBD,
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RB_SRES_2 => RB_SRES_IBD,
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RB_SRES_OR => RB_SRES
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RB_SRES_OR => RB_SRES
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);
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);
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end syn;
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end syn;
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