; $Id: vec_cpucatch_reset.mac 710 2015-08-31 06:19:56Z mueller $
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; $Id: vec_cpucatch_reset.mac 710 2015-08-31 06:19:56Z mueller $
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; Copyright 2015- by Walter F.J. Mueller
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; Copyright 2015- by Walter F.J. Mueller
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; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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;
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;
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; re-write vector catcher for basic cpu interrupts
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; re-write vector catcher for basic cpu interrupts
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;
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;
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mov #v..iit+2,v..iit ; vec 4
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mov #v..iit+2,v..iit ; vec 4
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clr v..iit+2
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clr v..iit+2
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mov #v..rit+2,v..rit ; vec 10
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mov #v..rit+2,v..rit ; vec 10
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clr v..rit+2
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clr v..rit+2
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;
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;
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mov #v..bpt+2,v..bpt ; vec 14 (T bit; BPT)
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mov #v..bpt+2,v..bpt ; vec 14 (T bit; BPT)
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clr v..bpt+2
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clr v..bpt+2
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mov #v..iot+2,v..iot ; vec 20 (IOT)
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mov #v..iot+2,v..iot ; vec 20 (IOT)
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clr v..iot+2
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clr v..iot+2
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mov #v..pwr+2,v..pwr ; vec 24 (Power fail, not used)
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mov #v..pwr+2,v..pwr ; vec 24 (Power fail, not used)
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clr v..pwr+2
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clr v..pwr+2
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mov #v..emt+2,v..emt ; vec 30 (EMT)
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mov #v..emt+2,v..emt ; vec 30 (EMT)
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clr v..emt+2
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clr v..emt+2
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mov #v..trp+2,v..trp ; vec 34 (TRAP)
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mov #v..trp+2,v..trp ; vec 34 (TRAP)
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clr v..trp+2
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clr v..trp+2
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;
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;
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mov #v..pir+2,v..pir ; vec 240 (PIRQ)
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mov #v..pir+2,v..pir ; vec 240 (PIRQ)
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clr v..pir+2
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clr v..pir+2
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mov #v..fpp+2,v..fpp ; vec 244 (FPP)
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mov #v..fpp+2,v..fpp ; vec 244 (FPP)
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clr v..fpp+2
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clr v..fpp+2
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mov #v..mmu+2,v..mmu ; vec 250 (MMU)
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mov #v..mmu+2,v..mmu ; vec 250 (MMU)
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clr v..mmu+2
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clr v..mmu+2
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;
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;
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