#!/usr/bin/perl -w
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#!/usr/bin/perl -w
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# $Id: vbomconv 804 2016-08-28 17:33:50Z mueller $
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# $Id: vbomconv 804 2016-08-28 17:33:50Z mueller $
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#
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#
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# Copyright 2007-2016 by Walter F.J. Mueller
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# Copyright 2007-2016 by Walter F.J. Mueller
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#
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#
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# This program is free software; you may redistribute and/or modify it under
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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# Software Foundation, either version 2, or at your option any later version.
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#
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#
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# This program is distributed in the hope that it will be useful, but
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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# for complete details.
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2016-08-28 804 1.17.3 xsim work dir now xsim..
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# 2016-08-28 804 1.17.3 xsim work dir now xsim..
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# 2016-07-02 782 1.17.2 add VBOMCONV_GHDL_OPTS and VBOMCONV_GHDL_GCOV
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# 2016-07-02 782 1.17.2 add VBOMCONV_GHDL_OPTS and VBOMCONV_GHDL_GCOV
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# 2016-06-24 778 1.17.1 -vsyn_prj: add [rep]sim models & VBOMCONV_XSIM_LANG
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# 2016-06-24 778 1.17.1 -vsyn_prj: add [rep]sim models & VBOMCONV_XSIM_LANG
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# -ghdl_(i|m|a): use --workdir
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# -ghdl_(i|m|a): use --workdir
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# 2016-06-19 777 1.17 -vsyn_prj: sim and syn source sets based on -UUT
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# 2016-06-19 777 1.17 -vsyn_prj: sim and syn source sets based on -UUT
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# -vsim_prj: finally functioning tsim builds
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# -vsim_prj: finally functioning tsim builds
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# 2016-04-30 766 1.16.2 use -UUT property instead of @uut
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# 2016-04-30 766 1.16.2 use -UUT property instead of @uut
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# 2016-04-23 764 1.16.1 --vsim_prj: use 'nosort'
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# 2016-04-23 764 1.16.1 --vsim_prj: use 'nosort'
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# 2016-04-22 763 1.16 --vsim_prj: use bash+pipefail, check exit status
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# 2016-04-22 763 1.16 --vsim_prj: use bash+pipefail, check exit status
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# 2016-03-27 752 1.15 1st support for file properties (xdc -SCOPE_REF)
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# 2016-03-27 752 1.15 1st support for file properties (xdc -SCOPE_REF)
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# 2016-02-20 734 1.14 add [ise,viv]; add preliminary --(vsyn|vsim)_export;
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# 2016-02-20 734 1.14 add [ise,viv]; add preliminary --(vsyn|vsim)_export;
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# 2016-02-14 731 1.13 add @uut tag handling;
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# 2016-02-14 731 1.13 add @uut tag handling;
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# 2016-02-07 728 1.12 add vivado xsim support; protect for empty xdc set
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# 2016-02-07 728 1.12 add vivado xsim support; protect for empty xdc set
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# 2015-02-15 646 1.11 add vivado support: add -xlpath, use instead
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# 2015-02-15 646 1.11 add vivado support: add -xlpath, use instead
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# of XTWI_PATH; drop --ise_path; add @lib:unimacro;
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# of XTWI_PATH; drop --ise_path; add @lib:unimacro;
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# drop --viv_vhdl; add --vsyn_prj, --dep_vsyn;
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# drop --viv_vhdl; add --vsyn_prj, --dep_vsyn;
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# drop cygwin support;
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# drop cygwin support;
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# 2014-07-26 575 1.10.1 use XTWI_PATH now (ise/vivado switch done later)
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# 2014-07-26 575 1.10.1 use XTWI_PATH now (ise/vivado switch done later)
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# 2013-10-20 543 1.10 add --viv_vhdl
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# 2013-10-20 543 1.10 add --viv_vhdl
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# 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top
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# 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top
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# 2012-01-02 448 1.9.3 use in ghdl_m -fexplicit also when simprim used
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# 2012-01-02 448 1.9.3 use in ghdl_m -fexplicit also when simprim used
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# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used
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# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used
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# 2011-08-13 405 1.9.1 always write 'vhdl' into xst prj files again; for
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# 2011-08-13 405 1.9.1 always write 'vhdl' into xst prj files again; for
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# -xst_export: remove opt file export, add ucf_cpp
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# -xst_export: remove opt file export, add ucf_cpp
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# handling
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# handling
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# 2011-06-26 385 1.9 add --ise_path, pass it to vbomconv --xst_prj
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# 2011-06-26 385 1.9 add --ise_path, pass it to vbomconv --xst_prj
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# 2011-06-09 383 1.8.6 fix xst_vhdl.opt logic (use rtl/vlib now)
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# 2011-06-09 383 1.8.6 fix xst_vhdl.opt logic (use rtl/vlib now)
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# 2010-07-03 312 1.8.5 add --flist action
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# 2010-07-03 312 1.8.5 add --flist action
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# 2010-06-03 299 1.8.4 generate ucf->ncd dependencies in dep_xst
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# 2010-06-03 299 1.8.4 generate ucf->ncd dependencies in dep_xst
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# 2010-04-26 284 1.8.3 add _[sft]sim support for ISim
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# 2010-04-26 284 1.8.3 add _[sft]sim support for ISim
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# 2009-11-28 253 1.8.2 fixup print_help...;
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# 2009-11-28 253 1.8.2 fixup print_help...;
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# 2009-11-22 252 1.8.1 add (export|dep)_isim, full ISim support;
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# 2009-11-22 252 1.8.1 add (export|dep)_isim, full ISim support;
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# add [isim] [sim], allow tag lists like [ghdl,isim];
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# add [isim] [sim], allow tag lists like [ghdl,isim];
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# --trace and messages to STDERR;
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# --trace and messages to STDERR;
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# 2009-11-20 251 1.8 add isim_prj, first ISim support
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# 2009-11-20 251 1.8 add isim_prj, first ISim support
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# 2008-03-09 124 1.7.3 add in .dep_(ghdl|xst) all dep on vbom dependencies
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# 2008-03-09 124 1.7.3 add in .dep_(ghdl|xst) all dep on vbom dependencies
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# target now also dependant on .dep_ file
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# target now also dependant on .dep_ file
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# 2008-03-02 122 1.7.2 add @lib: directive to include UNISIM
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# 2008-03-02 122 1.7.2 add @lib: directive to include UNISIM
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# 2007-12-17 102 1.7.1 fix @ucf_cpp logic.
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# 2007-12-17 102 1.7.1 fix @ucf_cpp logic.
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# 2007-12-16 101 1.7 add @ucf_cpp pseudo tag (handle cpp'ed ucf files)
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# 2007-12-16 101 1.7 add @ucf_cpp pseudo tag (handle cpp'ed ucf files)
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# 2007-11-25 98 1.6.1 drop trailing blanks on input lines
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# 2007-11-25 98 1.6.1 drop trailing blanks on input lines
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# 2007-11-02 94 1.6 added (xst|ghdl)_export
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# 2007-11-02 94 1.6 added (xst|ghdl)_export
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# 2007-10-26 92 1.5.1 emit '--no-vital-checks' for --ghdl_m for _[sft]sim
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# 2007-10-26 92 1.5.1 emit '--no-vital-checks' for --ghdl_m for _[sft]sim
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# 2007-10-14 98 1.5 handle .exe files under cygwin properly
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# 2007-10-14 98 1.5 handle .exe files under cygwin properly
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# 2007-09-15 82 1.4 handle C source objects properly
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# 2007-09-15 82 1.4 handle C source objects properly
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# 2007-08-10 72 1.3 add [xst], [ghdl] prefix support
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# 2007-08-10 72 1.3 add [xst], [ghdl] prefix support
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# 2007-07-22 68 1.2 add "tag = val"; list files in 'ready to analyse'
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# 2007-07-22 68 1.2 add "tag = val"; list files in 'ready to analyse'
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# order; add --ghdl_a option
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# order; add --ghdl_a option
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# 2007-07-08 65 1.1 add "tag : names"; inferral of _[ft]sim vboms
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# 2007-07-08 65 1.1 add "tag : names"; inferral of _[ft]sim vboms
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# 2007-07-06 64 1.0 Initial version
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# 2007-07-06 64 1.0 Initial version
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use 5.005; # require Perl 5.005 or higher
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use 5.005; # require Perl 5.005 or higher
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use strict; # require strict checking
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use strict; # require strict checking
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use FileHandle;
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use FileHandle;
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use Cwd 'getcwd';
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use Cwd 'getcwd';
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use Getopt::Long;
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use Getopt::Long;
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my %opts = ();
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my %opts = ();
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GetOptions(\%opts, "help", "trace", "xlpath=s",
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GetOptions(\%opts, "help", "trace", "xlpath=s",
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"dep_ghdl",
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"dep_ghdl",
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"dep_xst", "dep_isim",
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"dep_xst", "dep_isim",
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"dep_vsyn", "dep_vsim",
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"dep_vsyn", "dep_vsim",
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"xst_prj", "isim_prj",
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"xst_prj", "isim_prj",
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"vsyn_prj", "vsim_prj",
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"vsyn_prj", "vsim_prj",
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"ghdl_a", "ghdl_a_cmd",
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"ghdl_a", "ghdl_a_cmd",
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"ghdl_i", "ghdl_i_cmd",
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"ghdl_i", "ghdl_i_cmd",
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"ghdl_m", "ghdl_m_cmd",
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"ghdl_m", "ghdl_m_cmd",
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"ghdl_export=s",
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"ghdl_export=s",
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"xst_export=s",
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"xst_export=s",
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"isim_export=s",
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"isim_export=s",
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"vsyn_export=s",
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"vsyn_export=s",
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"vsim_export=s",
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"vsim_export=s",
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"get_top",
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"get_top",
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"flist") || exit 1;
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"flist") || exit 1;
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sub print_help;
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sub print_help;
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sub read_vbom;
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sub read_vbom;
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sub scan_vbom;
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sub scan_vbom;
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sub do_synsim;
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sub do_synsim;
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sub scan_synsim;
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sub scan_synsim;
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sub copy_edir;
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sub copy_edir;
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sub write_vbomdep;
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sub write_vbomdep;
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sub canon_fname;
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sub canon_fname;
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sub parse_props;
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sub parse_props;
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sub setup_props;
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sub setup_props;
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my @vbom_queue; # list of pending vbom's
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my @vbom_queue; # list of pending vbom's
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my @srcfile_list; # list of sources in compile order
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my @srcfile_list; # list of sources in compile order
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my @xdcfile_list; # list of xdc files
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my @xdcfile_list; # list of xdc files
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my @srcfile_list_vhd; # all vhdl sources
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my @srcfile_list_vhd; # all vhdl sources
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my @srcfile_list_v; # all (system) verilog sources
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my @srcfile_list_v; # all (system) verilog sources
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my @srcfile_list_c; # all C sources
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my @srcfile_list_c; # all C sources
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my %vbom_files; # key=vbom; val=full file list
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my %vbom_files; # key=vbom; val=full file list
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my %vbom_xdc; # key=vbom; val=xdc spec list
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my %vbom_xdc; # key=vbom; val=xdc spec list
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my %vbom_done; # key=vbom; val=done flags
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my %vbom_done; # key=vbom; val=done flags
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my %vbom_rank; # key=vbom; val=vbom ranks
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my %vbom_rank; # key=vbom; val=vbom ranks
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my %srcfile_rank; # key=source file; val=file rank
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my %srcfile_rank; # key=source file; val=file rank
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my %srcfile_synsim; # key=source file; val=syn or sim
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my %srcfile_synsim; # key=source file; val=syn or sim
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my %srcfile_prop; # key=source file; hash of props
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my %srcfile_prop; # key=source file; hash of props
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my %para_tbl; # substitution table
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my %para_tbl; # substitution table
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my @ucf_cpp_list;
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my @ucf_cpp_list;
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my $is_ghdl = 0; # ghdl simulation target
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my $is_ghdl = 0; # ghdl simulation target
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my $is_xst = 0; # XST synthesis target
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my $is_xst = 0; # XST synthesis target
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my $is_isim = 0; # ISim simulation target
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my $is_isim = 0; # ISim simulation target
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my $is_vsyn = 0; # vivado synthesis target
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my $is_vsyn = 0; # vivado synthesis target
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my $is_vsim = 0; # vivado simulation target
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my $is_vsim = 0; # vivado simulation target
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my $is_sim = 0; # simulation target (generic)
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my $is_sim = 0; # simulation target (generic)
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my $is_ise = 0; # ISE target
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my $is_ise = 0; # ISE target
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my $is_viv = 0; # vivado target
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my $is_viv = 0; # vivado target
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my $is_any = 0; # ignore tags (for --flist)
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my $is_any = 0; # ignore tags (for --flist)
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my $is_bsim = 0; # is behavioural simulation
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my $is_bsim = 0; # is behavioural simulation
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my $is_fsim = 0; # is functional simulation
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my $is_fsim = 0; # is functional simulation
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my $is_tsim = 0; # is timing simulation
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my $is_tsim = 0; # is timing simulation
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my $is_veri = 0; # is verilog model based
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my $is_veri = 0; # is verilog model based
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my $nactions = 0; # number of action commands
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my $nactions = 0; # number of action commands
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my $top_vbom; # top level vbom (from argv)
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my $top_vbom; # top level vbom (from argv)
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my $eff_vbom; # effective vbom ([fot]sim->ssim map)
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my $eff_vbom; # effective vbom ([fot]sim->ssim map)
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my $stem; # stem of $top_vbom
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my $stem; # stem of $top_vbom
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my $top; # top level entity name
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my $top; # top level entity name
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my $top_done = 0; # @top seen
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my $top_done = 0; # @top seen
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my $uut; # uut level name
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my $uut; # uut level name
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my $has_unisim; # @lib:unisim seen or implied
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my $has_unisim; # @lib:unisim seen or implied
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my $has_unimacro; # @lib:unimacro seen
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my $has_unimacro; # @lib:unimacro seen
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my $has_simprim; # @lib:simprim seen or implied
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my $has_simprim; # @lib:simprim seen or implied
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my $sim_mode = 'bsim';
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my $sim_mode = 'bsim';
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my $do_trace = exists $opts{trace};
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my $do_trace = exists $opts{trace};
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my $level = 0; # vbom nesting level
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my $level = 0; # vbom nesting level
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my $xst_writevhdl = 1;
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my $xst_writevhdl = 1;
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my $xlpath=$opts{xlpath};
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my $xlpath=$opts{xlpath};
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my $no_xlpath = ! defined $xlpath || $xlpath eq "";
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my $no_xlpath = ! defined $xlpath || $xlpath eq "";
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my $ghdl_opts = $ENV{VBOMCONV_GHDL_OPTS}; # ghdl extra options
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my $ghdl_opts = $ENV{VBOMCONV_GHDL_OPTS}; # ghdl extra options
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my $ghdl_gcov = $ENV{VBOMCONV_GHDL_GCOV}; # ghdl gcov enable
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my $ghdl_gcov = $ENV{VBOMCONV_GHDL_GCOV}; # ghdl gcov enable
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my $xsim_lang = $ENV{VBOMCONV_XSIM_LANG}; # xsim model language
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my $xsim_lang = $ENV{VBOMCONV_XSIM_LANG}; # xsim model language
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if ($ghdl_gcov) {
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if ($ghdl_gcov) {
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$ghdl_opts = '' unless defined $ghdl_opts;
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$ghdl_opts = '' unless defined $ghdl_opts;
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$ghdl_opts .= ' ' unless $ghdl_opts eq '';
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$ghdl_opts .= ' ' unless $ghdl_opts eq '';
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$ghdl_opts .= '-Wc,-ftest-coverage -Wc,-fprofile-arcs -Wl,-lgcov';
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$ghdl_opts .= '-Wc,-ftest-coverage -Wc,-fprofile-arcs -Wl,-lgcov';
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} else {
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} else {
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$ghdl_opts = '-O2 -g' unless defined $ghdl_opts;
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$ghdl_opts = '-O2 -g' unless defined $ghdl_opts;
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}
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}
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$xsim_lang = 'verilog' unless defined $xsim_lang;
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$xsim_lang = 'verilog' unless defined $xsim_lang;
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if ($xsim_lang ne 'verilog' && $xsim_lang ne 'vhdl') {
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if ($xsim_lang ne 'verilog' && $xsim_lang ne 'vhdl') {
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print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG is '$xsim_lang'\n";
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print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG is '$xsim_lang'\n";
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print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG must be 'verilog' or 'vhdl'\n";
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print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG must be 'verilog' or 'vhdl'\n";
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exit 1;
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exit 1;
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}
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}
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$is_veri = $xsim_lang eq 'verilog';
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$is_veri = $xsim_lang eq 'verilog';
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autoflush STDOUT 1; # autoflush, so nothing lost on exec later
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autoflush STDOUT 1; # autoflush, so nothing lost on exec later
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if (exists $opts{help}) {
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if (exists $opts{help}) {
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print_help;
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print_help;
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exit 0;
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exit 0;
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}
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}
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# ensure that one and only one vbom is specified
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# ensure that one and only one vbom is specified
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if (scalar(@ARGV) != 1) {
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if (scalar(@ARGV) != 1) {
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print STDERR "vbomconv-E: only one vbom file name allowed\n\n";
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print STDERR "vbomconv-E: only one vbom file name allowed\n\n";
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print_help;
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print_help;
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exit 1;
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exit 1;
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}
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}
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# get number of CPUs (used later....)
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# get number of CPUs (used later....)
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my $nproc = `nproc`;
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my $nproc = `nproc`;
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chomp $nproc;
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chomp $nproc;
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# check that only one action is defined, mark xst, gdhl, or isim class
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# check that only one action is defined, mark xst, gdhl, or isim class
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foreach (keys %opts) {
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foreach (keys %opts) {
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$nactions += 1 unless ($_ eq "trace" || $_ eq "xlpath");
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$nactions += 1 unless ($_ eq "trace" || $_ eq "xlpath");
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$is_ghdl = 1 if $_ eq "dep_ghdl";
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$is_ghdl = 1 if $_ eq "dep_ghdl";
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$is_ghdl = 1 if $_ =~ /^ghdl_/;
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$is_ghdl = 1 if $_ =~ /^ghdl_/;
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$is_xst = 1 if $_ eq "dep_xst";
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$is_xst = 1 if $_ eq "dep_xst";
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$is_xst = 1 if $_ =~ /^xst_/;
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$is_xst = 1 if $_ =~ /^xst_/;
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$is_isim = 1 if $_ eq "dep_isim";
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$is_isim = 1 if $_ eq "dep_isim";
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$is_isim = 1 if $_ =~ /^isim_/;
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$is_isim = 1 if $_ =~ /^isim_/;
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$is_vsyn = 1 if $_ eq "dep_vsyn";
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$is_vsyn = 1 if $_ eq "dep_vsyn";
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$is_vsyn = 1 if $_ =~ /^vsyn_/;
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$is_vsyn = 1 if $_ =~ /^vsyn_/;
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$is_vsim = 1 if $_ eq "dep_vsim";
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$is_vsim = 1 if $_ eq "dep_vsim";
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$is_vsim = 1 if $_ =~ /^vsim_/;
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$is_vsim = 1 if $_ =~ /^vsim_/;
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$is_any = 1 if $_ eq "flist";
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$is_any = 1 if $_ eq "flist";
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}
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}
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$is_sim = $is_ghdl | $is_isim | $is_vsim;
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$is_sim = $is_ghdl | $is_isim | $is_vsim;
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$is_ise = $is_xst | $is_isim;
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$is_ise = $is_xst | $is_isim;
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$is_viv = $is_vsyn | $is_vsim;
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$is_viv = $is_vsyn | $is_vsim;
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print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl;
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print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl;
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print STDERR "-- [xst] active\n" if $do_trace && $is_xst;
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print STDERR "-- [xst] active\n" if $do_trace && $is_xst;
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print STDERR "-- [isim] active\n" if $do_trace && $is_isim;
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print STDERR "-- [isim] active\n" if $do_trace && $is_isim;
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print STDERR "-- [vsyn] active\n" if $do_trace && $is_vsyn;
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print STDERR "-- [vsyn] active\n" if $do_trace && $is_vsyn;
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print STDERR "-- [vsim] active\n" if $do_trace && $is_vsim;
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print STDERR "-- [vsim] active\n" if $do_trace && $is_vsim;
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print STDERR "-- [sim] active\n" if $do_trace && $is_sim;
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print STDERR "-- [sim] active\n" if $do_trace && $is_sim;
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print STDERR "-- [ise] active\n" if $do_trace && $is_ise;
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print STDERR "-- [ise] active\n" if $do_trace && $is_ise;
|
print STDERR "-- [viv] active\n" if $do_trace && $is_viv;
|
print STDERR "-- [viv] active\n" if $do_trace && $is_viv;
|
|
|
if ($nactions > 1) {
|
if ($nactions > 1) {
|
print STDERR "vbomconv-E: only one action qualifier allowed\n\n";
|
print STDERR "vbomconv-E: only one action qualifier allowed\n\n";
|
print_help;
|
print_help;
|
exit 1;
|
exit 1;
|
}
|
}
|
|
|
$top_vbom = $ARGV[0];
|
$top_vbom = $ARGV[0];
|
|
|
$top_vbom .= ".vbom" unless $top_vbom =~ m{\.vbom$};
|
$top_vbom .= ".vbom" unless $top_vbom =~ m{\.vbom$};
|
|
|
$stem = $top_vbom;
|
$stem = $top_vbom;
|
$stem =~ s{\..*$}{};
|
$stem =~ s{\..*$}{};
|
|
|
$top = $stem;
|
$top = $stem;
|
$top =~ s{^.*/}{};
|
$top =~ s{^.*/}{};
|
|
|
# now prepare virtual _[forept]sim vbom's
|
# now prepare virtual _[forept]sim vbom's
|
# they are inferred from the _ssim vbom's
|
# they are inferred from the _ssim vbom's
|
|
|
if ($top_vbom =~ m{_([sforept]sim)\.vbom$}) {
|
if ($top_vbom =~ m{_([sforept]sim)\.vbom$}) {
|
$sim_mode = $1;
|
$sim_mode = $1;
|
}
|
}
|
|
|
$is_bsim = 1 if $sim_mode eq 'bsim';
|
$is_bsim = 1 if $sim_mode eq 'bsim';
|
$is_fsim = 1 if $sim_mode =~ m/^[fsor]sim$/;
|
$is_fsim = 1 if $sim_mode =~ m/^[fsor]sim$/;
|
$is_tsim = 1 if $sim_mode =~ m/^[ept]sim$/;
|
$is_tsim = 1 if $sim_mode =~ m/^[ept]sim$/;
|
|
|
$eff_vbom = $top_vbom;
|
$eff_vbom = $top_vbom;
|
$eff_vbom =~ s{_[forept]sim\.vbom$}{_ssim.vbom}; # map [forept]sim -> ssim
|
$eff_vbom =~ s{_[forept]sim\.vbom$}{_ssim.vbom}; # map [forept]sim -> ssim
|
|
|
# traverse all vbom's start with command line argument
|
# traverse all vbom's start with command line argument
|
|
|
push @vbom_queue, $eff_vbom;
|
push @vbom_queue, $eff_vbom;
|
|
|
while (@vbom_queue) {
|
while (@vbom_queue) {
|
my $cur_vbom = shift @vbom_queue;
|
my $cur_vbom = shift @vbom_queue;
|
read_vbom($cur_vbom);
|
read_vbom($cur_vbom);
|
}
|
}
|
|
|
# traverse internal vbom representation to build file table
|
# traverse internal vbom representation to build file table
|
|
|
$vbom_rank{$eff_vbom} = {min=>1, max=>1};
|
$vbom_rank{$eff_vbom} = {min=>1, max=>1};
|
scan_vbom($eff_vbom);
|
scan_vbom($eff_vbom);
|
|
|
# separate sym (uut) and sim (tb) parts
|
# separate sym (uut) and sim (tb) parts
|
do_synsim($uut);
|
do_synsim($uut);
|
|
|
# sort file table, build file list (decreasing rank)
|
# sort file table, build file list (decreasing rank)
|
# sort first by decreasing rank and second by filename
|
# sort first by decreasing rank and second by filename
|
# second sort only to get stable sequence, independent of hash keys
|
# second sort only to get stable sequence, independent of hash keys
|
|
|
my @srcpair_list;
|
my @srcpair_list;
|
foreach (keys %srcfile_rank) {
|
foreach (keys %srcfile_rank) {
|
push @srcpair_list, [$srcfile_rank{$_}, $_];
|
push @srcpair_list, [$srcfile_rank{$_}, $_];
|
}
|
}
|
|
|
@srcfile_list = map {$_->[1]}
|
@srcfile_list = map {$_->[1]}
|
sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]}
|
sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]}
|
@srcpair_list;
|
@srcpair_list;
|
|
|
# setup vbom list by rank
|
# setup vbom list by rank
|
my @vbom_rank_list;
|
my @vbom_rank_list;
|
foreach (sort keys %vbom_rank) {
|
foreach (sort keys %vbom_rank) {
|
push @vbom_rank_list, [$vbom_rank{$_}{min}, $vbom_rank{$_}{max}, $_];
|
push @vbom_rank_list, [$vbom_rank{$_}{min}, $vbom_rank{$_}{max}, $_];
|
}
|
}
|
my @vbomfile_list_min = map {$_->[2]}
|
my @vbomfile_list_min = map {$_->[2]}
|
sort {$a->[0] <=> $b->[0] || $a->[1] cmp $b->[1]}
|
sort {$a->[0] <=> $b->[0] || $a->[1] cmp $b->[1]}
|
@vbom_rank_list;
|
@vbom_rank_list;
|
|
|
# setup xdc files list (if one @xdc: seen)
|
# setup xdc files list (if one @xdc: seen)
|
foreach (@vbomfile_list_min) {
|
foreach (@vbomfile_list_min) {
|
push @xdcfile_list, @{$vbom_xdc{$_}} if exists $vbom_xdc{$_};
|
push @xdcfile_list, @{$vbom_xdc{$_}} if exists $vbom_xdc{$_};
|
}
|
}
|
|
|
# now split source list according to languages
|
# now split source list according to languages
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
if (m/\.vhd$/) {
|
if (m/\.vhd$/) {
|
push @srcfile_list_vhd, $_;
|
push @srcfile_list_vhd, $_;
|
} elsif (m/\.(v|sv)$/) {
|
} elsif (m/\.(v|sv)$/) {
|
push @srcfile_list_v, $_;
|
push @srcfile_list_v, $_;
|
} elsif (m/\.c$/) {
|
} elsif (m/\.c$/) {
|
push @srcfile_list_c, $_;
|
push @srcfile_list_c, $_;
|
# } else {
|
# } else {
|
# print STDERR "unknown file type $_\n";
|
# print STDERR "unknown file type $_\n";
|
}
|
}
|
}
|
}
|
|
|
# now generate output and actions, depending on options given
|
# now generate output and actions, depending on options given
|
|
|
# --trace ------------------------------------------------------------
|
# --trace ------------------------------------------------------------
|
|
|
if ($do_trace) {
|
if ($do_trace) {
|
print STDERR "\n";
|
print STDERR "\n";
|
print STDERR "filename substitution table:\n";
|
print STDERR "filename substitution table:\n";
|
foreach (sort keys %para_tbl) {
|
foreach (sort keys %para_tbl) {
|
print STDERR " $_ = $para_tbl{$_}\n";
|
print STDERR " $_ = $para_tbl{$_}\n";
|
}
|
}
|
|
|
print STDERR "\n";
|
print STDERR "\n";
|
print STDERR "final vbom_rank table (sort by min rank):\n";
|
print STDERR "final vbom_rank table (sort by min rank):\n";
|
print STDERR " min max var vbom-name:\n";
|
print STDERR " min max var vbom-name:\n";
|
foreach (sort {$a->[0] <=> $b->[0] || $a->[2] cmp $b->[2]} @vbom_rank_list) {
|
foreach (sort {$a->[0] <=> $b->[0] || $a->[2] cmp $b->[2]} @vbom_rank_list) {
|
printf STDERR " %3d %3d %3d %s\n",
|
printf STDERR " %3d %3d %3d %s\n",
|
$_->[0], $_->[1], $_->[1]-$_->[0], $_->[2];
|
$_->[0], $_->[1], $_->[1]-$_->[0], $_->[2];
|
}
|
}
|
|
|
print STDERR "\n";
|
print STDERR "\n";
|
print STDERR "final srcfile_rank table (sort by rank):\n";
|
print STDERR "final srcfile_rank table (sort by rank):\n";
|
foreach (sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} @srcpair_list) {
|
foreach (sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} @srcpair_list) {
|
printf STDERR " %5d %s %s\n", $_->[0], $srcfile_synsim{$_->[1]}, $_->[1];
|
printf STDERR " %5d %s %s\n", $_->[0], $srcfile_synsim{$_->[1]}, $_->[1];
|
}
|
}
|
|
|
print STDERR "\n";
|
print STDERR "\n";
|
print STDERR "properties:\n";
|
print STDERR "properties:\n";
|
print STDERR " \@top: $top\n";
|
print STDERR " \@top: $top\n";
|
print STDERR " \-UUT: $uut\n" if defined $uut;
|
print STDERR " \-UUT: $uut\n" if defined $uut;
|
}
|
}
|
|
|
# --ghdl_a -- ghdl analysis command ----------------------------------
|
# --ghdl_a -- ghdl analysis command ----------------------------------
|
|
|
if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) {
|
if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) {
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) {
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) {
|
print STDERR "vbomconv-E: --xlpath required with ghdl_a or ghdl_a_cmd";
|
print STDERR "vbomconv-E: --xlpath required with ghdl_a or ghdl_a_cmd";
|
exit 1;
|
exit 1;
|
}
|
}
|
my $workdir = "ghdl.${sim_mode}";
|
my $workdir = "ghdl.${sim_mode}";
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
my $file = $_;
|
my $file = $_;
|
my $cmd = "ghdl -a --workdir=${workdir}";
|
my $cmd = "ghdl -a --workdir=${workdir}";
|
$cmd .= " -P$xlpath/unisim" if $has_unisim;
|
$cmd .= " -P$xlpath/unisim" if $has_unisim;
|
$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
|
$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
|
$cmd .= " -P$xlpath/simprim" if $has_simprim;
|
$cmd .= " -P$xlpath/simprim" if $has_simprim;
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " ${ghdl_opts}";
|
$cmd .= " ${ghdl_opts}";
|
$cmd .= " $file";
|
$cmd .= " $file";
|
print "$cmd\n";
|
print "$cmd\n";
|
if (exists $opts{ghdl_a}) {
|
if (exists $opts{ghdl_a}) {
|
my $wrc = system "/bin/sh", "-c", $cmd;
|
my $wrc = system "/bin/sh", "-c", $cmd;
|
if ($wrc != 0) {
|
if ($wrc != 0) {
|
my $rc = int($wrc/256);
|
my $rc = int($wrc/256);
|
if ($rc == 0) {
|
if ($rc == 0) {
|
my $sig = $wrc % 256;
|
my $sig = $wrc % 256;
|
print STDERR "vbomconv-I: compilation aborted by signal $sig\n";
|
print STDERR "vbomconv-I: compilation aborted by signal $sig\n";
|
exit(1);
|
exit(1);
|
} else {
|
} else {
|
print STDERR "vbomconv-I: compilation failed (rc=$rc) $?\n";
|
print STDERR "vbomconv-I: compilation failed (rc=$rc) $?\n";
|
exit($rc);
|
exit($rc);
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
# --ghdl_i -- ghdl inspection command --------------------------------
|
# --ghdl_i -- ghdl inspection command --------------------------------
|
|
|
if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) {
|
if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) {
|
my $workdir = "ghdl.${sim_mode}";
|
my $workdir = "ghdl.${sim_mode}";
|
my %ghdl_work;
|
my %ghdl_work;
|
|
|
system "mkdir ${workdir}" unless -d ${workdir};
|
system "mkdir ${workdir}" unless -d ${workdir};
|
|
|
# read ghdl "work-obj93.cf" file. It has the format
|
# read ghdl "work-obj93.cf" file. It has the format
|
# file . "" "" "ghdl -i or -a date>":
|
# file . "" "" "ghdl -i or -a date>":
|
# entity at nn( nn) + nn on nn;
|
# entity at nn( nn) + nn on nn;
|
# architecture of at nn( nn) + nn on nn;
|
# architecture of at nn( nn) + nn on nn;
|
|
|
if (-r "${workdir}/work-obj93.cf") {
|
if (-r "${workdir}/work-obj93.cf") {
|
open (WFILE, "${workdir}/work-obj93.cf") or
|
open (WFILE, "${workdir}/work-obj93.cf") or
|
die "can't open for ${workdir}/read work-obj93.cf: $!";
|
die "can't open for ${workdir}/read work-obj93.cf: $!";
|
while () {
|
while () {
|
if (m{^file \. \"(.*?)\"}) {
|
if (m{^file \. \"(.*?)\"}) {
|
$ghdl_work{$1} = 1;
|
$ghdl_work{$1} = 1;
|
}
|
}
|
}
|
}
|
close (WFILE);
|
close (WFILE);
|
}
|
}
|
|
|
my $cmd = "ghdl -i --workdir=${workdir}";
|
my $cmd = "ghdl -i --workdir=${workdir}";
|
my $nfile = 0;
|
my $nfile = 0;
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
next if /\.c$/; # skip C sources, only vhd handled
|
next if /\.c$/; # skip C sources, only vhd handled
|
if (not exists $ghdl_work{$_}) {
|
if (not exists $ghdl_work{$_}) {
|
$cmd .= " \\\n $_";
|
$cmd .= " \\\n $_";
|
$nfile += 1;
|
$nfile += 1;
|
}
|
}
|
}
|
}
|
|
|
if ($nfile) {
|
if ($nfile) {
|
print "$cmd\n";
|
print "$cmd\n";
|
if (exists $opts{ghdl_i}) {
|
if (exists $opts{ghdl_i}) {
|
exec "/bin/sh", "-c", $cmd;
|
exec "/bin/sh", "-c", $cmd;
|
die "failed to exec /bin/sh -c $cmd: $!";
|
die "failed to exec /bin/sh -c $cmd: $!";
|
}
|
}
|
} else {
|
} else {
|
print "# $cmd ## all files already inspected\n";
|
print "# $cmd ## all files already inspected\n";
|
}
|
}
|
}
|
}
|
|
|
# --ghdl_m -- ghdl make command --------------------------------------
|
# --ghdl_m -- ghdl make command --------------------------------------
|
# Note: the 'buildin' make used by the -m option of ghdl does not
|
# Note: the 'buildin' make used by the -m option of ghdl does not
|
# check for object files linked with -Wl, e.g. vhpi objects.
|
# check for object files linked with -Wl, e.g. vhpi objects.
|
# To force a re-elaboration the old executable is deleted first.
|
# To force a re-elaboration the old executable is deleted first.
|
# If used from make with proper dependencies, this will just do
|
# If used from make with proper dependencies, this will just do
|
# the right thing.
|
# the right thing.
|
|
|
if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) {
|
if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) {
|
my $workdir = "ghdl.${sim_mode}";
|
my $workdir = "ghdl.${sim_mode}";
|
my $cmd = "";
|
my $cmd = "";
|
|
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) {
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) {
|
print STDERR "vbomconv-E: --xlpath required with ghdl_m or ghdl_m_cmd";
|
print STDERR "vbomconv-E: --xlpath required with ghdl_m or ghdl_m_cmd";
|
exit 1;
|
exit 1;
|
}
|
}
|
|
|
if (-r $stem) { # check for old executable
|
if (-r $stem) { # check for old executable
|
$cmd .= "rm $stem\n" ; # rm to force elaboration
|
$cmd .= "rm $stem\n" ; # rm to force elaboration
|
}
|
}
|
|
|
$cmd .= "ghdl -m --workdir=${workdir}";
|
$cmd .= "ghdl -m --workdir=${workdir}";
|
$cmd .= " -o $stem";
|
$cmd .= " -o $stem";
|
# -fexplicit needed for ISE 13.1,13.3
|
# -fexplicit needed for ISE 13.1,13.3
|
$cmd .= ' -fexplicit' if $has_unisim or $has_unimacro or $has_simprim;
|
$cmd .= ' -fexplicit' if $has_unisim or $has_unimacro or $has_simprim;
|
$cmd .= " -P$xlpath/unisim" if $has_unisim;
|
$cmd .= " -P$xlpath/unisim" if $has_unisim;
|
$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
|
$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
|
$cmd .= " -P$xlpath/simprim" if $has_simprim;
|
$cmd .= " -P$xlpath/simprim" if $has_simprim;
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " ${ghdl_opts}";
|
$cmd .= " ${ghdl_opts}";
|
$cmd .= " --no-vital-checks" if $sim_mode ne 'bsim';
|
$cmd .= " --no-vital-checks" if $sim_mode ne 'bsim';
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
next unless /\.c$/; # C source ?
|
next unless /\.c$/; # C source ?
|
my $ofile = $_; # copy to break alias for following s///
|
my $ofile = $_; # copy to break alias for following s///
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s/\.c$/.o/; # add clause to link C source object file
|
$ofile =~ s/\.c$/.o/; # add clause to link C source object file
|
$cmd .= " -Wl,$ofile";
|
$cmd .= " -Wl,$ofile";
|
}
|
}
|
$cmd .= " $top";
|
$cmd .= " $top";
|
print "$cmd\n";
|
print "$cmd\n";
|
if (exists $opts{ghdl_m}) {
|
if (exists $opts{ghdl_m}) {
|
exec "/bin/sh", "-c", $cmd;
|
exec "/bin/sh", "-c", $cmd;
|
die "failed to exec /bin/sh -c $cmd: $!";
|
die "failed to exec /bin/sh -c $cmd: $!";
|
}
|
}
|
}
|
}
|
|
|
# --xst_prj ----------------------------------------------------------
|
# --xst_prj ----------------------------------------------------------
|
|
|
if (exists $opts{xst_prj}) {
|
if (exists $opts{xst_prj}) {
|
## $xst_writevhdl = 0; # needed in case "-use_new_parser yes" used
|
## $xst_writevhdl = 0; # needed in case "-use_new_parser yes" used
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
if ($xst_writevhdl) {
|
if ($xst_writevhdl) {
|
print "vhdl work $_\n";
|
print "vhdl work $_\n";
|
} else {
|
} else {
|
print "work $_\n"; # for ISE S-6/V-6 compilations with '-ifmt VHDL'
|
print "work $_\n"; # for ISE S-6/V-6 compilations with '-ifmt VHDL'
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
# --isim_prj ---------------------------------------------------------
|
# --isim_prj ---------------------------------------------------------
|
|
|
if (exists $opts{isim_prj}) {
|
if (exists $opts{isim_prj}) {
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
print "vhdl work $_\n";
|
print "vhdl work $_\n";
|
}
|
}
|
}
|
}
|
|
|
# --vsyn_prj ---------------------------------------------------------
|
# --vsyn_prj ---------------------------------------------------------
|
|
|
if (exists $opts{vsyn_prj}) {
|
if (exists $opts{vsyn_prj}) {
|
# determine source and simulation file sets
|
# determine source and simulation file sets
|
my @fl_syn;
|
my @fl_syn;
|
my @fl_sim;
|
my @fl_sim;
|
foreach my $fi (@srcfile_list) {
|
foreach my $fi (@srcfile_list) {
|
if ($srcfile_synsim{$fi} eq 'syn') {
|
if ($srcfile_synsim{$fi} eq 'syn') {
|
push @fl_syn, $fi;
|
push @fl_syn, $fi;
|
} else {
|
} else {
|
push @fl_sim, $fi;
|
push @fl_sim, $fi;
|
}
|
}
|
}
|
}
|
print "#\n";
|
print "#\n";
|
print "# setup sources for synthesis\n";
|
print "# setup sources for synthesis\n";
|
print "#\n";
|
print "#\n";
|
print "set syn_files {\n";
|
print "set syn_files {\n";
|
foreach (@fl_syn) {
|
foreach (@fl_syn) {
|
print " $_\n";
|
print " $_\n";
|
}
|
}
|
print "}\n";
|
print "}\n";
|
print "\n";
|
print "\n";
|
|
|
print "set obj [get_filesets sources_1]\n";
|
print "set obj [get_filesets sources_1]\n";
|
print "add_files -norecurse -fileset \$obj \$syn_files\n";
|
print "add_files -norecurse -fileset \$obj \$syn_files\n";
|
# defined top only when not doing test bench
|
# defined top only when not doing test bench
|
print "set_property \"top\" \"$top\" \$obj\n" unless defined $uut;
|
print "set_property \"top\" \"$top\" \$obj\n" unless defined $uut;
|
|
|
if (defined $uut) {
|
if (defined $uut) {
|
print "#\n";
|
print "#\n";
|
print "# setup sources for simulation\n";
|
print "# setup sources for simulation\n";
|
print "#\n";
|
print "#\n";
|
print "set sim_files {\n";
|
print "set sim_files {\n";
|
foreach (@fl_sim) {
|
foreach (@fl_sim) {
|
print " $_\n";
|
print " $_\n";
|
}
|
}
|
print "}\n";
|
print "}\n";
|
print "\n";
|
print "\n";
|
|
|
print "set obj [get_filesets sim_1]\n";
|
print "set obj [get_filesets sim_1]\n";
|
print "add_files -norecurse -fileset \$obj \$sim_files\n";
|
print "add_files -norecurse -fileset \$obj \$sim_files\n";
|
print "set_property SOURCE_SET sources_1 \$obj\n";
|
print "set_property SOURCE_SET sources_1 \$obj\n";
|
}
|
}
|
|
|
# setup constraints
|
# setup constraints
|
print "#\n";
|
print "#\n";
|
print "# setup constraints\n";
|
print "# setup constraints\n";
|
print "#\n";
|
print "#\n";
|
|
|
print "set xdc_files {\n";
|
print "set xdc_files {\n";
|
foreach (@xdcfile_list) {
|
foreach (@xdcfile_list) {
|
print " $_\n";
|
print " $_\n";
|
}
|
}
|
print "}\n";
|
print "}\n";
|
print "\n";
|
print "\n";
|
|
|
# add_files does not allow adding an empty set, so protect
|
# add_files does not allow adding an empty set, so protect
|
if (scalar @xdcfile_list) {
|
if (scalar @xdcfile_list) {
|
print "set obj [get_filesets constrs_1]\n";
|
print "set obj [get_filesets constrs_1]\n";
|
print "add_files -norecurse -fileset \$obj \$xdc_files\n";
|
print "add_files -norecurse -fileset \$obj \$xdc_files\n";
|
print "\n";
|
print "\n";
|
foreach my $fnam (@xdcfile_list) {
|
foreach my $fnam (@xdcfile_list) {
|
if (exists $srcfile_prop{$fnam}->{-SCOPE_REF}) {
|
if (exists $srcfile_prop{$fnam}->{-SCOPE_REF}) {
|
my $target = $srcfile_prop{$fnam}->{-SCOPE_REF};
|
my $target = $srcfile_prop{$fnam}->{-SCOPE_REF};
|
$target = $srcfile_prop{$fnam}->{VBstem} if $target eq '';
|
$target = $srcfile_prop{$fnam}->{VBstem} if $target eq '';
|
print "set_property SCOPED_TO_REF $target \\\n";
|
print "set_property SCOPED_TO_REF $target \\\n";
|
print " [get_files $fnam]\n";
|
print " [get_files $fnam]\n";
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
print "\n";
|
print "\n";
|
}
|
}
|
|
|
# --vsim_prj ---------------------------------------------------------
|
# --vsim_prj ---------------------------------------------------------
|
|
|
if (exists $opts{vsim_prj}) {
|
if (exists $opts{vsim_prj}) {
|
# Note: use a separate workdir for each sim_mode and each model (given
|
# Note: use a separate workdir for each sim_mode and each model (given
|
# by stem). This allows to have all co-existant, and to delete the workdir
|
# by stem). This allows to have all co-existant, and to delete the workdir
|
# each time one of them is re-build.
|
# each time one of them is re-build.
|
my $workdir = "xsim.${sim_mode}.${stem}";
|
my $workdir = "xsim.${sim_mode}.${stem}";
|
my $fname_forwarder = "${stem}_XSim";
|
my $fname_forwarder = "${stem}_XSim";
|
$fname_forwarder =~ s/_([sorept]sim)_XSim/_XSim_$1/;
|
$fname_forwarder =~ s/_([sorept]sim)_XSim/_XSim_$1/;
|
|
|
print "#!/bin/bash\n";
|
print "#!/bin/bash\n";
|
# pipefail ensures that in pipes like xvlog | tee ect the exits status is
|
# pipefail ensures that in pipes like xvlog | tee ect the exits status is
|
# from the last failed command, and not simply from last command (tee).
|
# from the last failed command, and not simply from last command (tee).
|
# that ensures that the xvlog exit codes can be tested
|
# that ensures that the xvlog exit codes can be tested
|
print "set -o pipefail\n";
|
print "set -o pipefail\n";
|
print "#\n";
|
print "#\n";
|
print "# generated by vbomconv -vsim_prj $top_vbom\n";
|
print "# generated by vbomconv -vsim_prj $top_vbom\n";
|
print "#\n";
|
print "#\n";
|
|
|
print "# ---------- delete old forwarder\n";
|
print "# ---------- delete old forwarder\n";
|
print "rm -f $fname_forwarder\n";
|
print "rm -f $fname_forwarder\n";
|
print "#\n";
|
print "#\n";
|
|
|
print "# ---------- setup fresh working directory\n";
|
print "# ---------- setup fresh working directory\n";
|
print "rm -rf ${workdir}\n";
|
print "rm -rf ${workdir}\n";
|
print "mkdir ${workdir}\n";
|
print "mkdir ${workdir}\n";
|
print "pushd ${workdir}\n";
|
print "pushd ${workdir}\n";
|
print "#\n";
|
print "#\n";
|
|
|
# compile verilog before vhdl !
|
# compile verilog before vhdl !
|
# currently verilog only used for DPI interface code or simulation models
|
# currently verilog only used for DPI interface code or simulation models
|
# xvhdl relies in strict compilation order, also across languages, and fails
|
# xvhdl relies in strict compilation order, also across languages, and fails
|
# when a not yet compiled module is instantiated via entiry work.xxx
|
# when a not yet compiled module is instantiated via entiry work.xxx
|
|
|
if (scalar @srcfile_list_v) {
|
if (scalar @srcfile_list_v) {
|
print "# ---------- xvlog step\n";
|
print "# ---------- xvlog step\n";
|
my $tfile_xvlog_prj = "tmp_${stem}_xvlog.prj";
|
my $tfile_xvlog_prj = "tmp_${stem}_xvlog.prj";
|
print "cat > $tfile_xvlog_prj <
|
print "cat > $tfile_xvlog_prj <
|
print "#compile verilog source files\n";
|
print "#compile verilog source files\n";
|
foreach (@srcfile_list_v) {
|
foreach (@srcfile_list_v) {
|
my $type = (m/\.v$/) ? "verilog" : "sv ";
|
my $type = (m/\.v$/) ? "verilog" : "sv ";
|
print "$type xil_defaultlib ../$_\n";
|
print "$type xil_defaultlib ../$_\n";
|
}
|
}
|
print "#do not sort compile order\n";
|
print "#do not sort compile order\n";
|
print "nosort\n";
|
print "nosort\n";
|
print "tmp_xvlog_end_token\n";
|
print "tmp_xvlog_end_token\n";
|
print "#\n";
|
print "#\n";
|
|
|
my $opts_xvlog = "-m64 --relax";
|
my $opts_xvlog = "-m64 --relax";
|
print "xtwv xvlog $opts_xvlog -prj $tfile_xvlog_prj 2>&1 |\\\n";
|
print "xtwv xvlog $opts_xvlog -prj $tfile_xvlog_prj 2>&1 |\\\n";
|
print " tee xvlog_${stem}.log\n";
|
print " tee xvlog_${stem}.log\n";
|
print 'exitstatus=$?' . "\n";
|
print 'exitstatus=$?' . "\n";
|
print "rm -f $tfile_xvlog_prj\n";
|
print "rm -f $tfile_xvlog_prj\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print "#\n";
|
print "#\n";
|
}
|
}
|
|
|
if (scalar @srcfile_list_vhd) {
|
if (scalar @srcfile_list_vhd) {
|
print "# ---------- xvhdl step\n";
|
print "# ---------- xvhdl step\n";
|
my $tfile_xvhdl_prj = "tmp_${stem}_xvhdl.prj";
|
my $tfile_xvhdl_prj = "tmp_${stem}_xvhdl.prj";
|
print "cat > $tfile_xvhdl_prj <
|
print "cat > $tfile_xvhdl_prj <
|
print "#compile vhdl source files\n";
|
print "#compile vhdl source files\n";
|
foreach (@srcfile_list_vhd) {
|
foreach (@srcfile_list_vhd) {
|
print "vhdl xil_defaultlib ../$_\n";
|
print "vhdl xil_defaultlib ../$_\n";
|
}
|
}
|
print "#do not sort compile order\n";
|
print "#do not sort compile order\n";
|
print "nosort\n";
|
print "nosort\n";
|
print "tmp_xvhdl_end_token\n";
|
print "tmp_xvhdl_end_token\n";
|
print "#\n";
|
print "#\n";
|
|
|
my $opts_xvhdl = "-m64 --relax";
|
my $opts_xvhdl = "-m64 --relax";
|
print "xtwv xvhdl $opts_xvhdl -prj $tfile_xvhdl_prj 2>&1 |\\\n";
|
print "xtwv xvhdl $opts_xvhdl -prj $tfile_xvhdl_prj 2>&1 |\\\n";
|
print " tee xvhdl_${stem}.log\n";
|
print " tee xvhdl_${stem}.log\n";
|
print 'exitstatus=$?' . "\n";
|
print 'exitstatus=$?' . "\n";
|
print "rm -f $tfile_xvhdl_prj\n";
|
print "rm -f $tfile_xvhdl_prj\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print "#\n";
|
print "#\n";
|
}
|
}
|
|
|
if (scalar @srcfile_list_c) {
|
if (scalar @srcfile_list_c) {
|
print "# ---------- xsc step\n";
|
print "# ---------- xsc step\n";
|
print "xtwv xsc";
|
print "xtwv xsc";
|
foreach (@srcfile_list_c) {
|
foreach (@srcfile_list_c) {
|
print " \\\n ../$_";
|
print " \\\n ../$_";
|
}
|
}
|
print "\n";
|
print "\n";
|
print 'exitstatus=$?' . "\n";
|
print 'exitstatus=$?' . "\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print "#\n";
|
print "#\n";
|
}
|
}
|
|
|
# Note: xelab -mt auto doesn't seem to work, use --mt `nproc`
|
# Note: xelab -mt auto doesn't seem to work, use --mt `nproc`
|
print "# ---------- xelab step\n";
|
print "# ---------- xelab step\n";
|
print "xtwv xelab --relax --debug typical --mt $nproc -m64 \\\n";
|
print "xtwv xelab --relax --debug typical --mt $nproc -m64 \\\n";
|
print " -L xil_defaultlib";
|
print " -L xil_defaultlib";
|
print " -L simprims_ver" if $is_tsim;
|
print " -L simprims_ver" if $is_tsim;
|
print " -L unisims_ver" if $is_veri && ! ($is_bsim || $is_tsim);
|
print " -L unisims_ver" if $is_veri && ! ($is_bsim || $is_tsim);
|
print " \\\n";
|
print " \\\n";
|
if (scalar @srcfile_list_c) {
|
if (scalar @srcfile_list_c) {
|
print " --sv_lib dpi \\\n";
|
print " --sv_lib dpi \\\n";
|
}
|
}
|
if ($is_tsim) {
|
if ($is_tsim) {
|
print " -transport_int_delays -pulse_r 0 -pulse_int_r 0 \\\n";
|
print " -transport_int_delays -pulse_r 0 -pulse_int_r 0 \\\n";
|
}
|
}
|
print " --snapshot $stem \\\n";
|
print " --snapshot $stem \\\n";
|
print " -log xelab_${stem}.log \\\n";
|
print " -log xelab_${stem}.log \\\n";
|
print " xil_defaultlib.$top";
|
print " xil_defaultlib.$top";
|
print " xil_defaultlib.glbl" if $is_tsim || ($is_veri && ! $is_bsim);
|
print " xil_defaultlib.glbl" if $is_tsim || ($is_veri && ! $is_bsim);
|
print " \n";
|
print " \n";
|
print 'exitstatus=$?' . "\n";
|
print 'exitstatus=$?' . "\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n";
|
print "#\n";
|
print "#\n";
|
|
|
my $cwd = getcwd();
|
my $cwd = getcwd();
|
# use in forwarder full absolute path to relevant xsim.dir
|
# use in forwarder full absolute path to relevant xsim.dir
|
# this allows to call the tb from every directory
|
# this allows to call the tb from every directory
|
|
|
print "# ---------- create forwarder\n";
|
print "# ---------- create forwarder\n";
|
print "popd\n";
|
print "popd\n";
|
print "if [ -x \"${workdir}/xsim.dir/${stem}/xsimk\" ]\n";
|
print "if [ -x \"${workdir}/xsim.dir/${stem}/xsimk\" ]\n";
|
print "then\n";
|
print "then\n";
|
print "#\n";
|
print "#\n";
|
print "cat > $fname_forwarder <
|
print "cat > $fname_forwarder <
|
print "#!/bin/sh\n";
|
print "#!/bin/sh\n";
|
print "rm -rf xsim.dir\n";
|
print "rm -rf xsim.dir\n";
|
print "ln -s ${cwd}/${workdir}/xsim.dir xsim.dir\n";
|
print "ln -s ${cwd}/${workdir}/xsim.dir xsim.dir\n";
|
# Note: double escape \"\\\$\@\" needed to ensure file contains "$@"
|
# Note: double escape \"\\\$\@\" needed to ensure file contains "$@"
|
print "exec xtwv xsim ${stem} \"\\\$\@\"\n";
|
print "exec xtwv xsim ${stem} \"\\\$\@\"\n";
|
print "forwarder_end_token\n";
|
print "forwarder_end_token\n";
|
print "#\n";
|
print "#\n";
|
print "chmod +x $fname_forwarder\n";
|
print "chmod +x $fname_forwarder\n";
|
print "fi\n";
|
print "fi\n";
|
}
|
}
|
|
|
# --dep_ghdl ---------------------------------------------------------
|
# --dep_ghdl ---------------------------------------------------------
|
|
|
if (exists $opts{dep_ghdl}) {
|
if (exists $opts{dep_ghdl}) {
|
|
|
print "#\n";
|
print "#\n";
|
print "$stem : $stem.dep_ghdl\n";
|
print "$stem : $stem.dep_ghdl\n";
|
|
|
if ($sim_mode eq 'ssim') {
|
if ($sim_mode eq 'ssim') {
|
foreach my $type (qw(f o r t)) {
|
foreach my $type (qw(f o r t)) {
|
my $stem_ghdl = $stem;
|
my $stem_ghdl = $stem;
|
$stem_ghdl =~ s/_ssim$/_${type}sim/;
|
$stem_ghdl =~ s/_ssim$/_${type}sim/;
|
print "$stem_ghdl : $stem.dep_ghdl\n";
|
print "$stem_ghdl : $stem.dep_ghdl\n";
|
}
|
}
|
print "#\n";
|
print "#\n";
|
}
|
}
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
if (/\.c$/) {
|
if (/\.c$/) {
|
my $ofile = $_; # copy to break alias for following s///
|
my $ofile = $_; # copy to break alias for following s///
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s/\.c$/.o/; # object file name
|
$ofile =~ s/\.c$/.o/; # object file name
|
print "$stem : $ofile\n"; # depend on C source object file
|
print "$stem : $ofile\n"; # depend on C source object file
|
# C source object compilation dependence
|
# C source object compilation dependence
|
open (ODEPFILE, ">$ofile.dep_ghdl") or
|
open (ODEPFILE, ">$ofile.dep_ghdl") or
|
die "can't write $ofile.dep_ghdl: $!";
|
die "can't write $ofile.dep_ghdl: $!";
|
print ODEPFILE "$ofile : $_\n";
|
print ODEPFILE "$ofile : $_\n";
|
print ODEPFILE "\t\$(COMPILE.c) \$(OUTPUT_OPTION) \$<\n";
|
print ODEPFILE "\t\$(COMPILE.c) \$(OUTPUT_OPTION) \$<\n";
|
close ODEPFILE;
|
close ODEPFILE;
|
} else {
|
} else {
|
print "$stem : $_\n";
|
print "$stem : $_\n";
|
}
|
}
|
}
|
}
|
|
|
# Notes: _fsim only for ISE useful
|
# Notes: _fsim only for ISE useful
|
# _tsim only for VIV useful
|
# _tsim only for VIV useful
|
if ($sim_mode eq 'ssim') {
|
if ($sim_mode eq 'ssim') {
|
foreach my $type (qw(f o r t)) {
|
foreach my $type (qw(f o r t)) {
|
my $stem_ghdl = $stem;
|
my $stem_ghdl = $stem;
|
$stem_ghdl =~ s/_ssim$/_${type}sim/;
|
$stem_ghdl =~ s/_ssim$/_${type}sim/;
|
|
|
print "#\n";
|
print "#\n";
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
if (/\.c$/) {
|
if (/\.c$/) {
|
$file =~ s{^.*/}{}; # remove directory path
|
$file =~ s{^.*/}{}; # remove directory path
|
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
} else {
|
} else {
|
$file =~ s/_ssim\.vhd$/_${type}sim.vhd/;
|
$file =~ s/_ssim\.vhd$/_${type}sim.vhd/;
|
}
|
}
|
print "$stem_ghdl : $file\n";
|
print "$stem_ghdl : $file\n";
|
}
|
}
|
}
|
}
|
|
|
}
|
}
|
|
|
write_vbomdep("$stem.dep_ghdl");
|
write_vbomdep("$stem.dep_ghdl");
|
|
|
}
|
}
|
|
|
# --dep_xst ----------------------------------------------------------
|
# --dep_xst ----------------------------------------------------------
|
|
|
if (exists $opts{dep_xst}) {
|
if (exists $opts{dep_xst}) {
|
print "#\n";
|
print "#\n";
|
print "$stem.ngc : $stem.dep_xst\n";
|
print "$stem.ngc : $stem.dep_xst\n";
|
print "#\n";
|
print "#\n";
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
print "$stem.ngc : $_\n";
|
print "$stem.ngc : $_\n";
|
}
|
}
|
# handle cpp preprocessed ucf's
|
# handle cpp preprocessed ucf's
|
foreach (@ucf_cpp_list) {
|
foreach (@ucf_cpp_list) {
|
my $file = $_;
|
my $file = $_;
|
$file =~ s/\.ucf$//;
|
$file =~ s/\.ucf$//;
|
print "#\n";
|
print "#\n";
|
print "$file.ncd : $file.ucf\n";
|
print "$file.ncd : $file.ucf\n";
|
print "include $file.dep_ucf_cpp\n";
|
print "include $file.dep_ucf_cpp\n";
|
}
|
}
|
# handle plain ucf's
|
# handle plain ucf's
|
if (scalar(@ucf_cpp_list)==0 && -r "$stem.ucf") {
|
if (scalar(@ucf_cpp_list)==0 && -r "$stem.ucf") {
|
print "#\n";
|
print "#\n";
|
print "$stem.ncd : $stem.ucf\n";
|
print "$stem.ncd : $stem.ucf\n";
|
}
|
}
|
write_vbomdep("$stem.dep_xst");
|
write_vbomdep("$stem.dep_xst");
|
}
|
}
|
|
|
# --dep_isim ---------------------------------------------------------
|
# --dep_isim ---------------------------------------------------------
|
|
|
if (exists $opts{dep_isim}) {
|
if (exists $opts{dep_isim}) {
|
my $stem_isim = $stem . "_ISim";
|
my $stem_isim = $stem . "_ISim";
|
|
|
$stem_isim =~ s/_ssim_ISim$/_ISim_ssim/ if ($sim_mode eq 'ssim');
|
$stem_isim =~ s/_ssim_ISim$/_ISim_ssim/ if ($sim_mode eq 'ssim');
|
|
|
my $stem_fsim_isim = $stem_isim;
|
my $stem_fsim_isim = $stem_isim;
|
my $stem_tsim_isim = $stem_isim;
|
my $stem_tsim_isim = $stem_isim;
|
$stem_fsim_isim =~ s/_ssim$/_fsim/;
|
$stem_fsim_isim =~ s/_ssim$/_fsim/;
|
$stem_tsim_isim =~ s/_ssim$/_tsim/;
|
$stem_tsim_isim =~ s/_ssim$/_tsim/;
|
|
|
print "#\n";
|
print "#\n";
|
print "$stem_isim : $stem.dep_isim\n";
|
print "$stem_isim : $stem.dep_isim\n";
|
if ($sim_mode eq 'ssim') {
|
if ($sim_mode eq 'ssim') {
|
print "$stem_fsim_isim : $stem.dep_isim\n";
|
print "$stem_fsim_isim : $stem.dep_isim\n";
|
print "$stem_tsim_isim : $stem.dep_isim\n";
|
print "$stem_tsim_isim : $stem.dep_isim\n";
|
}
|
}
|
print "#\n";
|
print "#\n";
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
print "$stem_isim : $_\n";
|
print "$stem_isim : $_\n";
|
}
|
}
|
|
|
if ($sim_mode eq 'ssim') {
|
if ($sim_mode eq 'ssim') {
|
|
|
print "#\n";
|
print "#\n";
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
print "$stem_fsim_isim : $file\n";
|
print "$stem_fsim_isim : $file\n";
|
}
|
}
|
|
|
print "#\n";
|
print "#\n";
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
$file =~ s/_ssim\.vhd$/_tsim.vhd/;
|
$file =~ s/_ssim\.vhd$/_tsim.vhd/;
|
print "$stem_tsim_isim : $file\n";
|
print "$stem_tsim_isim : $file\n";
|
}
|
}
|
|
|
}
|
}
|
|
|
write_vbomdep("$stem.dep_isim");
|
write_vbomdep("$stem.dep_isim");
|
}
|
}
|
|
|
# --dep_vsyn ---------------------------------------------------------
|
# --dep_vsyn ---------------------------------------------------------
|
|
|
if (exists $opts{dep_vsyn}) {
|
if (exists $opts{dep_vsyn}) {
|
print "#\n";
|
print "#\n";
|
print "$stem.bit : $stem.dep_vsyn\n";
|
print "$stem.bit : $stem.dep_vsyn\n";
|
print "#\n";
|
print "#\n";
|
my @files;
|
my @files;
|
push @files, @srcfile_list;
|
push @files, @srcfile_list;
|
push @files, @xdcfile_list;
|
push @files, @xdcfile_list;
|
foreach (@files) {
|
foreach (@files) {
|
print "$stem.bit : $_\n";
|
print "$stem.bit : $_\n";
|
}
|
}
|
print "#\n";
|
print "#\n";
|
foreach (@files) {
|
foreach (@files) {
|
print "${stem}_syn.dcp : $_\n";
|
print "${stem}_syn.dcp : $_\n";
|
}
|
}
|
print "#\n";
|
print "#\n";
|
foreach (@files) {
|
foreach (@files) {
|
print "${stem}_rou.dcp : $_\n";
|
print "${stem}_rou.dcp : $_\n";
|
}
|
}
|
write_vbomdep("$stem.dep_vsyn");
|
write_vbomdep("$stem.dep_vsyn");
|
}
|
}
|
|
|
# --dep_vsim ---------------------------------------------------------
|
# --dep_vsim ---------------------------------------------------------
|
|
|
if (exists $opts{dep_vsim}) {
|
if (exists $opts{dep_vsim}) {
|
my $stem_vsim = $stem . "_XSim";
|
my $stem_vsim = $stem . "_XSim";
|
|
|
$stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($sim_mode eq 'ssim');
|
$stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($sim_mode eq 'ssim');
|
|
|
print "#\n";
|
print "#\n";
|
print "$stem_vsim : $stem.dep_vsim\n";
|
print "$stem_vsim : $stem.dep_vsim\n";
|
|
|
if ($sim_mode eq 'ssim') {
|
if ($sim_mode eq 'ssim') {
|
foreach my $type (qw(o r e p t)) {
|
foreach my $type (qw(o r e p t)) {
|
my $stem_xsim = $stem_vsim;
|
my $stem_xsim = $stem_vsim;
|
$stem_xsim =~ s/_ssim$/_${type}sim/;
|
$stem_xsim =~ s/_ssim$/_${type}sim/;
|
print "$stem_xsim : $stem.dep_vsim\n";
|
print "$stem_xsim : $stem.dep_vsim\n";
|
}
|
}
|
}
|
}
|
print "#\n";
|
print "#\n";
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
print "$stem_vsim : $_\n";
|
print "$stem_vsim : $_\n";
|
}
|
}
|
|
|
if ($sim_mode eq 'ssim') {
|
if ($sim_mode eq 'ssim') {
|
|
|
# Note: when --dep_vsim is used for a _ssim.vbom read_vbom will remap
|
# Note: when --dep_vsim is used for a _ssim.vbom read_vbom will remap
|
# _ssim.vhd to _ssim.v depending on $xsim_lang. [ept]sim always uses
|
# _ssim.vhd to _ssim.v depending on $xsim_lang. [ept]sim always uses
|
# verilog, that's why there is a explict mapping below.
|
# verilog, that's why there is a explict mapping below.
|
|
|
foreach my $type (qw(o r e p t)) {
|
foreach my $type (qw(o r e p t)) {
|
my $stem_xsim = $stem_vsim;
|
my $stem_xsim = $stem_vsim;
|
$stem_xsim =~ s/_ssim$/_${type}sim/;
|
$stem_xsim =~ s/_ssim$/_${type}sim/;
|
|
|
print "#\n";
|
print "#\n";
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
$file =~ s/_ssim\.(v|vhd)$/_${type}sim.$1/;
|
$file =~ s/_ssim\.(v|vhd)$/_${type}sim.$1/;
|
$file =~ s/_([ept])sim\.vhd$/_${1}sim.v/; # see Note above
|
$file =~ s/_([ept])sim\.vhd$/_${1}sim.v/; # see Note above
|
print "$stem_xsim : $file\n";
|
print "$stem_xsim : $file\n";
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
write_vbomdep("$stem.dep_vsim");
|
write_vbomdep("$stem.dep_vsim");
|
}
|
}
|
|
|
# --ghdl_export or xst_export or isim_export -------------------------
|
# --ghdl_export or xst_export or isim_export -------------------------
|
|
|
if (exists $opts{ghdl_export} or
|
if (exists $opts{ghdl_export} or
|
exists $opts{xst_export} or
|
exists $opts{xst_export} or
|
exists $opts{isim_export}) {
|
exists $opts{isim_export}) {
|
my $edir;
|
my $edir;
|
$edir = $opts{ghdl_export} if exists $opts{ghdl_export};
|
$edir = $opts{ghdl_export} if exists $opts{ghdl_export};
|
$edir = $opts{xst_export} if exists $opts{xst_export};
|
$edir = $opts{xst_export} if exists $opts{xst_export};
|
$edir = $opts{isim_export} if exists $opts{isim_export};
|
$edir = $opts{isim_export} if exists $opts{isim_export};
|
|
|
if (not -d $edir) {
|
if (not -d $edir) {
|
print STDERR "vbomconv-I: create target directory $edir\n";
|
print STDERR "vbomconv-I: create target directory $edir\n";
|
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
} else {
|
} else {
|
print STDERR "vbomconv-I: target directory $edir already exists\n";
|
print STDERR "vbomconv-I: target directory $edir already exists\n";
|
}
|
}
|
|
|
open(PFILE, ">$edir/$stem.prj") or die "can't write open $edir/$stem.prj: $!";
|
open(PFILE, ">$edir/$stem.prj") or die "can't write open $edir/$stem.prj: $!";
|
|
|
foreach (@srcfile_list) {
|
foreach (@srcfile_list) {
|
my $fname = $_;
|
my $fname = $_;
|
my $fdpath = ".";
|
my $fdpath = ".";
|
if (m{(.*)/(.*)}) {
|
if (m{(.*)/(.*)}) {
|
$fname = $2;
|
$fname = $2;
|
$fdpath = $1;
|
$fdpath = $1;
|
}
|
}
|
copy_edir($_, $edir);
|
copy_edir($_, $edir);
|
print PFILE "vhdl work $fname\n";
|
print PFILE "vhdl work $fname\n";
|
}
|
}
|
|
|
close(PFILE);
|
close(PFILE);
|
|
|
# Note: currently no xflow opt files exported !!
|
# Note: currently no xflow opt files exported !!
|
if (exists $opts{xst_export}) {
|
if (exists $opts{xst_export}) {
|
open(XFILE, ">$edir/$stem.xcf") or
|
open(XFILE, ">$edir/$stem.xcf") or
|
die "can't write open $edir/$stem.xcf: $!";
|
die "can't write open $edir/$stem.xcf: $!";
|
close(XFILE);
|
close(XFILE);
|
|
|
foreach (glob("*.xcf")) { copy_edir($_, $edir); }
|
foreach (glob("*.xcf")) { copy_edir($_, $edir); }
|
|
|
if (-r "$stem.ucf_cpp") {
|
if (-r "$stem.ucf_cpp") {
|
system "/bin/sh", "-c", "make $stem.ucf";
|
system "/bin/sh", "-c", "make $stem.ucf";
|
}
|
}
|
|
|
foreach (glob("*.ucf")) { copy_edir($_, $edir); }
|
foreach (glob("*.ucf")) { copy_edir($_, $edir); }
|
}
|
}
|
|
|
}
|
}
|
|
|
# --vsyn_export or vsim_export ---------------------------------------
|
# --vsyn_export or vsim_export ---------------------------------------
|
|
|
if (exists $opts{vsyn_export} or
|
if (exists $opts{vsyn_export} or
|
exists $opts{vsim_export}) {
|
exists $opts{vsim_export}) {
|
my $edir;
|
my $edir;
|
$edir = $opts{vsyn_export} if exists $opts{vsyn_export};
|
$edir = $opts{vsyn_export} if exists $opts{vsyn_export};
|
$edir = $opts{vsim_export} if exists $opts{vsim_export};
|
$edir = $opts{vsim_export} if exists $opts{vsim_export};
|
|
|
if (not -d $edir) {
|
if (not -d $edir) {
|
print STDERR "vbomconv-I: create target directory $edir\n";
|
print STDERR "vbomconv-I: create target directory $edir\n";
|
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
} else {
|
} else {
|
print STDERR "vbomconv-I: target directory $edir already exists\n";
|
print STDERR "vbomconv-I: target directory $edir already exists\n";
|
}
|
}
|
|
|
my @filist;
|
my @filist;
|
push @filist, @srcfile_list;
|
push @filist, @srcfile_list;
|
push @filist, @xdcfile_list;
|
push @filist, @xdcfile_list;
|
my @fl_syn;
|
my @fl_syn;
|
my @fl_sim;
|
my @fl_sim;
|
my @fl_xdc;
|
my @fl_xdc;
|
|
|
foreach my $fi (@filist) {
|
foreach my $fi (@filist) {
|
my $fname = $fi;
|
my $fname = $fi;
|
my $fdpath = ".";
|
my $fdpath = ".";
|
if ($fi =~ m{(.*)/(.*)}) {
|
if ($fi =~ m{(.*)/(.*)}) {
|
$fname = $2;
|
$fname = $2;
|
$fdpath = $1;
|
$fdpath = $1;
|
}
|
}
|
|
|
copy_edir($fi, $edir);
|
copy_edir($fi, $edir);
|
|
|
if ($fname =~ m{\.(vhd|sv)$}) { # .vhd or .sv
|
if ($fname =~ m{\.(vhd|sv)$}) { # .vhd or .sv
|
if ($srcfile_synsim{$fi} eq 'syn') {
|
if ($srcfile_synsim{$fi} eq 'syn') {
|
push @fl_syn, $fname;
|
push @fl_syn, $fname;
|
} else {
|
} else {
|
push @fl_sim, $fname;
|
push @fl_sim, $fname;
|
}
|
}
|
} elsif ($fname =~ m{\.c}) { # .c
|
} elsif ($fname =~ m{\.c}) { # .c
|
printf "+++2 $fi\n";
|
printf "+++2 $fi\n";
|
push @fl_sim, $fname;
|
push @fl_sim, $fname;
|
} elsif ($fname =~ m{\.xdc}) { # .xdc
|
} elsif ($fname =~ m{\.xdc}) { # .xdc
|
push @fl_xdc, $fname;
|
push @fl_xdc, $fname;
|
} else {
|
} else {
|
print STDERR "vbomconv-W: file $fname not processed (unknown type)\n";
|
print STDERR "vbomconv-W: file $fname not processed (unknown type)\n";
|
}
|
}
|
}
|
}
|
|
|
open(TFILE, ">$edir/$stem.tcl") or die "can't write open $edir/$stem.tcl: $!";
|
open(TFILE, ">$edir/$stem.tcl") or die "can't write open $edir/$stem.tcl: $!";
|
|
|
print TFILE "#\n";
|
print TFILE "#\n";
|
print TFILE "# setup file lists\n";
|
print TFILE "# setup file lists\n";
|
print TFILE "#\n";
|
print TFILE "#\n";
|
|
|
print TFILE "set syn_files {\n";
|
print TFILE "set syn_files {\n";
|
foreach (@fl_syn) {
|
foreach (@fl_syn) {
|
print TFILE " $_\n";
|
print TFILE " $_\n";
|
}
|
}
|
print TFILE "}\n";
|
print TFILE "}\n";
|
print TFILE "\n";
|
print TFILE "\n";
|
|
|
print TFILE "set sim_files {\n";
|
print TFILE "set sim_files {\n";
|
foreach (@fl_sim) {
|
foreach (@fl_sim) {
|
print TFILE " $_\n";
|
print TFILE " $_\n";
|
}
|
}
|
print TFILE "}\n";
|
print TFILE "}\n";
|
print TFILE "\n";
|
print TFILE "\n";
|
|
|
print TFILE "set xdc_files {\n";
|
print TFILE "set xdc_files {\n";
|
foreach (@fl_xdc) {
|
foreach (@fl_xdc) {
|
print TFILE " $_\n";
|
print TFILE " $_\n";
|
}
|
}
|
print TFILE "}\n";
|
print TFILE "}\n";
|
print TFILE "\n";
|
print TFILE "\n";
|
|
|
print TFILE 'set obj [get_filesets sources_1]' . "\n";
|
print TFILE 'set obj [get_filesets sources_1]' . "\n";
|
print TFILE 'add_files -norecurse -fileset $obj $syn_files' . "\n";
|
print TFILE 'add_files -norecurse -fileset $obj $syn_files' . "\n";
|
printf TFILE 'set_property "top" "%s" $obj' . "\n", $top;
|
printf TFILE 'set_property "top" "%s" $obj' . "\n", $top;
|
print TFILE "\n";
|
print TFILE "\n";
|
|
|
if (scalar @fl_sim) {
|
if (scalar @fl_sim) {
|
print TFILE 'set obj [get_filesets sim_1]' . "\n";
|
print TFILE 'set obj [get_filesets sim_1]' . "\n";
|
print TFILE 'add_files -norecurse -fileset $obj $sim_files' . "\n";
|
print TFILE 'add_files -norecurse -fileset $obj $sim_files' . "\n";
|
print TFILE "\n";
|
print TFILE "\n";
|
}
|
}
|
|
|
if (scalar @fl_xdc) {
|
if (scalar @fl_xdc) {
|
print TFILE 'set obj [get_filesets constrs_1]' . "\n";
|
print TFILE 'set obj [get_filesets constrs_1]' . "\n";
|
print TFILE 'add_files -norecurse -fileset $obj $xdc_files' . "\n";
|
print TFILE 'add_files -norecurse -fileset $obj $xdc_files' . "\n";
|
print TFILE "\n";
|
print TFILE "\n";
|
}
|
}
|
|
|
close(TFILE);
|
close(TFILE);
|
|
|
|
|
}
|
}
|
|
|
# --get_top ----------------------------------------------------------
|
# --get_top ----------------------------------------------------------
|
|
|
if (exists $opts{get_top}) {
|
if (exists $opts{get_top}) {
|
print "$top\n";
|
print "$top\n";
|
}
|
}
|
|
|
# --flist ------------------------------------------------------------
|
# --flist ------------------------------------------------------------
|
|
|
if (exists $opts{flist}) {
|
if (exists $opts{flist}) {
|
|
|
my @flist;
|
my @flist;
|
|
|
push @flist, @srcfile_list;
|
push @flist, @srcfile_list;
|
push @flist, sort keys %vbom_done;
|
push @flist, sort keys %vbom_done;
|
|
|
if (scalar(@ucf_cpp_list)) {
|
if (scalar(@ucf_cpp_list)) {
|
foreach (@ucf_cpp_list) {
|
foreach (@ucf_cpp_list) {
|
push @flist, $_."_cpp";
|
push @flist, $_."_cpp";
|
}
|
}
|
} else {
|
} else {
|
if (-r "$stem.ucf") {
|
if (-r "$stem.ucf") {
|
push @flist, "$stem.ucf";
|
push @flist, "$stem.ucf";
|
}
|
}
|
}
|
}
|
|
|
push @flist, @xdcfile_list;
|
push @flist, @xdcfile_list;
|
|
|
foreach (sort @flist) {
|
foreach (sort @flist) {
|
my $fname = $_;
|
my $fname = $_;
|
my $fdpath = ".";
|
my $fdpath = ".";
|
if (m{(.*)/(.*)}) {
|
if (m{(.*)/(.*)}) {
|
$fname = $2;
|
$fname = $2;
|
$fdpath = $1;
|
$fdpath = $1;
|
}
|
}
|
print "$fdpath/$fname\n";
|
print "$fdpath/$fname\n";
|
}
|
}
|
|
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub read_vbom {
|
sub read_vbom {
|
my ($vbom) = @_;
|
my ($vbom) = @_;
|
|
|
print STDERR "-- open $vbom\n" if $do_trace;
|
print STDERR "-- open $vbom\n" if $do_trace;
|
|
|
open (IFILE, $vbom) or die "can't open for read $vbom: $!";
|
open (IFILE, $vbom) or die "can't open for read $vbom: $!";
|
|
|
my $vbom_path = "";
|
my $vbom_path = "";
|
my $vbom_file = $vbom;
|
my $vbom_file = $vbom;
|
if ($vbom =~ m{^(.*)/([a-zA-Z0-9_.]*)$}) {
|
if ($vbom =~ m{^(.*)/([a-zA-Z0-9_.]*)$}) {
|
$vbom_path = $1;
|
$vbom_path = $1;
|
$vbom_file = $2;
|
$vbom_file = $2;
|
}
|
}
|
|
|
$vbom_done{$vbom} += 1; # mark this vbom already read
|
$vbom_done{$vbom} += 1; # mark this vbom already read
|
|
|
while () {
|
while () {
|
chomp;
|
chomp;
|
next if /^\s*#/; # drop comments
|
next if /^\s*#/; # drop comments
|
next if /^\s*$/; # drop empty lines
|
next if /^\s*$/; # drop empty lines
|
|
|
s/\s*$//; # drop trailing blanks
|
s/\s*$//; # drop trailing blanks
|
|
|
# process parameter definitions
|
# process parameter definitions
|
if (m{([\w]+)\s*=\s*(.*)}) {
|
if (m{([\w]+)\s*=\s*(.*)}) {
|
my $para = $1;
|
my $para = $1;
|
my $val = $2;
|
my $val = $2;
|
if ($val eq "") {
|
if ($val eq "") {
|
print STDERR "vbomconv-E: invalid \'$_\' in $vbom_file\n";
|
print STDERR "vbomconv-E: invalid \'$_\' in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
if (not exists $para_tbl{$para}) {
|
if (not exists $para_tbl{$para}) {
|
$para_tbl{$para} = canon_fname($vbom_path, $val);
|
$para_tbl{$para} = canon_fname($vbom_path, $val);
|
print STDERR "--- define \${$para} = $val\n" if $do_trace;
|
print STDERR "--- define \${$para} = $val\n" if $do_trace;
|
} else {
|
} else {
|
print STDERR "--- ignore \${$para} = $val\n" if $do_trace;
|
print STDERR "--- ignore \${$para} = $val\n" if $do_trace;
|
}
|
}
|
next;
|
next;
|
}
|
}
|
|
|
# process parameter substitutions
|
# process parameter substitutions
|
while (m{\$\{([\w]+)\s*(:=)?\s*(.*?)\}}) {
|
while (m{\$\{([\w]+)\s*(:=)?\s*(.*?)\}}) {
|
my $para = $1;
|
my $para = $1;
|
my $del = $2;
|
my $del = $2;
|
my $val = $3;
|
my $val = $3;
|
my $pre = $`;
|
my $pre = $`;
|
my $post = $';
|
my $post = $';
|
if (defined $del && $del eq ":=") {
|
if (defined $del && $del eq ":=") {
|
if (not exists $para_tbl{$para}) {
|
if (not exists $para_tbl{$para}) {
|
$para_tbl{$para} = canon_fname($vbom_path, $val);
|
$para_tbl{$para} = canon_fname($vbom_path, $val);
|
print STDERR "--- define \${$para := $val}\n" if $do_trace;
|
print STDERR "--- define \${$para := $val}\n" if $do_trace;
|
} else {
|
} else {
|
print STDERR "--- ignore \${$para := $val}\n" if $do_trace;
|
print STDERR "--- ignore \${$para := $val}\n" if $do_trace;
|
}
|
}
|
}
|
}
|
if (defined $para_tbl{$para}) {
|
if (defined $para_tbl{$para}) {
|
if ($do_trace) {
|
if ($do_trace) {
|
print STDERR "--- use \${$para} -> $para_tbl{$para}\n";
|
print STDERR "--- use \${$para} -> $para_tbl{$para}\n";
|
} else {
|
} else {
|
## print STDERR "vbomconv-I: \${$para} -> $para_tbl{$para}\n";
|
## print STDERR "vbomconv-I: \${$para} -> $para_tbl{$para}\n";
|
}
|
}
|
$_ = $pre . "!" . $para_tbl{$para} . $post;
|
$_ = $pre . "!" . $para_tbl{$para} . $post;
|
} else {
|
} else {
|
print STDERR "vbomconv-E: undefined \${$para} in $vbom_file\n";
|
print STDERR "vbomconv-E: undefined \${$para} in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
}
|
}
|
|
|
if (/^\[([a-z,]+)\]\s*(.+)$/) { # [xxx,yyy] tag seen
|
if (/^\[([a-z,]+)\]\s*(.+)$/) { # [xxx,yyy] tag seen
|
my $qual = $1;
|
my $qual = $1;
|
my $name = $2;
|
my $name = $2;
|
my $keep = $is_any;
|
my $keep = $is_any;
|
## print STDERR "+++1 |$qual|$name|$vbom|\n";
|
## print STDERR "+++1 |$qual|$name|$vbom|\n";
|
foreach my $pref (split /,/,$qual) {
|
foreach my $pref (split /,/,$qual) {
|
if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim|ise|viv)$/) {
|
if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim|ise|viv)$/) {
|
$keep = 1 if ($pref eq "ghdl" && $is_ghdl);
|
$keep = 1 if ($pref eq "ghdl" && $is_ghdl);
|
$keep = 1 if ($pref eq "xst" && $is_xst);
|
$keep = 1 if ($pref eq "xst" && $is_xst);
|
$keep = 1 if ($pref eq "isim" && $is_isim);
|
$keep = 1 if ($pref eq "isim" && $is_isim);
|
$keep = 1 if ($pref eq "vsyn" && $is_vsyn);
|
$keep = 1 if ($pref eq "vsyn" && $is_vsyn);
|
$keep = 1 if ($pref eq "vsim" && $is_vsim);
|
$keep = 1 if ($pref eq "vsim" && $is_vsim);
|
$keep = 1 if ($pref eq "sim" && $is_sim);
|
$keep = 1 if ($pref eq "sim" && $is_sim);
|
$keep = 1 if ($pref eq "ise" && $is_ise);
|
$keep = 1 if ($pref eq "ise" && $is_ise);
|
$keep = 1 if ($pref eq "viv" && $is_viv);
|
$keep = 1 if ($pref eq "viv" && $is_viv);
|
} else {
|
} else {
|
print STDERR "vbomconv-W: unknown tag [$pref] in $vbom_file\n";
|
print STDERR "vbomconv-W: unknown tag [$pref] in $vbom_file\n";
|
}
|
}
|
}
|
}
|
if (not $keep) {
|
if (not $keep) {
|
print STDERR "--- drop \"$_\"\n" if $do_trace;
|
print STDERR "--- drop \"$_\"\n" if $do_trace;
|
next;
|
next;
|
}
|
}
|
$_ = $name; # remove [xxx] tag
|
$_ = $name; # remove [xxx] tag
|
}
|
}
|
|
|
my $tag;
|
my $tag;
|
my $val = $_;
|
my $val = $_;
|
|
|
# detect tag:val lines
|
# detect tag:val lines
|
if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) {
|
if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) {
|
$tag = $1;
|
$tag = $1;
|
$val = $2;
|
$val = $2;
|
|
|
# process @top: lines
|
# process @top: lines
|
if ($tag eq '@top') {
|
if ($tag eq '@top') {
|
$top = $val unless $top_done;
|
$top = $val unless $top_done;
|
next;
|
next;
|
|
|
# process @ucf_cpp: lines
|
# process @ucf_cpp: lines
|
} elsif ($tag eq '@ucf_cpp') {
|
} elsif ($tag eq '@ucf_cpp') {
|
push @ucf_cpp_list, $val;
|
push @ucf_cpp_list, $val;
|
next;
|
next;
|
|
|
# process @xdc: lines
|
# process @xdc: lines
|
} elsif ($tag eq '@xdc') {
|
} elsif ($tag eq '@xdc') {
|
my ($fname,$rphash) = parse_props($val);
|
my ($fname,$rphash) = parse_props($val);
|
$fname = canon_fname($vbom_path, $fname);
|
$fname = canon_fname($vbom_path, $fname);
|
setup_props($fname, $rphash);
|
setup_props($fname, $rphash);
|
push @{$vbom_xdc{$vbom}}, $fname;
|
push @{$vbom_xdc{$vbom}}, $fname;
|
next;
|
next;
|
|
|
# process @lib: lines
|
# process @lib: lines
|
} elsif ($tag eq '@lib') {
|
} elsif ($tag eq '@lib') {
|
if ($val eq 'unisim') {
|
if ($val eq 'unisim') {
|
$has_unisim = 1;
|
$has_unisim = 1;
|
} elsif ($val eq 'unimacro') {
|
} elsif ($val eq 'unimacro') {
|
$has_unimacro = 1;
|
$has_unimacro = 1;
|
} elsif ($val eq 'simprim') {
|
} elsif ($val eq 'simprim') {
|
$has_simprim = 1;
|
$has_simprim = 1;
|
} else {
|
} else {
|
print STDERR "vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n";
|
print STDERR "vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
next;
|
next;
|
|
|
# catch invalid @ tags
|
# catch invalid @ tags
|
} else {
|
} else {
|
print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n";
|
print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
|
|
}
|
}
|
|
|
# split in filename and property list
|
# split in filename and property list
|
my ($fname,$rphash) = parse_props($val);
|
my ($fname,$rphash) = parse_props($val);
|
|
|
# now do model source file mapping
|
# now do model source file mapping
|
my $fname_old = $fname;
|
my $fname_old = $fname;
|
if ($is_ise || $is_ghdl) {
|
if ($is_ise || $is_ghdl) {
|
$fname =~ s{_ssim\.vhd$}{_fsim.vhd} if $sim_mode eq 'fsim';
|
$fname =~ s{_ssim\.vhd$}{_fsim.vhd} if $sim_mode eq 'fsim';
|
$fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim';
|
$fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim';
|
$fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim';
|
$fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim';
|
$fname =~ s{_ssim\.vhd$}{_tsim.vhd} if $sim_mode eq 'tsim';
|
$fname =~ s{_ssim\.vhd$}{_tsim.vhd} if $sim_mode eq 'tsim';
|
}
|
}
|
if ($is_viv) {
|
if ($is_viv) {
|
$fname =~ s{_ssim\.vhd$}{_esim.v} if $sim_mode eq 'esim';
|
$fname =~ s{_ssim\.vhd$}{_esim.v} if $sim_mode eq 'esim';
|
$fname =~ s{_ssim\.vhd$}{_psim.v} if $sim_mode eq 'psim';
|
$fname =~ s{_ssim\.vhd$}{_psim.v} if $sim_mode eq 'psim';
|
$fname =~ s{_ssim\.vhd$}{_tsim.v} if $sim_mode eq 'tsim';
|
$fname =~ s{_ssim\.vhd$}{_tsim.v} if $sim_mode eq 'tsim';
|
if ($is_veri) {
|
if ($is_veri) {
|
$fname =~ s{_ssim\.vhd$}{_ssim.v} if $sim_mode eq 'ssim';
|
$fname =~ s{_ssim\.vhd$}{_ssim.v} if $sim_mode eq 'ssim';
|
$fname =~ s{_ssim\.vhd$}{_osim.v} if $sim_mode eq 'osim';
|
$fname =~ s{_ssim\.vhd$}{_osim.v} if $sim_mode eq 'osim';
|
$fname =~ s{_ssim\.vhd$}{_rsim.v} if $sim_mode eq 'rsim';
|
$fname =~ s{_ssim\.vhd$}{_rsim.v} if $sim_mode eq 'rsim';
|
} else {
|
} else {
|
$fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim';
|
$fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim';
|
$fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim';
|
$fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim';
|
}
|
}
|
}
|
}
|
print STDERR "--- map $fname_old -> $fname\n"
|
print STDERR "--- map $fname_old -> $fname\n"
|
if $do_trace && $fname_old ne $fname;
|
if $do_trace && $fname_old ne $fname;
|
|
|
# process normal .vhd, .v, or .vbom file lines
|
# process normal .vhd, .v, or .vbom file lines
|
# canonize file name unless not already done by filename substitution
|
# canonize file name unless not already done by filename substitution
|
my $fullname;
|
my $fullname;
|
if ($fname =~ m{^!(.*)$}) {
|
if ($fname =~ m{^!(.*)$}) {
|
$fullname = $1;
|
$fullname = $1;
|
} else {
|
} else {
|
$fullname = canon_fname($vbom_path, $fname);
|
$fullname = canon_fname($vbom_path, $fname);
|
}
|
}
|
|
|
# handle properties
|
# handle properties
|
setup_props($fullname, $rphash);
|
setup_props($fullname, $rphash);
|
|
|
# process -UUT property here, with canonized file names
|
# process -UUT property here, with canonized file names
|
if (exists $rphash->{-UUT}) {
|
if (exists $rphash->{-UUT}) {
|
if (defined $uut) {
|
if (defined $uut) {
|
print STDERR "vbomconv-E: duplicate -UUT:, 1st '$uut' 2nd '$val'\n";
|
print STDERR "vbomconv-E: duplicate -UUT:, 1st '$uut' 2nd '$val'\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
$uut = $fullname;
|
$uut = $fullname;
|
}
|
}
|
|
|
# determine whether additional libs needed
|
# determine whether additional libs needed
|
if ($fullname =~ m{_[sor]sim\.vhd$}) { # is ssim, osim or rsim
|
if ($fullname =~ m{_[sor]sim\.vhd$}) { # is ssim, osim or rsim
|
$has_unisim = 1;
|
$has_unisim = 1;
|
}
|
}
|
if ($fullname =~ m{_[ft]sim\.vhd$}) { # is fsim or tsim
|
if ($fullname =~ m{_[ft]sim\.vhd$}) { # is fsim or tsim
|
$has_simprim = 1;
|
$has_simprim = 1;
|
}
|
}
|
|
|
# build vbom table
|
# build vbom table
|
push @{$vbom_files{$vbom}}, $fullname;
|
push @{$vbom_files{$vbom}}, $fullname;
|
print STDERR "--- add $fullname\n" if $do_trace;
|
print STDERR "--- add $fullname\n" if $do_trace;
|
|
|
# if a vbom, queue if not not already read
|
# if a vbom, queue if not not already read
|
if ($fullname =~ m{\.vbom$} && not exists $vbom_done{$fullname} ) {
|
if ($fullname =~ m{\.vbom$} && not exists $vbom_done{$fullname} ) {
|
push @vbom_queue, $fullname;
|
push @vbom_queue, $fullname;
|
print STDERR "--- queue $fullname\n" if $do_trace;
|
print STDERR "--- queue $fullname\n" if $do_trace;
|
}
|
}
|
|
|
}
|
}
|
|
|
$top_done = 1;
|
$top_done = 1;
|
|
|
close (IFILE);
|
close (IFILE);
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub scan_vbom {
|
sub scan_vbom {
|
my ($vbom) = @_;
|
my ($vbom) = @_;
|
|
|
$level += 1;
|
$level += 1;
|
my $rank = 1000*$level + scalar(@{$vbom_files{$vbom}});
|
my $rank = 1000*$level + scalar(@{$vbom_files{$vbom}});
|
print STDERR "--> $level: $vbom\n" if $do_trace;
|
print STDERR "--> $level: $vbom\n" if $do_trace;
|
|
|
die "vbomcov-E excessive vbom stack depth \n" if $level>=1000;
|
die "vbomcov-E excessive vbom stack depth \n" if $level>=1000;
|
|
|
if (exists $vbom_rank{$vbom}) {
|
if (exists $vbom_rank{$vbom}) {
|
$vbom_rank{$vbom}{min} = $level if $level < $vbom_rank{$vbom}{min};
|
$vbom_rank{$vbom}{min} = $level if $level < $vbom_rank{$vbom}{min};
|
$vbom_rank{$vbom}{max} = $level if $level > $vbom_rank{$vbom}{max};
|
$vbom_rank{$vbom}{max} = $level if $level > $vbom_rank{$vbom}{max};
|
} else {
|
} else {
|
$vbom_rank{$vbom} = {min=>$level, max=>$level};
|
$vbom_rank{$vbom} = {min=>$level, max=>$level};
|
}
|
}
|
|
|
foreach my $file (@{$vbom_files{$vbom}}) {
|
foreach my $file (@{$vbom_files{$vbom}}) {
|
$rank -= 1;
|
$rank -= 1;
|
if ($file =~ m{\.vbom$}) {
|
if ($file =~ m{\.vbom$}) {
|
scan_vbom($file);
|
scan_vbom($file);
|
} else {
|
} else {
|
if (exists $srcfile_rank{$file}) {
|
if (exists $srcfile_rank{$file}) {
|
if ($rank > $srcfile_rank{$file}) {
|
if ($rank > $srcfile_rank{$file}) {
|
print STDERR " $file $srcfile_rank{$file} -> $rank\n" if $do_trace;
|
print STDERR " $file $srcfile_rank{$file} -> $rank\n" if $do_trace;
|
$srcfile_rank{$file} = $rank;
|
$srcfile_rank{$file} = $rank;
|
} else {
|
} else {
|
print STDERR " $file $srcfile_rank{$file} (keep)\n" if $do_trace;
|
print STDERR " $file $srcfile_rank{$file} (keep)\n" if $do_trace;
|
}
|
}
|
} else {
|
} else {
|
$srcfile_rank{$file} = $rank;
|
$srcfile_rank{$file} = $rank;
|
print STDERR " $file $srcfile_rank{$file} (new)\n" if $do_trace;
|
print STDERR " $file $srcfile_rank{$file} (new)\n" if $do_trace;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
print STDERR "<-- $level: $vbom\n" if $do_trace;
|
print STDERR "<-- $level: $vbom\n" if $do_trace;
|
$level -= 1;
|
$level -= 1;
|
|
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub do_synsim {
|
sub do_synsim {
|
my ($uut) = @_;
|
my ($uut) = @_;
|
|
|
# all is syn if no @uut defined; preset with sim when @uut defined
|
# all is syn if no @uut defined; preset with sim when @uut defined
|
my $def = (defined $uut) ? 'sim' : 'syn';
|
my $def = (defined $uut) ? 'sim' : 'syn';
|
foreach my $file (keys %srcfile_rank) {
|
foreach my $file (keys %srcfile_rank) {
|
$srcfile_synsim{$file} = $def;
|
$srcfile_synsim{$file} = $def;
|
}
|
}
|
return unless defined $uut;
|
return unless defined $uut;
|
|
|
# if @uut seen separate them
|
# if @uut seen separate them
|
if (defined $uut) {
|
if (defined $uut) {
|
if ($uut =~ m{\.vbom}) { # uut is vbom (behavioral sim)
|
if ($uut =~ m{\.vbom}) { # uut is vbom (behavioral sim)
|
scan_synsim($uut);
|
scan_synsim($uut);
|
} else { # uut is file (post syn sim)
|
} else { # uut is file (post syn sim)
|
$srcfile_synsim{$uut} = 'syn';
|
$srcfile_synsim{$uut} = 'syn';
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub scan_synsim {
|
sub scan_synsim {
|
my ($vbom) = @_;
|
my ($vbom) = @_;
|
|
|
foreach my $file (@{$vbom_files{$vbom}}) {
|
foreach my $file (@{$vbom_files{$vbom}}) {
|
if ($file =~ m{\.vbom$}) {
|
if ($file =~ m{\.vbom$}) {
|
scan_synsim($file);
|
scan_synsim($file);
|
} else {
|
} else {
|
$srcfile_synsim{$file} = 'syn';
|
$srcfile_synsim{$file} = 'syn';
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub copy_edir {
|
sub copy_edir {
|
my ($file, $edir) = @_;
|
my ($file, $edir) = @_;
|
print "cp -p $file $edir\n";
|
print "cp -p $file $edir\n";
|
system("cp -p $file $edir")==0 or die "cp -p failed: $?";
|
system("cp -p $file $edir")==0 or die "cp -p failed: $?";
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub write_vbomdep {
|
sub write_vbomdep {
|
my ($target) = @_;
|
my ($target) = @_;
|
print "#\n";
|
print "#\n";
|
print "# .dep_* on .vbom dependencies\n";
|
print "# .dep_* on .vbom dependencies\n";
|
print "#\n";
|
print "#\n";
|
foreach (sort keys %vbom_done) {
|
foreach (sort keys %vbom_done) {
|
print "$target : $_\n";
|
print "$target : $_\n";
|
}
|
}
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
sub canon_fname {
|
sub canon_fname {
|
my ($vpath,$fname) = @_;
|
my ($vpath,$fname) = @_;
|
# get full relative file name (relative to cwd)
|
# get full relative file name (relative to cwd)
|
$fname = "$vpath/$fname" if $vpath ne "";
|
$fname = "$vpath/$fname" if $vpath ne "";
|
|
|
# remove 'inner' .., e.g. ../x/../y --> ../y
|
# remove 'inner' .., e.g. ../x/../y --> ../y
|
# this will also canonize the file names, thus same file same name
|
# this will also canonize the file names, thus same file same name
|
|
|
my @flist;
|
my @flist;
|
foreach (split "/",$fname) {
|
foreach (split "/",$fname) {
|
if (scalar(@flist) && $flist[$#flist] ne ".." && $_ eq "..") {
|
if (scalar(@flist) && $flist[$#flist] ne ".." && $_ eq "..") {
|
pop @flist;
|
pop @flist;
|
} else {
|
} else {
|
push @flist, $_;
|
push @flist, $_;
|
}
|
}
|
}
|
}
|
|
|
return join "/", @flist;
|
return join "/", @flist;
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
sub parse_props {
|
sub parse_props {
|
my ($val) = @_;
|
my ($val) = @_;
|
my $fname = $val;
|
my $fname = $val;
|
my %phash = ();
|
my %phash = ();
|
if ($val =~ /^\s*(\S+)\s+(-.+)$/) { # "fname -xxx..." seen
|
if ($val =~ /^\s*(\S+)\s+(-.+)$/) { # "fname -xxx..." seen
|
$fname = $1;
|
$fname = $1;
|
my $plist = $2;
|
my $plist = $2;
|
foreach my $pitem (split /\s+/,$plist) {
|
foreach my $pitem (split /\s+/,$plist) {
|
if ($pitem =~ m/^(.*)\:(.*)$/) { # -key:val (not k=v !!)
|
if ($pitem =~ m/^(.*)\:(.*)$/) { # -key:val (not k=v !!)
|
$phash{$1} = $2;
|
$phash{$1} = $2;
|
} else {
|
} else {
|
$phash{$pitem} = '';
|
$phash{$pitem} = '';
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
return ($fname, \%phash);
|
return ($fname, \%phash);
|
|
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
sub setup_props {
|
sub setup_props {
|
my ($fname, $rphash) = @_;
|
my ($fname, $rphash) = @_;
|
$srcfile_prop{$fname} = $rphash;
|
$srcfile_prop{$fname} = $rphash;
|
my $path = '.';
|
my $path = '.';
|
my $name = $fname;
|
my $name = $fname;
|
if ($fname =~ m|^(.+)/(.+)$|) {
|
if ($fname =~ m|^(.+)/(.+)$|) {
|
$path = $1;
|
$path = $1;
|
$name = $2;
|
$name = $2;
|
}
|
}
|
my $stem = $name;
|
my $stem = $name;
|
my $type = '';
|
my $type = '';
|
if ($name =~ m/^(.+)(\..*)/) {
|
if ($name =~ m/^(.+)(\..*)/) {
|
$stem = $1;
|
$stem = $1;
|
$type = $2;
|
$type = $2;
|
}
|
}
|
$srcfile_prop{$fname}->{VBpath} = $path;
|
$srcfile_prop{$fname}->{VBpath} = $path;
|
$srcfile_prop{$fname}->{VBstem} = $stem;
|
$srcfile_prop{$fname}->{VBstem} = $stem;
|
$srcfile_prop{$fname}->{VBtype} = $type;
|
$srcfile_prop{$fname}->{VBtype} = $type;
|
return;
|
return;
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub print_help {
|
sub print_help {
|
print "usage: vbomconf file.vbom\n";
|
print "usage: vbomconf file.vbom\n";
|
print " --help this message\n";
|
print " --help this message\n";
|
print " --trace trace recursive processing of vbom's\n";
|
print " --trace trace recursive processing of vbom's\n";
|
print " --dep_ghdl generate ghdl dependencies for make\n";
|
print " --dep_ghdl generate ghdl dependencies for make\n";
|
print " --dep_xst generate xst dependencies for make\n";
|
print " --dep_xst generate xst dependencies for make\n";
|
print " --dep_isim generate isim dependencies for make\n";
|
print " --dep_isim generate isim dependencies for make\n";
|
print " --dep_vsyn generate vsyn dependencies for make\n";
|
print " --dep_vsyn generate vsyn dependencies for make\n";
|
print " --ghdl_a generate and execute ghdl -a (analyse)\n";
|
print " --ghdl_a generate and execute ghdl -a (analyse)\n";
|
print " --ghdl_a_cmd like ghdl_a, but only print command, no exec\n";
|
print " --ghdl_a_cmd like ghdl_a, but only print command, no exec\n";
|
print " --ghdl_i generate and execute ghdl -i (inspect)\n";
|
print " --ghdl_i generate and execute ghdl -i (inspect)\n";
|
print " --ghdl_i_cmd like ghdl_i, but only print command, no exec\n";
|
print " --ghdl_i_cmd like ghdl_i, but only print command, no exec\n";
|
print " --ghdl_m generate and execute ghdl -m (make)\n";
|
print " --ghdl_m generate and execute ghdl -m (make)\n";
|
print " --ghdl_m_cmd like ghdl_m, but only print command, no exec\n";
|
print " --ghdl_m_cmd like ghdl_m, but only print command, no exec\n";
|
print " --xst_prj generate xst project file\n";
|
print " --xst_prj generate xst project file\n";
|
print " --isim_prj generate isim project file\n";
|
print " --isim_prj generate isim project file\n";
|
print " --vsyn_prj generate vivado synthesis project definition\n";
|
print " --vsyn_prj generate vivado synthesis project definition\n";
|
print " --ghdl_export=s export all ghdl source files into directory s\n";
|
print " --ghdl_export=s export all ghdl source files into directory s\n";
|
print " --xst_export=s export all xst source files into directory s\n";
|
print " --xst_export=s export all xst source files into directory s\n";
|
print " --isim_export=s export all isim source files into directory s\n";
|
print " --isim_export=s export all isim source files into directory s\n";
|
print " --vsyn_export=s export all vsyn source files into directory s\n";
|
print " --vsyn_export=s export all vsyn source files into directory s\n";
|
print " --vsim_export=s export all vsim source files into directory s\n";
|
print " --vsim_export=s export all vsim source files into directory s\n";
|
print " --get_top return top level entity name\n";
|
print " --get_top return top level entity name\n";
|
print " --flist list all files touched by vbom for all tags\n";
|
print " --flist list all files touched by vbom for all tags\n";
|
}
|
}
|
|
|