////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: aximemsim.cpp
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// Filename: aximemsim.cpp
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//
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//
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// Project: Pipelined Wishbone to AXI converter
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// Project: Pipelined Wishbone to AXI converter
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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// Copyright (C) 2016-2018, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This file is part of the pipelined Wishbone to AXI converter project, a
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// modify it under the terms of the GNU General Public License as published
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// project that contains multiple bus bridging designs and formal bus property
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// by the Free Software Foundation, either version 3 of the License, or (at
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// sets.
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// your option) any later version.
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//
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//
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// The bus bridge designs and property sets are free RTL designs: you can
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// redistribute them and/or modify any of them under the terms of the GNU
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// Lesser General Public License as published by the Free Software Foundation,
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// either version 3 of the License, or (at your option) any later version.
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// for more details.
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//
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//
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// The bus bridge designs and property sets are distributed in the hope that
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// You should have received a copy of the GNU General Public License along
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// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// target there if the PDF file isn't present.) If not, see
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with these designs. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/lgpl.html
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include "aximemsim.h"
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#include "aximemsim.h"
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class ADRFIFO {
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class ADRFIFO {
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typedef {
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typedef {
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int id; unsigned addr;
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int id; unsigned addr;
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} ADRFIFOELEMENT;
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} ADRFIFOELEMENT;
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int m_head, m_tail, m_len;
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int m_head, m_tail, m_len;
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int *m_mem;
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int *m_mem;
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public:
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public:
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ADRFIFO(int ln) {
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ADRFIFO(int ln) {
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m_mem = new ADRFIFOELEMENT[ln];
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m_mem = new ADRFIFOELEMENT[ln];
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m_head = m_tail = 0;
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m_head = m_tail = 0;
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m_len = ln;
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m_len = ln;
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}
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}
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void push(int id, unsigned addr) {
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void push(int id, unsigned addr) {
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int nhead = m_head + 1;
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int nhead = m_head + 1;
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if (nhead >= m_len)
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if (nhead >= m_len)
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nhead = 0;
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nhead = 0;
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assert(nhead != m_tail);
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assert(nhead != m_tail);
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m_mem[m_head].id = id;
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m_mem[m_head].id = id;
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m_mem[m_head].addr = addr;
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m_mem[m_head].addr = addr;
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m_head = nhead;
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m_head = nhead;
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}
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}
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bool full(void) {
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bool full(void) {
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int nhead = m_head + 1;
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int nhead = m_head + 1;
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if (nhead >= m_len)
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if (nhead >= m_len)
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nhead = 0;
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nhead = 0;
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return (nhead == m_tail);
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return (nhead == m_tail);
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}
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}
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bool valid(void) {
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bool valid(void) {
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return (m_head != m_tail);
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return (m_head != m_tail);
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}
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}
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int id(void) { return m_mem[m_tail].id; }
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int id(void) { return m_mem[m_tail].id; }
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int addr(void) { return m_mem[m_tail].addr; }
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int addr(void) { return m_mem[m_tail].addr; }
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int pop(void) {
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int pop(void) {
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if (m_tail == m_head)
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if (m_tail == m_head)
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return;
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return;
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m_tail++;
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m_tail++;
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if (m_tail >= m_len)
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if (m_tail >= m_len)
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m_tail = 0;
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m_tail = 0;
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}
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}
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};
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};
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class DATFIFO {
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class DATFIFO {
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typedef {
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typedef {
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unsigned data[4];
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unsigned data[4];
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int strb;
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int strb;
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} DATAFIFOELEMENT;
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} DATAFIFOELEMENT;
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int m_head, m_tail, m_len;
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int m_head, m_tail, m_len;
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int *m_mem;
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int *m_mem;
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public:
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public:
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DATAFIFO(int ln) {
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DATAFIFO(int ln) {
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m_mem = new DATAFIFOELEMENT[ln];
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m_mem = new DATAFIFOELEMENT[ln];
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m_head = m_tail = 0;
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m_head = m_tail = 0;
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m_len = ln;
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m_len = ln;
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}
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}
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void push(int strb, unsigned dat0, unsigned dat1,
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void push(int strb, unsigned dat0, unsigned dat1,
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unsigned dat, unsigned dat3) {
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unsigned dat, unsigned dat3) {
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int nhead = m_head + 1;
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int nhead = m_head + 1;
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if (nhead >= m_len)
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if (nhead >= m_len)
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nhead = 0;
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nhead = 0;
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assert(nhead != m_tail);
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assert(nhead != m_tail);
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m_mem[m_head].strb = id;
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m_mem[m_head].strb = id;
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m_mem[m_head].data[0] = dat0;
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m_mem[m_head].data[0] = dat0;
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m_mem[m_head].data[1] = dat1;
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m_mem[m_head].data[1] = dat1;
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m_mem[m_head].data[2] = dat2;
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m_mem[m_head].data[2] = dat2;
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m_mem[m_head].data[3] = dat3;
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m_mem[m_head].data[3] = dat3;
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m_head = nhead;
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m_head = nhead;
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}
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}
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bool full(void) {
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bool full(void) {
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int nhead = m_head + 1;
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int nhead = m_head + 1;
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if (nhead >= m_len)
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if (nhead >= m_len)
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nhead = 0;
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nhead = 0;
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return (nhead == m_tail);
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return (nhead == m_tail);
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}
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}
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bool valid(void) {
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bool valid(void) {
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return (m_head != m_tail);
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return (m_head != m_tail);
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}
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}
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int strb(void) { return m_mem[m_tail].strb; }
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int strb(void) { return m_mem[m_tail].strb; }
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unsigned *data(void) { return &m_mem[m_tail].data[0]; }
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unsigned *data(void) { return &m_mem[m_tail].data[0]; }
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int pop(void) {
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int pop(void) {
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if (m_tail == m_head)
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if (m_tail == m_head)
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return;
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return;
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m_tail++;
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m_tail++;
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if (m_tail >= m_len)
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if (m_tail >= m_len)
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m_tail = 0;
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m_tail = 0;
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}
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}
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};
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};
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AXIMEMSIM::AXIMEMSIM(unsigned abits) {
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AXIMEMSIM::AXIMEMSIM(unsigned abits) {
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// abits is the number of bits in a memory address, referencing 8-bit
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// abits is the number of bits in a memory address, referencing 8-bit
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// bytes, therefore we can size our memory properly.
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// bytes, therefore we can size our memory properly.
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assert(abits>2);
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assert(abits>2);
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m_len = (1<<(abits-2));
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m_len = (1<<(abits-2));
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m_mask= m_len-1;
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m_mask= m_len-1;
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m_mem = new unsigned[(1<<(abits-2))];
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m_mem = new unsigned[(1<<(abits-2))];
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memset(m_mem, 0, sizeof(unsigned)<<(abits-2));
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memset(m_mem, 0, sizeof(unsigned)<<(abits-2));
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}
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}
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void AXIMEMSIM::apply(AXIBUS &bus) {
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void AXIMEMSIM::apply(AXIBUS &bus) {
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// First, let's validate our inputs ..., and queue up our outputs
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// First, let's validate our inputs ..., and queue up our outputs
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bus.ar.ready = (!m_readfifo.full());
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bus.ar.ready = (!m_readfifo.full());
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bus.aw.ready = (!m_writefifo.full());
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bus.aw.ready = (!m_writefifo.full());
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bus.w.ready = (!m_wdata.full());
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bus.w.ready = (!m_wdata.full());
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if (bus.r.ready)
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if (bus.r.ready)
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bus.r.valid = false;
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bus.r.valid = false;
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if (bus.b.ready)
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if (bus.b.ready)
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bus.b.valid = false;
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bus.b.valid = false;
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if ((bus.ar.ready)&&(!m_readfifo.full())) {
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if ((bus.ar.ready)&&(!m_readfifo.full())) {
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assert(bus.ar.len == 0);
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assert(bus.ar.len == 0);
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assert(bus.ar.size == 5);
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assert(bus.ar.size == 5);
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assert(bus.ar.burst == 1);
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assert(bus.ar.burst == 1);
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assert(bus.ar.lock == 0);
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assert(bus.ar.lock == 0);
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assert(bus.ar.cache == 2);
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assert(bus.ar.cache == 2);
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assert(bus.ar.prot == 2);
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assert(bus.ar.prot == 2);
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assert(bus.ar.qos == 0);
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assert(bus.ar.qos == 0);
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m_readfifo.push(bus.ar.id, bus.ar.addr);
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m_readfifo.push(bus.ar.id, bus.ar.addr);
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}
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}
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if ((bus.aw.ready)&&(!m_writefifo.full())) {
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if ((bus.aw.ready)&&(!m_writefifo.full())) {
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assert(bus.aw.len == 0);
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assert(bus.aw.len == 0);
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assert(bus.aw.size == 5);
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assert(bus.aw.size == 5);
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assert(bus.aw.burst == 1);
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assert(bus.aw.burst == 1);
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assert(bus.aw.lock == 0);
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assert(bus.aw.lock == 0);
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assert(bus.aw.cache == 2);
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assert(bus.aw.cache == 2);
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assert(bus.aw.prot == 2);
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assert(bus.aw.prot == 2);
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assert(bus.aw.qos == 0);
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assert(bus.aw.qos == 0);
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m_awfifo.push(bus.aw.id, bus.aw.addr);
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m_awfifo.push(bus.aw.id, bus.aw.addr);
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}
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}
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if ((bus.w.ready)&&(!m_writedata.full())) {
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if ((bus.w.ready)&&(!m_writedata.full())) {
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m_writefifo.push(bus.aw.strb, bus.aw.data[0], bus.aw.data[1],
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m_writefifo.push(bus.aw.strb, bus.aw.data[0], bus.aw.data[1],
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bus.aw.data[2], bus.aw.data[3]);
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bus.aw.data[2], bus.aw.data[3]);
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if (m_respfifo[m_now].valid) {
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if (m_respfifo[m_now].valid) {
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if (m_respfifo[m_now].read) {
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if (m_respfifo[m_now].read) {
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if ((!bus.r.valid)||(bus.r.ready)) {
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if ((!bus.r.valid)||(bus.r.ready)) {
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bus.r.data[0] = m_respfifo[m_now].data[0];
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bus.r.data[0] = m_respfifo[m_now].data[0];
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bus.r.data[1] = m_respfifo[m_now].data[1];
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bus.r.data[1] = m_respfifo[m_now].data[1];
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bus.r.data[2] = m_respfifo[m_now].data[2];
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bus.r.data[2] = m_respfifo[m_now].data[2];
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bus.r.data[3] = m_respfifo[m_now].data[3];
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bus.r.data[3] = m_respfifo[m_now].data[3];
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bus.r.valid = true;
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bus.r.valid = true;
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m_now++;
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m_now++;
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}
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}
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} else if ((!bus.b.valid)||(bus.b.ready)) {
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} else if ((!bus.b.valid)||(bus.b.ready)) {
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bus.b.resp = m_respfifo[m_now].resp;
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bus.b.resp = m_respfifo[m_now].resp;
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bus.b.id = m_respfifo[m_now].id;
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bus.b.id = m_respfifo[m_now].id;
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bus.b.valid = true;
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bus.b.valid = true;
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m_now++;
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m_now++;
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}
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}
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}
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}
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}
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}
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