////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbm2axisp.v
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// Filename: wbm2axisp.v
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//
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//
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// Project: Pipelined Wishbone to AXI converter
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// Project: Pipelined Wishbone to AXI converter
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//
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//
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// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as
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// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as
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// one per clock. The AXI bus allows transactions at a speed of
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// one per clock. The AXI bus allows transactions at a speed of
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// one read and one write transaction per clock. These capabilities work
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// one read and one write transaction per clock. These capabilities work
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// by allowing requests to take place prior to responses, such that the
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// by allowing requests to take place prior to responses, such that the
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// requests might go out at once per clock and take several clocks, and
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// requests might go out at once per clock and take several clocks, and
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// the responses may start coming back several clocks later. In other
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// the responses may start coming back several clocks later. In other
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// words, both protocols allow multiple transactions to be "in flight" at
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// words, both protocols allow multiple transactions to be "in flight" at
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// the same time. Current wishbone to AXI converters, however, handle only
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// the same time. Current wishbone to AXI converters, however, handle only
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// one transaction at a time: initiating the transaction, and then waiting
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// one transaction at a time: initiating the transaction, and then waiting
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// for the transaction to complete before initiating the next.
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// for the transaction to complete before initiating the next.
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//
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//
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// The purpose of this core is to maintain the speed of both busses, while
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// The purpose of this core is to maintain the speed of both busses, while
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// transiting from the Wishbone (as master) to the AXI bus (as slave) and
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// transiting from the Wishbone (as master) to the AXI bus (as slave) and
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// back again.
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// back again.
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//
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//
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// Since the AXI bus allows transactions to be reordered, whereas the
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// Since the AXI bus allows transactions to be reordered, whereas the
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// wishbone does not, this core can be configured to reorder return
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// wishbone does not, this core can be configured to reorder return
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// transactions as well.
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// transactions as well.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbm2axisp #(
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module wbm2axisp #(
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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// This is an int between 1-16
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// This is an int between 1-16
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter AW = 28, // Wishbone address width
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parameter AW = 28, // Wishbone address width
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parameter DW = 32, // Wishbone data width
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parameter DW = 128, // Wishbone data width
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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) (
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) (
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input i_clk, // System clock
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input i_clk, // System clock
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input i_reset,// Wishbone reset signal
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input i_reset,// Wishbone reset signal
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|
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// AXI write address channel signals
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// AXI write address channel signals
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input i_axi_wready, // Slave is ready to accept
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input i_axi_wready, // Slave is ready to accept
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_wid, // Write ID
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_wid, // Write ID
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output reg [AW-1:0] o_axi_waddr, // Write address
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output reg [AW-1:0] o_axi_waddr, // Write address
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output wire [7:0] o_axi_wlen, // Write Burst Length
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output wire [7:0] o_axi_wlen, // Write Burst Length
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output wire [2:0] o_axi_wsize, // Write Burst size
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output wire [2:0] o_axi_wsize, // Write Burst size
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output wire [1:0] o_axi_wburst, // Write Burst type
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output wire [1:0] o_axi_wburst, // Write Burst type
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output wire [1:0] o_axi_wlock, // Write lock type
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output wire [1:0] o_axi_wlock, // Write lock type
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output wire [3:0] o_axi_wcache, // Write Cache type
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output wire [3:0] o_axi_wcache, // Write Cache type
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output wire [2:0] o_axi_wprot, // Write Protection type
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output wire [2:0] o_axi_wprot, // Write Protection type
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output reg o_axi_wvalid, // Write address valid
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output reg o_axi_wvalid, // Write address valid
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|
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// AXI write data channel signals
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// AXI write data channel signals
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input i_axi_wd_wready, // Write data ready
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input i_axi_wd_wready, // Write data ready
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
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output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data
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output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data
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output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes
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output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes
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output wire o_axi_wd_last, // Last write transaction
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output wire o_axi_wd_last, // Last write transaction
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output reg o_axi_wd_valid, // Write valid
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output reg o_axi_wd_valid, // Write valid
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|
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// AXI write response channel signals
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// AXI write response channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID
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input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID
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input [1:0] i_axi_wd_bresp, // Write response
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input [1:0] i_axi_wd_bresp, // Write response
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input i_axi_wd_bvalid, // Write reponse valid
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input i_axi_wd_bvalid, // Write reponse valid
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output wire o_axi_wd_bready, // Response ready
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output wire o_axi_wd_bready, // Response ready
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|
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// AXI read address channel signals
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// AXI read address channel signals
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input i_axi_rready, // Read address ready
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input i_axi_rready, // Read address ready
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Read ID
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Read ID
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output wire [AW-1:0] o_axi_raddr, // Read address
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output wire [AW-1:0] o_axi_raddr, // Read address
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output wire [7:0] o_axi_rlen, // Read Burst Length
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output wire [7:0] o_axi_rlen, // Read Burst Length
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output wire [2:0] o_axi_rsize, // Read Burst size
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output wire [2:0] o_axi_rsize, // Read Burst size
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output wire [1:0] o_axi_rburst, // Read Burst type
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output wire [1:0] o_axi_rburst, // Read Burst type
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output wire [1:0] o_axi_rlock, // Read lock type
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output wire [1:0] o_axi_rlock, // Read lock type
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output wire [3:0] o_axi_rcache, // Read Cache type
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output wire [3:0] o_axi_rcache, // Read Cache type
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output wire [2:0] o_axi_rprot, // Read Protection type
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output wire [2:0] o_axi_rprot, // Read Protection type
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output reg o_axi_rvalid, // Read address valid
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output reg o_axi_rvalid, // Read address valid
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|
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// AXI read data channel signals
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// AXI read data channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
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input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
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input [1:0] i_axi_rd_rresp, // Read response
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input [1:0] i_axi_rd_rresp, // Read response
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input i_axi_rd_rvalid, // Read reponse valid
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input i_axi_rd_rvalid, // Read reponse valid
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input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data
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input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data
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input i_axi_rd_last, // Read last
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input i_axi_rd_last, // Read last
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output wire o_axi_rd_rready, // Read Response ready
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output wire o_axi_rd_rready, // Read Response ready
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|
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// We'll share the clock and the reset
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// We'll share the clock and the reset
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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input i_wb_we,
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input i_wb_we,
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input [AW-1:0] i_wb_addr,
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input [AW-1:0] i_wb_addr,
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input [DW-1:0] i_wb_data,
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input [DW-1:0] i_wb_data,
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input [3:0] i_wb_sel,
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input [(DW/8-1):0] i_wb_sel,
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output reg o_wb_ack,
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output reg o_wb_ack,
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output wire o_wb_stall,
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output wire o_wb_stall,
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output reg [DW-1:0] o_wb_data,
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output reg [DW-1:0] o_wb_data,
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output reg o_wb_err
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output reg o_wb_err
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);
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);
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//*****************************************************************************
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//*****************************************************************************
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// Parameter declarations
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// Parameter declarations
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//*****************************************************************************
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//*****************************************************************************
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localparam CTL_SIG_WIDTH = 3; // Control signal width
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localparam CTL_SIG_WIDTH = 3; // Control signal width
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localparam RD_STS_WIDTH = 16; // Read status signal width
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localparam RD_STS_WIDTH = 16; // Read status signal width
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localparam WR_STS_WIDTH = 16; // Write status signal width
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localparam WR_STS_WIDTH = 16; // Write status signal width
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|
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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// Internal register and wire declarations
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//*****************************************************************************
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//*****************************************************************************
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wire cmd_en;
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wire cmd_en;
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wire [2:0] cmd;
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wire [2:0] cmd;
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wire [7:0] blen;
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wire [7:0] blen;
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wire [31:0] addr;
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wire [31:0] addr;
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wire [CTL_SIG_WIDTH-1:0] ctl;
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wire [CTL_SIG_WIDTH-1:0] ctl;
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wire cmd_ack;
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wire cmd_ack;
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// User interface write ports
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// User interface write ports
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wire wrdata_vld;
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wire wrdata_vld;
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wire [C_AXI_DATA_WIDTH-1:0] wrdata;
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wire [C_AXI_DATA_WIDTH-1:0] wrdata;
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wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
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wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
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wire wrdata_cmptd;
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wire wrdata_cmptd;
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wire wrdata_rdy;
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wire wrdata_rdy;
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wire wrdata_sts_vld;
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wire wrdata_sts_vld;
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wire [WR_STS_WIDTH-1:0] wrdata_sts;
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wire [WR_STS_WIDTH-1:0] wrdata_sts;
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// User interface read ports
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// User interface read ports
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wire rddata_rdy;
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wire rddata_rdy;
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wire rddata_vld;
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wire rddata_vld;
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wire [C_AXI_DATA_WIDTH-1:0] rddata;
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wire [C_AXI_DATA_WIDTH-1:0] rddata;
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wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
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wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
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wire rddata_cmptd;
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wire rddata_cmptd;
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wire [RD_STS_WIDTH-1:0] rddata_sts;
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wire [RD_STS_WIDTH-1:0] rddata_sts;
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reg cmptd_one_wr;
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reg cmptd_one_wr;
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reg cmptd_one_rd;
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reg cmptd_one_rd;
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// Things we're not changing ...
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// Things we're not changing ...
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assign o_axi_wlen = 8'h0; // Burst length is one
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assign o_axi_wlen = 8'h0; // Burst length is one
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assign o_axi_wsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_wsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_wburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_wburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_rburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_rburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_wlock = 2'b00; // Normal signaling
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assign o_axi_wlock = 2'b00; // Normal signaling
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assign o_axi_rlock = 2'b00; // Normal signaling
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assign o_axi_rlock = 2'b00; // Normal signaling
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assign o_axi_wcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_wcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_rcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_rcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_wprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_wprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_rprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_rprot = 3'h010; // Unpriviledged, unsecure, data access
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// Command logic
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// Command logic
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assign o_wb_stall = (i_wb_we)&&(~i_axi_wready)
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assign o_wb_stall = (i_wb_we)&&(~i_axi_wready)
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||(~i_wb_we)&&(!i_axi_rready);
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||(~i_wb_we)&&(!i_axi_rready);
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// Write address logic
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// Write address logic
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
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||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
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o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
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|
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reg [5:0] transaction_id;
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reg [5:0] transaction_id;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!i_wb_cyc)
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if (!i_wb_cyc)
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transaction_id <= 6'h00;
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transaction_id <= 6'h00;
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else if ((i_wb_stb)&&(~o_wb_stall))
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else if ((i_wb_stb)&&(~o_wb_stall))
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transaction_id <= transaction_id + 6'h01;
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transaction_id <= transaction_id + 6'h01;
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assign o_axi_wid = transaction_id;
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assign o_axi_wid = transaction_id;
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|
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// Read address logic
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// Read address logic
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assign o_axi_rid = transaction_id;
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assign o_axi_rid = transaction_id;
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assign o_axi_raddr = o_axi_waddr;
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assign o_axi_raddr = o_axi_waddr;
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assign o_axi_rlen = o_axi_wlen;
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assign o_axi_rlen = o_axi_wlen;
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assign o_axi_rsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_rsize = 3'b101; // maximum bytes per burst is 32
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
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||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
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|
|
|
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// Write data logic
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// Write data logic
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assign o_axi_wd_wid = transaction_id;
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assign o_axi_wd_wid = transaction_id;
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generate
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if (DW == 32)
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|
begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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case(i_wb_addr[1:0])
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case(i_wb_addr[1:0])
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2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
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2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
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2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
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2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
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endcase
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endcase
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|
end else if (DW == 128)
|
|
begin
|
|
always @(posedge i_clk)
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if (!o_wb_stall)
|
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o_axi_wd_data <= i_wb_data;
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_axi_wd_strb <= i_wb_sel;
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end endgenerate
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|
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assign o_axi_wd_last = 1'b1;
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assign o_axi_wd_last = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
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o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
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||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
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||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
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|
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// Read data channel / response logic
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// Read data channel / response logic
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assign o_axi_rd_rready = 1'b1;
|
assign o_axi_rd_rready = 1'b1;
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assign o_axi_wd_bready = 1'b1;
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assign o_axi_wd_bready = 1'b1;
|
|
|
wire w_fifo_full;
|
wire w_fifo_full;
|
generate
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generate
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if (STRICT_ORDER == 0)
|
if (STRICT_ORDER == 0)
|
begin
|
begin
|
// Reorder FIFO
|
// Reorder FIFO
|
//
|
//
|
localparam LGFIFOLN = C_AXI_ID_WIDTH;
|
localparam LGFIFOLN = C_AXI_ID_WIDTH;
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localparam FIFOLN = (1<<LGFIFOLN);
|
localparam FIFOLN = (1<<LGFIFOLN);
|
// FIFO reorder buffer
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// FIFO reorder buffer
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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if (DW == 32)
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begin
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] low_addr;
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reg [1:0] low_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_stb)&&(!o_wb_stall))
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if ((i_wb_stb)&&(!o_wb_stall))
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low_addr <= i_wb_addr[1:0];
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low_addr <= i_wb_addr[1:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_axi_rvalid)&&(i_axi_rready))
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if ((o_axi_rvalid)&&(i_axi_rready))
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reorder_fifo_addr[o_axi_rid] <= low_addr;
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reorder_fifo_addr[o_axi_rid] <= low_addr;
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always @(posedge i_clk)
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case(reorder_fifo_addr[1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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o_wb_data <= reorder_fifo_data[fifo_tail];
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end
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wire [(LGFIFOLN-1):0] fifo_head;
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wire [(LGFIFOLN-1):0] fifo_head;
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assign fifo_head = transaction_id;
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assign fifo_head = transaction_id;
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// Let's do some math to figure out where the FIFO head will
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// Let's do some math to figure out where the FIFO head will
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// point to next, but let's also insist that it be LGFIFOLN
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// point to next, but let's also insist that it be LGFIFOLN
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// bits in size as well. This'll be part of the fifo_full
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// bits in size as well. This'll be part of the fifo_full
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// calculation below.
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// calculation below.
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wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
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wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
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assign n_fifo_head = fifo_head+1'b1;
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assign n_fifo_head = fifo_head+1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
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reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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begin
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begin
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reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
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reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
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reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];
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reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];
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end
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end
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if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
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if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
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begin
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begin
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reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
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reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
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reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
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reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
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end
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end
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case(reorder_fifo_addr[1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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if (reorder_fifo_valid[fifo_tail])
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if (reorder_fifo_valid[fifo_tail])
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begin
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begin
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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o_wb_err <= reorder_fifo_err[fifo_tail];
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o_wb_err <= reorder_fifo_err[fifo_tail];
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fifo_tail <= fifo_tail + 6'h1;
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fifo_tail <= fifo_tail + 6'h1;
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reorder_fifo_valid[fifo_tail] <= 1'b0;
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reorder_fifo_valid[fifo_tail] <= 1'b0;
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reorder_fifo_err[fifo_tail] <= 1'b0;
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reorder_fifo_err[fifo_tail] <= 1'b0;
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end else begin
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end else begin
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_err <= 1'b0;
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o_wb_err <= 1'b0;
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end
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end
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if (!i_wb_cyc)
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if (!i_wb_cyc)
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begin
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begin
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reorder_fifo_valid <= {(FIFOLN){1'b0}};
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reorder_fifo_valid <= {(FIFOLN){1'b0}};
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reorder_fifo_err <= {(FIFOLN){1'b0}};
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reorder_fifo_err <= {(FIFOLN){1'b0}};
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fifo_tail <= 6'h0;
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fifo_tail <= 6'h0;
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o_wb_err <= 1'b0;
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o_wb_err <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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end
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end
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end
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end
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reg r_fifo_full;
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reg r_fifo_full;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (!i_wb_cyc)
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if (!i_wb_cyc)
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r_fifo_full <= 1'b0;
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r_fifo_full <= 1'b0;
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else if ((i_wb_stb)&&(~o_wb_stall)
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else if ((i_wb_stb)&&(~o_wb_stall)
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&&(reorder_fifo_valid[fifo_tail]))
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&&(reorder_fifo_valid[fifo_tail]))
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r_fifo_full <= (fifo_tail==n_fifo_head);
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r_fifo_full <= (fifo_tail==n_fifo_head);
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else if ((i_wb_stb)&&(~o_wb_stall))
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else if ((i_wb_stb)&&(~o_wb_stall))
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r_fifo_full <= (fifo_tail==nn_fifo_head);
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r_fifo_full <= (fifo_tail==nn_fifo_head);
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else if (reorder_fifo_valid[fifo_tail])
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else if (reorder_fifo_valid[fifo_tail])
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r_fifo_full <= 1'b0;
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r_fifo_full <= 1'b0;
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else
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else
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r_fifo_full <= (fifo_tail==n_fifo_head);
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r_fifo_full <= (fifo_tail==n_fifo_head);
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end
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end
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assign w_fifo_full = r_fifo_full;
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assign w_fifo_full = r_fifo_full;
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end else begin
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end else begin
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assign w_fifo_full = 1'b0;
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assign w_fifo_full = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_data <= i_axi_rd_data;
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o_wb_data <= i_axi_rd_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
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||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
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o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
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||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))
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||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))
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||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
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||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
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end endgenerate
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end endgenerate
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// Now, the difficult signal ... the stall signal
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// Now, the difficult signal ... the stall signal
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// Let's build for a single cycle input ... and only stall if something
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// Let's build for a single cycle input ... and only stall if something
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// outgoing is valid and nothing is ready.
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// outgoing is valid and nothing is ready.
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assign o_wb_stall = (i_wb_cyc)&&(
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assign o_wb_stall = (i_wb_cyc)&&(
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(w_fifo_full)
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(w_fifo_full)
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||((o_axi_wvalid)&&(!i_axi_wready))
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||((o_axi_wvalid)&&(!i_axi_wready))
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||((o_axi_wd_valid)&&(!i_axi_wd_wready))
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||((o_axi_wd_valid)&&(!i_axi_wd_wready))
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||((o_axi_rvalid)&&(!i_axi_rready)));
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||((o_axi_rvalid)&&(!i_axi_rready)));
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endmodule
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endmodule
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