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;; This sourcecode is released under BSD license.
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;; This sourcecode is released under BSD license.
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;; Please see http://www.opensource.org/licenses/bsd-license.php for details!
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;; Please see http://www.opensource.org/licenses/bsd-license.php for details!
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;;
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;;
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;; Copyright (c) 2010, Stefan Fischer
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;; Copyright (c) 2010, Stefan Fischer
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;; All rights reserved.
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;; All rights reserved.
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;;
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are met:
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;; modification, are permitted provided that the following conditions are met:
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;;
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;;
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;; * Redistributions of source code must retain the above copyright notice,
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;; * Redistributions of source code must retain the above copyright notice,
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;; this list of conditions and the following disclaimer.
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;; this list of conditions and the following disclaimer.
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;; * Redistributions in binary form must reproduce the above copyright notice,
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;; * Redistributions in binary form must reproduce the above copyright notice,
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;; this list of conditions and the following disclaimer in the documentation
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;; this list of conditions and the following disclaimer in the documentation
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;; and/or other materials provided with the distribution.
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;; and/or other materials provided with the distribution.
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;; * Neither the name of the author nor the names of his contributors may be
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;; used to endorse or promote products derived from this software without
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;; specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;; POSSIBILITY OF SUCH DAMAGE.
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;; POSSIBILITY OF SUCH DAMAGE.
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;;
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;;
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;; filename: pbwbgpio.psm
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;; filename: pbwbgpio.psm
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;; description: gpio example, demonstrating access to wishbone peripherals
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;; description: gpio example, demonstrating access to wishbone peripherals
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;; todo4user: modify main program and gpio_init code as needed
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;; todo4user: modify main program and gpio_init code as needed
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;; version: 0.0.0
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;; version: 0.0.0
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;; changelog: - 0.0.0, initial release
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;; changelog: - 0.0.0, initial release
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;; - ...
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;; - ...
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; wishbone variables
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; wishbone variables
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NAMEREG sF , wb_addr
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NAMEREG sF , wb_addr
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NAMEREG sE , wb_data ; also used as tmp-reg for status polling
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NAMEREG sE , wb_data ; also used as tmp-reg for status polling
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ADDRESS 000
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ADDRESS 000
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; main entry point
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; main entry point
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;;;;;;;;;;;;;;;;;;
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DISABLE INTERRUPT
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DISABLE INTERRUPT
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CALL gpio_init
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CALL gpio_init
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; mirroring upper nibble gpio inputs
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; mirroring upper nibble gpio inputs
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; to lower nibble gpio outputs
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; to lower nibble gpio outputs
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LOAD wb_addr , GPIO_IO_ADDR
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LOAD wb_addr , GPIO_IO_ADDR
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mainloop:
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mainloop:
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CALL wb_rd
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CALL wb_rd
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NAMEREG s0 , i
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NAMEREG s0 , i
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LOAD i , 04
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LOAD i , 04
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for_i_in_4_downto_1_loop: ; bitshifting (wb_data>>4)
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for_i_in_4_downto_1_loop: ; bitshifting (wb_data>>4)
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SR0 wb_data
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SR0 wb_data
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SUB i , 01
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SUB i , 01
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JUMP NZ , for_i_in_4_downto_1_loop
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JUMP NZ , for_i_in_4_downto_1_loop
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CALL wb_wr
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CALL wb_wr
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JUMP mainloop
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JUMP mainloop
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; wbs_gpio module subroutines and settings
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; wbs_gpio module subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; usage:
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; usage:
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; 1. set bitmasks for output enable and output level in gpio_init subroutine
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; 1. set bitmasks for output enable and output level in gpio_init subroutine
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; 2. call gpio_init subroutine to configure wbs_gpio module for operation
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; 2. call gpio_init subroutine to configure wbs_gpio module for operation
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; 3. use wb_wr and wb_rd subroutines to access i/o register
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; 3. use wb_wr and wb_rd subroutines to access i/o register
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; gpio start-up configuration, i. e. i/o direction and default output value
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; gpio start-up configuration, i. e. i/o direction and default output value
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gpio_init:
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gpio_init:
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; setting all outputs low
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; setting all outputs low
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LOAD wb_addr , GPIO_IO_ADDR
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LOAD wb_addr , GPIO_IO_ADDR
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LOAD wb_data , 00
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LOAD wb_data , 00
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CALL wb_wr
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CALL wb_wr
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; configuring lower gpio nibble as output
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; configuring lower gpio nibble as output
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LOAD wb_addr , GPIO_OE_ADDR
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LOAD wb_addr , GPIO_OE_ADDR
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LOAD wb_data , 0F
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LOAD wb_data , 0F
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CALL wb_wr
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CALL wb_wr
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RETURN
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RETURN
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; register addressing
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; register addressing
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CONSTANT GPIO_IO_ADDR , 00 ; input/output register
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CONSTANT GPIO_IO_ADDR , 00 ; input/output register
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CONSTANT GPIO_OE_ADDR , 01 ; output-enable register
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CONSTANT GPIO_OE_ADDR , 01 ; output-enable register
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; wbm_picoblaze module subroutines and settings
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; wbm_picoblaze module subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
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; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
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; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
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; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
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; is a supporting subroutine, which should not be called directly
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; is a supporting subroutine, which should not be called directly
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;
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;
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; transfer principle wishbone write:
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; transfer principle wishbone write:
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; 1. OUTPUT cycle to set up wishbone address, data and control signals from
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; 1. OUTPUT cycle to set up wishbone address, data and control signals from
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; PORT_ID, OUT_PORT and WRITE_STROBE
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; PORT_ID, OUT_PORT and WRITE_STROBE
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; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
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; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
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; => at least one OUTPUT and one INPUT cycle for a write
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; => at least one OUTPUT and one INPUT cycle for a write
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;
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;
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; transfer principle wishbone read:
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; transfer principle wishbone read:
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; 1. INPUT cycle to set up wishbone address and control signals from PORT_ID
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; 1. INPUT cycle to set up wishbone address and control signals from PORT_ID
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; and READ_STROBE
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; and READ_STROBE
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; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
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; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
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; 3. the very next INPUT cycle after acknowledgement contains valid wishbone
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; 3. the very next INPUT cycle after acknowledgement contains valid wishbone
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; data from IN_PORT
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; data from IN_PORT
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; => at least three INPUT cycles for a read
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; => at least three INPUT cycles for a read
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;
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;
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; calling examples:
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; calling examples:
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;
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;
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; wishbone write code =>
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; wishbone write code =>
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;
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;
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; LOAD wb_addr , ; setting up address
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; LOAD wb_addr , ; setting up address
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; LOAD wb_data , ; setting up data
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; LOAD wb_data , ; setting up data
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; CALL wb_wr ; starting wishbone write cycle
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; CALL wb_wr ; starting wishbone write cycle
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; ; wishbone cycle finished
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; ; wishbone cycle finished
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;
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;
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; wishbone read code =>
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; wishbone read code =>
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;
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;
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; LOAD wb_addr , ; setting up address
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; LOAD wb_addr , ; setting up address
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; CALL wb_rd ; starting wishbone read cycle
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; CALL wb_rd ; starting wishbone read cycle
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; LOAD , wb_data ; wb_data is updated now
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; LOAD , wb_data ; wb_data is updated now
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; ; wishbone cycle finished
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; ; wishbone cycle finished
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; wishbone write access
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; wishbone write access
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wb_wr:
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wb_wr:
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OUTPUT wb_data , (wb_addr)
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OUTPUT wb_data , (wb_addr)
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CALL wb_wait_on_ack
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CALL wb_wait_on_ack
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RETURN
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RETURN
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; wishbone read access
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; wishbone read access
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wb_rd:
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wb_rd:
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CALL wb_wait_on_ack
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CALL wb_wait_on_ack
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INPUT wb_data , (wb_addr)
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INPUT wb_data , (wb_addr)
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RETURN
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RETURN
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; waiting on wishbone cycle to complete
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; waiting on wishbone cycle to complete
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wb_wait_on_ack:
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wb_wait_on_ack:
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INPUT wb_data , (wb_addr)
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INPUT wb_data , (wb_addr)
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TEST wb_data , WB_ACK_FLAG
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TEST wb_data , WB_ACK_FLAG
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JUMP Z , wb_wait_on_ack
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JUMP Z , wb_wait_on_ack
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RETURN
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RETURN
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CONSTANT WB_ACK_FLAG , 01
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CONSTANT WB_ACK_FLAG , 01
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; interrupt subroutines and settings
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; interrupt subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; IMPORTANT NOTICE!
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; IMPORTANT NOTICE!
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; be carefull, if using interrupts. wishbone cycles must be atomar, as any
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; be carefull, if using interrupts. wishbone cycles must be atomar, as any
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; other processor local bus cycles are normally be. interrupting wishbone
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; other processor local bus cycles are normally be. interrupting wishbone
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; access may cause a crash of external wishbone master fsm, especially, if
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; access may cause a crash of external wishbone master fsm, especially, if
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; program flow through isr leads to another wishbone cycle!
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; program flow through isr leads to another wishbone cycle!
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; interrupt handling template, if needed
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; interrupt handling template, if needed
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isr:
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isr:
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RETURNI DISABLE
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RETURNI DISABLE
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ADDRESS 3FF
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ADDRESS 3FF
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JUMP isr
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JUMP isr
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