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;; This sourcecode is released under BSD license.
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;; This sourcecode is released under BSD license.
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;; Please see http://www.opensource.org/licenses/bsd-license.php for details!
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;; Please see http://www.opensource.org/licenses/bsd-license.php for details!
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;;
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;; Copyright (c) 2010, Stefan Fischer
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;; Copyright (c) 2010, Stefan Fischer
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;; All rights reserved.
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;; All rights reserved.
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;;
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are met:
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;; modification, are permitted provided that the following conditions are met:
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;;
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;;
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;; * Redistributions of source code must retain the above copyright notice,
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;; * Redistributions of source code must retain the above copyright notice,
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;; this list of conditions and the following disclaimer.
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;; this list of conditions and the following disclaimer.
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;; * Redistributions in binary form must reproduce the above copyright notice,
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;; * Redistributions in binary form must reproduce the above copyright notice,
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;; this list of conditions and the following disclaimer in the documentation
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;; this list of conditions and the following disclaimer in the documentation
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;; and/or other materials provided with the distribution.
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;; and/or other materials provided with the distribution.
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;; * Neither the name of the author nor the names of his contributors may be
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;; used to endorse or promote products derived from this software without
|
|
;; specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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;; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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;; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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;; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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;; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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;; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;; POSSIBILITY OF SUCH DAMAGE.
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;; POSSIBILITY OF SUCH DAMAGE.
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;;
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; filename: pbwbuart.psm
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;; filename: pbwbuart.psm
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;; description: uart example, demonstrating access to wishbone peripherals
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;; description: uart example, demonstrating access to wishbone peripherals
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;; todo4user: modify main program and uart code as needed, i. e. non-blocking
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;; todo4user: modify main program and uart code as needed, i. e. non-blocking
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;; read and write transactions or data burst transfers
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;; read and write transactions or data burst transfers
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;; version: 0.0.0
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;; version: 0.0.0
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;; changelog: - 0.0.0, initial release
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;; changelog: - 0.0.0, initial release
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;; - ...
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;; - ...
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; wishbone variables
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; wishbone variables
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NAMEREG sF , wb_addr
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NAMEREG sF , wb_addr
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NAMEREG sE , wb_data ; also used as tmp-reg for status polling
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NAMEREG sE , wb_data ; also used as tmp-reg for status polling
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; uart variables
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; uart variables
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NAMEREG sD , uart_data
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NAMEREG sD , uart_data
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ADDRESS 000
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ADDRESS 000
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; main entry point
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; main entry point
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;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;
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DISABLE INTERRUPT
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DISABLE INTERRUPT
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CALL uart_init
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CALL uart_init
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; obligatory "Hello World!" message
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; obligatory "Hello World!" message
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; new line
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; new line
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LOAD uart_data , ASCII_CR_CHAR
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LOAD uart_data , ASCII_CR_CHAR
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CALL uart_wr_byte
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CALL uart_wr_byte
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LOAD uart_data , ASCII_LF_CHAR
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LOAD uart_data , ASCII_LF_CHAR
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CALL uart_wr_byte
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CALL uart_wr_byte
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; H
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; H
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LOAD uart_data , ASCII_H_UC
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LOAD uart_data , ASCII_H_UC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; e
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; e
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LOAD uart_data , ASCII_E_LC
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LOAD uart_data , ASCII_E_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; l
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; l
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LOAD uart_data , ASCII_L_LC
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LOAD uart_data , ASCII_L_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; l
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; l
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LOAD uart_data , ASCII_L_LC
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LOAD uart_data , ASCII_L_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; o
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; o
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LOAD uart_data , ASCII_O_LC
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LOAD uart_data , ASCII_O_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; space
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; space
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LOAD uart_data , ASCII_SP_CHAR
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LOAD uart_data , ASCII_SP_CHAR
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CALL uart_wr_byte
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CALL uart_wr_byte
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; W
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; W
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LOAD uart_data , ASCII_W_UC
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LOAD uart_data , ASCII_W_UC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; o
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; o
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LOAD uart_data , ASCII_O_LC
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LOAD uart_data , ASCII_O_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; r
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; r
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LOAD uart_data , ASCII_R_LC
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LOAD uart_data , ASCII_R_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; l
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; l
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LOAD uart_data , ASCII_L_LC
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LOAD uart_data , ASCII_L_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; d
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; d
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LOAD uart_data , ASCII_D_LC
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LOAD uart_data , ASCII_D_LC
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CALL uart_wr_byte
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CALL uart_wr_byte
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; !
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; !
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LOAD uart_data , ASCII_EXCLAMATION_MARK_SIGN
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LOAD uart_data , ASCII_EXCLAMATION_MARK_SIGN
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CALL uart_wr_byte
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CALL uart_wr_byte
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; new line
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; new line
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LOAD uart_data , ASCII_CR_CHAR
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LOAD uart_data , ASCII_CR_CHAR
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CALL uart_wr_byte
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CALL uart_wr_byte
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LOAD uart_data , ASCII_LF_CHAR
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LOAD uart_data , ASCII_LF_CHAR
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CALL uart_wr_byte
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CALL uart_wr_byte
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; simple loopback of uart data
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; simple loopback of uart data
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mainloop:
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mainloop:
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CALL uart_rd_byte
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CALL uart_rd_byte
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CALL uart_wr_byte
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CALL uart_wr_byte
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JUMP mainloop
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JUMP mainloop
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; wbs_uart module subroutines and settings
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; wbs_uart module subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; usage:
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; usage:
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; 1. set baud rate in uart_init subroutine
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; 1. set baud rate in uart_init subroutine
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; 2. call uart_init subroutine to configure wbs_uart module for operation
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; 2. call uart_init subroutine to configure wbs_uart module for operation
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; 3. use uart_wr_byte and uart_rd_byte subroutines to access uart transceiver,
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; 3. use uart_wr_byte and uart_rd_byte subroutines to access uart transceiver,
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; all accesses are blocking, subroutines do not return, if wbs_uart tx buffer
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; all accesses are blocking, subroutines do not return, if wbs_uart tx buffer
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; is full or rx buffer is empty
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; is full or rx buffer is empty
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; uart write code =>
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; uart write code =>
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; LOAD uart_data , ; setting up data
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; LOAD uart_data , ; setting up data
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; CALL uart_wr_byte ; writing data to uart module
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; CALL uart_wr_byte ; writing data to uart module
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;
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;
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; uart read code =>
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; uart read code =>
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; CALL uart_rd_byte ; reading data from uart module
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; CALL uart_rd_byte ; reading data from uart module
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; LOAD , uart_data ; uart_data is updated now
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; LOAD , uart_data ; uart_data is updated now
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;
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;
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; 4. uart_clr_buff subroutine can be used to discard wbs_uart rx buffer contents
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; 4. uart_clr_buff subroutine can be used to discard wbs_uart rx buffer contents
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; during software runtime
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; during software runtime
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; uart start-up configuration, i. e. baudrate
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; uart start-up configuration, i. e. baudrate
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uart_init:
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uart_init:
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; setting baud rate
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; setting baud rate
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LOAD wb_addr , UART_BAUD_LO_ADDR
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LOAD wb_addr , UART_BAUD_LO_ADDR
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LOAD wb_data , UART_BAUD_LO_115200_VALUE
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LOAD wb_data , UART_BAUD_LO_115200_VALUE
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CALL wb_wr
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CALL wb_wr
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LOAD wb_addr , UART_BAUD_HI_ADDR
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LOAD wb_addr , UART_BAUD_HI_ADDR
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LOAD wb_data , UART_BAUD_HI_115200_VALUE
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LOAD wb_data , UART_BAUD_HI_115200_VALUE
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CALL wb_wr
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CALL wb_wr
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; clear uart receive buffer, after power up and change of baud rate, there is
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; clear uart receive buffer, after power up and change of baud rate, there is
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; maybe invalid data in it
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; maybe invalid data in it
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CALL uart_clr_buff
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CALL uart_clr_buff
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RETURN
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RETURN
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; blocking write byte to uart
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; blocking write byte to uart
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uart_wr_byte:
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uart_wr_byte:
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LOAD wb_addr , UART_RXTX_ADDR
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LOAD wb_addr , UART_RXTX_ADDR
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LOAD wb_data , uart_data
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LOAD wb_data , uart_data
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CALL wb_wr
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CALL wb_wr
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RETURN
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RETURN
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; blocking read byte from uart
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; blocking read byte from uart
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uart_rd_byte:
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uart_rd_byte:
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LOAD wb_addr , UART_RXTX_ADDR
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LOAD wb_addr , UART_RXTX_ADDR
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CALL wb_rd
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CALL wb_rd
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LOAD uart_data , wb_data
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LOAD uart_data , wb_data
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RETURN
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RETURN
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; uart rx buffer clear
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; uart rx buffer clear
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uart_clr_buff:
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uart_clr_buff:
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; uart receive buffer software reset, checking status register for level and
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; uart receive buffer software reset, checking status register for level and
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; reading out all available data
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; reading out all available data
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LOAD wb_addr , UART_SR_ADDR ; setting status register address
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LOAD wb_addr , UART_SR_ADDR ; setting status register address
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CALL wb_rd
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CALL wb_rd
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; checking data present flag
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; checking data present flag
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TEST wb_data , UART_SR_RX_DP_FLAG
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TEST wb_data , UART_SR_RX_DP_FLAG
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; if flag is not set, returning immediately
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; if flag is not set, returning immediately
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RETURN Z
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RETURN Z
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; else reading out next byte and checking flag again
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; else reading out next byte and checking flag again
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CALL uart_rd_byte
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CALL uart_rd_byte
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JUMP uart_clr_buff
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JUMP uart_clr_buff
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; register and flag addressing
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; register and flag addressing
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CONSTANT UART_RXTX_ADDR , 00 ; receive/transmit data pipe
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CONSTANT UART_RXTX_ADDR , 00 ; receive/transmit data pipe
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CONSTANT UART_SR_ADDR , 01 ; status register
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CONSTANT UART_SR_ADDR , 01 ; status register
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CONSTANT UART_SR_RX_F_FLAG , 01 ; status rx full
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CONSTANT UART_SR_RX_F_FLAG , 01 ; status rx full
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CONSTANT UART_SR_RX_HF_FLAG , 02 ; status rx half full
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CONSTANT UART_SR_RX_HF_FLAG , 02 ; status rx half full
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CONSTANT UART_SR_RX_DP_FLAG , 04 ; status rx data present
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CONSTANT UART_SR_RX_DP_FLAG , 04 ; status rx data present
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CONSTANT UART_SR_TX_F_FLAG , 10 ; status tx full
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CONSTANT UART_SR_TX_F_FLAG , 10 ; status tx full
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CONSTANT UART_SR_TX_HF_FLAG , 20 ; status tx half full
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CONSTANT UART_SR_TX_HF_FLAG , 20 ; status tx half full
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CONSTANT UART_BAUD_LO_ADDR , 02 ; baud rate cfg. register / low byte
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CONSTANT UART_BAUD_LO_ADDR , 02 ; baud rate cfg. register / low byte
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CONSTANT UART_BAUD_HI_ADDR , 03 ; baud rate cfg. register / high byte
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CONSTANT UART_BAUD_HI_ADDR , 03 ; baud rate cfg. register / high byte
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; baud rate configuration:
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; baud rate configuration:
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; baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
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; baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
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; i. e. 9600 baud at 50 MHz system clock =>
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; i. e. 9600 baud at 50 MHz system clock =>
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; baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
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; baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
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; WARNING, baud rate error should not exceed 1.0 % for reliable operation!
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; WARNING, baud rate error should not exceed 1.0 % for reliable operation!
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; baud rate settings for 50.0E6 Hz system reference clock
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; baud rate settings for 50.0E6 Hz system reference clock
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; max. 3125000.0 baud
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; max. 3125000.0 baud
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; min. 48.0 baud (16 bit baud timer)
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; min. 48.0 baud (16 bit baud timer)
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CONSTANT UART_BAUD_LO_300_VALUE , B0 ; actual baud rate 299.99
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CONSTANT UART_BAUD_LO_300_VALUE , B0 ; actual baud rate 299.99
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CONSTANT UART_BAUD_HI_300_VALUE , 28 ; => baud rate error 0.003 %
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CONSTANT UART_BAUD_HI_300_VALUE , 28 ; => baud rate error 0.003 %
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CONSTANT UART_BAUD_LO_600_VALUE , 57 ; actual baud rate 600.04
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CONSTANT UART_BAUD_LO_600_VALUE , 57 ; actual baud rate 600.04
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CONSTANT UART_BAUD_HI_600_VALUE , 14 ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_HI_600_VALUE , 14 ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_LO_1200_VALUE , 2B ; actual baud rate 1200.08
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CONSTANT UART_BAUD_LO_1200_VALUE , 2B ; actual baud rate 1200.08
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CONSTANT UART_BAUD_HI_1200_VALUE , 0A ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_HI_1200_VALUE , 0A ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_LO_2400_VALUE , 15 ; actual baud rate 2400.15
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CONSTANT UART_BAUD_LO_2400_VALUE , 15 ; actual baud rate 2400.15
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CONSTANT UART_BAUD_HI_2400_VALUE , 05 ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_HI_2400_VALUE , 05 ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_LO_4800_VALUE , 8A ; actual baud rate 4800.31
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CONSTANT UART_BAUD_LO_4800_VALUE , 8A ; actual baud rate 4800.31
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CONSTANT UART_BAUD_HI_4800_VALUE , 02 ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_HI_4800_VALUE , 02 ; => baud rate error 0.006 %
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CONSTANT UART_BAUD_LO_9600_VALUE , 45 ; actual baud rate 9585.89
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CONSTANT UART_BAUD_LO_9600_VALUE , 45 ; actual baud rate 9585.89
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CONSTANT UART_BAUD_HI_9600_VALUE , 01 ; => baud rate error 0.147 %
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CONSTANT UART_BAUD_HI_9600_VALUE , 01 ; => baud rate error 0.147 %
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CONSTANT UART_BAUD_LO_19200_VALUE , A2 ; actual baud rate 19171.78
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CONSTANT UART_BAUD_LO_19200_VALUE , A2 ; actual baud rate 19171.78
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CONSTANT UART_BAUD_HI_19200_VALUE , 00 ; => baud rate error 0.147 %
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CONSTANT UART_BAUD_HI_19200_VALUE , 00 ; => baud rate error 0.147 %
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CONSTANT UART_BAUD_LO_38400_VALUE , 50 ; actual baud rate 38580.25
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CONSTANT UART_BAUD_LO_38400_VALUE , 50 ; actual baud rate 38580.25
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CONSTANT UART_BAUD_HI_38400_VALUE , 00 ; => baud rate error 0.467 %
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CONSTANT UART_BAUD_HI_38400_VALUE , 00 ; => baud rate error 0.467 %
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CONSTANT UART_BAUD_LO_57600_VALUE , 35 ; actual baud rate 57870.37
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CONSTANT UART_BAUD_LO_57600_VALUE , 35 ; actual baud rate 57870.37
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CONSTANT UART_BAUD_HI_57600_VALUE , 00 ; => baud rate error 0.467 %
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CONSTANT UART_BAUD_HI_57600_VALUE , 00 ; => baud rate error 0.467 %
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CONSTANT UART_BAUD_LO_115200_VALUE , 1A ; actual baud rate 115740.74
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CONSTANT UART_BAUD_LO_115200_VALUE , 1A ; actual baud rate 115740.74
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CONSTANT UART_BAUD_HI_115200_VALUE , 00 ; => baud rate error 0.467 %
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CONSTANT UART_BAUD_HI_115200_VALUE , 00 ; => baud rate error 0.467 %
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;CONSTANT UART_BAUD_LO_230400_VALUE , 0D ; actual baud rate 223214.29
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;CONSTANT UART_BAUD_LO_230400_VALUE , 0D ; actual baud rate 223214.29
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;CONSTANT UART_BAUD_HI_230400_VALUE , 00 ; => baud rate error 3.219 %
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;CONSTANT UART_BAUD_HI_230400_VALUE , 00 ; => baud rate error 3.219 %
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;CONSTANT UART_BAUD_LO_460800_VALUE , 06 ; actual baud rate 446428.57
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;CONSTANT UART_BAUD_LO_460800_VALUE , 06 ; actual baud rate 446428.57
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;CONSTANT UART_BAUD_HI_460800_VALUE , 00 ; => baud rate error 3.219 %
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;CONSTANT UART_BAUD_HI_460800_VALUE , 00 ; => baud rate error 3.219 %
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;CONSTANT UART_BAUD_LO_921600_VALUE , 02 ; actual baud rate 1041666.67
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;CONSTANT UART_BAUD_LO_921600_VALUE , 02 ; actual baud rate 1041666.67
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;CONSTANT UART_BAUD_HI_921600_VALUE , 00 ; => baud rate error 11.526 %
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;CONSTANT UART_BAUD_HI_921600_VALUE , 00 ; => baud rate error 11.526 %
|
|
|
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; wbm_picoblaze module subroutines and settings
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; wbm_picoblaze module subroutines and settings
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
|
; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
|
; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
|
; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
|
; is a supporting subroutine, which should not be called directly
|
; is a supporting subroutine, which should not be called directly
|
;
|
;
|
; transfer principle wishbone write:
|
; transfer principle wishbone write:
|
; 1. OUTPUT cycle to set up wishbone address, data and control signals from
|
; 1. OUTPUT cycle to set up wishbone address, data and control signals from
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; PORT_ID, OUT_PORT and WRITE_STROBE
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; PORT_ID, OUT_PORT and WRITE_STROBE
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; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
|
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
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; => at least one OUTPUT and one INPUT cycle for a write
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; => at least one OUTPUT and one INPUT cycle for a write
|
;
|
;
|
; transfer principle wishbone read:
|
; transfer principle wishbone read:
|
; 1. INPUT cycle to set up wishbone address and control signals from PORT_ID
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; 1. INPUT cycle to set up wishbone address and control signals from PORT_ID
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; and READ_STROBE
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; and READ_STROBE
|
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
|
; 2. INPUT cycle(s) to poll wishbone peripheral acknowledgement using IN_PORT
|
; 3. the very next INPUT cycle after acknowledgement contains valid wishbone
|
; 3. the very next INPUT cycle after acknowledgement contains valid wishbone
|
; data from IN_PORT
|
; data from IN_PORT
|
; => at least three INPUT cycles for a read
|
; => at least three INPUT cycles for a read
|
;
|
;
|
; calling examples:
|
; calling examples:
|
;
|
;
|
; wishbone write code =>
|
; wishbone write code =>
|
;
|
;
|
; LOAD wb_addr , ; setting up address
|
; LOAD wb_addr , ; setting up address
|
; LOAD wb_data , ; setting up data
|
; LOAD wb_data , ; setting up data
|
; CALL wb_wr ; starting wishbone write cycle
|
; CALL wb_wr ; starting wishbone write cycle
|
; ; wishbone cycle finished
|
; ; wishbone cycle finished
|
;
|
;
|
; wishbone read code =>
|
; wishbone read code =>
|
;
|
;
|
; LOAD wb_addr , ; setting up address
|
; LOAD wb_addr , ; setting up address
|
; CALL wb_rd ; starting wishbone read cycle
|
; CALL wb_rd ; starting wishbone read cycle
|
; LOAD , wb_data ; wb_data is updated now
|
; LOAD , wb_data ; wb_data is updated now
|
; ; wishbone cycle finished
|
; ; wishbone cycle finished
|
|
|
; wishbone write access
|
; wishbone write access
|
wb_wr:
|
wb_wr:
|
OUTPUT wb_data , (wb_addr)
|
OUTPUT wb_data , (wb_addr)
|
CALL wb_wait_on_ack
|
CALL wb_wait_on_ack
|
RETURN
|
RETURN
|
|
|
; wishbone read access
|
; wishbone read access
|
wb_rd:
|
wb_rd:
|
CALL wb_wait_on_ack
|
CALL wb_wait_on_ack
|
INPUT wb_data , (wb_addr)
|
INPUT wb_data , (wb_addr)
|
RETURN
|
RETURN
|
|
|
; waiting on wishbone cycle to complete
|
; waiting on wishbone cycle to complete
|
wb_wait_on_ack:
|
wb_wait_on_ack:
|
INPUT wb_data , (wb_addr)
|
INPUT wb_data , (wb_addr)
|
TEST wb_data , WB_ACK_FLAG
|
TEST wb_data , WB_ACK_FLAG
|
JUMP Z , wb_wait_on_ack
|
JUMP Z , wb_wait_on_ack
|
RETURN
|
RETURN
|
|
|
CONSTANT WB_ACK_FLAG , 01
|
CONSTANT WB_ACK_FLAG , 01
|
|
|
|
|
; interrupt subroutines and settings
|
; interrupt subroutines and settings
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
; IMPORTANT NOTICE!
|
; IMPORTANT NOTICE!
|
; be carefull, if using interrupts. wishbone cycles must be atomar, as any
|
; be carefull, if using interrupts. wishbone cycles must be atomar, as any
|
; other processor local bus cycles are normally be. interrupting wishbone
|
; other processor local bus cycles are normally be. interrupting wishbone
|
; access may cause a crash of external wishbone master fsm, especially, if
|
; access may cause a crash of external wishbone master fsm, especially, if
|
; program flow through isr leads to another wishbone cycle!
|
; program flow through isr leads to another wishbone cycle!
|
|
|
; interrupt handling template, if needed
|
; interrupt handling template, if needed
|
isr:
|
isr:
|
RETURNI DISABLE
|
RETURNI DISABLE
|
ADDRESS 3FF
|
ADDRESS 3FF
|
JUMP isr
|
JUMP isr
|
|
|
|
|
; ascii table
|
; ascii table
|
;;;;;;;;;;;;;
|
;;;;;;;;;;;;;
|
|
|
CONSTANT ASCII_NUL_CHAR , 00 ; NUL
|
CONSTANT ASCII_NUL_CHAR , 00 ; NUL
|
CONSTANT ASCII_SOH_CHAR , 01 ; SOH
|
CONSTANT ASCII_SOH_CHAR , 01 ; SOH
|
CONSTANT ASCII_STX_CHAR , 02 ; STX
|
CONSTANT ASCII_STX_CHAR , 02 ; STX
|
CONSTANT ASCII_ETX_CHAR , 03 ; ETX
|
CONSTANT ASCII_ETX_CHAR , 03 ; ETX
|
CONSTANT ASCII_EOT_CHAR , 04 ; EOT
|
CONSTANT ASCII_EOT_CHAR , 04 ; EOT
|
CONSTANT ASCII_ENQ_CHAR , 05 ; ENQ
|
CONSTANT ASCII_ENQ_CHAR , 05 ; ENQ
|
CONSTANT ASCII_ACK_CHAR , 06 ; ACK
|
CONSTANT ASCII_ACK_CHAR , 06 ; ACK
|
CONSTANT ASCII_BEL_CHAR , 07 ; BEL
|
CONSTANT ASCII_BEL_CHAR , 07 ; BEL
|
CONSTANT ASCII_BS_CHAR , 08 ; BS
|
CONSTANT ASCII_BS_CHAR , 08 ; BS
|
CONSTANT ASCII_TAB_CHAR , 09 ; TAB
|
CONSTANT ASCII_TAB_CHAR , 09 ; TAB
|
CONSTANT ASCII_LF_CHAR , 0A ; LF
|
CONSTANT ASCII_LF_CHAR , 0A ; LF
|
CONSTANT ASCII_VT_CHAR , 0B ; VT
|
CONSTANT ASCII_VT_CHAR , 0B ; VT
|
CONSTANT ASCII_FF_CHAR , 0C ; FF
|
CONSTANT ASCII_FF_CHAR , 0C ; FF
|
CONSTANT ASCII_CR_CHAR , 0D ; CR
|
CONSTANT ASCII_CR_CHAR , 0D ; CR
|
CONSTANT ASCII_SO_CHAR , 0E ; SO
|
CONSTANT ASCII_SO_CHAR , 0E ; SO
|
CONSTANT ASCII_SI_CHAR , 0F ; SI
|
CONSTANT ASCII_SI_CHAR , 0F ; SI
|
CONSTANT ASCII_DLE_CHAR , 10 ; DLE
|
CONSTANT ASCII_DLE_CHAR , 10 ; DLE
|
CONSTANT ASCII_DC1_CHAR , 11 ; DC1
|
CONSTANT ASCII_DC1_CHAR , 11 ; DC1
|
CONSTANT ASCII_DC2_CHAR , 12 ; DC2
|
CONSTANT ASCII_DC2_CHAR , 12 ; DC2
|
CONSTANT ASCII_DC3_CHAR , 13 ; DC3
|
CONSTANT ASCII_DC3_CHAR , 13 ; DC3
|
CONSTANT ASCII_DC4_CHAR , 14 ; DC4
|
CONSTANT ASCII_DC4_CHAR , 14 ; DC4
|
CONSTANT ASCII_NAK_CHAR , 15 ; NAK
|
CONSTANT ASCII_NAK_CHAR , 15 ; NAK
|
CONSTANT ASCII_SYN_CHAR , 16 ; SYN
|
CONSTANT ASCII_SYN_CHAR , 16 ; SYN
|
CONSTANT ASCII_ETB_CHAR , 17 ; ETB
|
CONSTANT ASCII_ETB_CHAR , 17 ; ETB
|
CONSTANT ASCII_CAN_CHAR , 18 ; CAN
|
CONSTANT ASCII_CAN_CHAR , 18 ; CAN
|
CONSTANT ASCII_EM_CHAR , 19 ; EM
|
CONSTANT ASCII_EM_CHAR , 19 ; EM
|
CONSTANT ASCII_SUB_CHAR , 1A ; SUB
|
CONSTANT ASCII_SUB_CHAR , 1A ; SUB
|
CONSTANT ASCII_ESC_CHAR , 1B ; ESC
|
CONSTANT ASCII_ESC_CHAR , 1B ; ESC
|
CONSTANT ASCII_FS_CHAR , 1C ; FS
|
CONSTANT ASCII_FS_CHAR , 1C ; FS
|
CONSTANT ASCII_GS_CHAR , 1D ; GS
|
CONSTANT ASCII_GS_CHAR , 1D ; GS
|
CONSTANT ASCII_RS_CHAR , 1E ; RS
|
CONSTANT ASCII_RS_CHAR , 1E ; RS
|
CONSTANT ASCII_US_CHAR , 1F ; US
|
CONSTANT ASCII_US_CHAR , 1F ; US
|
CONSTANT ASCII_SP_CHAR , 20 ; SP
|
CONSTANT ASCII_SP_CHAR , 20 ; SP
|
CONSTANT ASCII_EXCLAMATION_MARK_SIGN , 21 ; !
|
CONSTANT ASCII_EXCLAMATION_MARK_SIGN , 21 ; !
|
CONSTANT ASCII_DOUBLE_QUOTE_SIGN , 22 ; "
|
CONSTANT ASCII_DOUBLE_QUOTE_SIGN , 22 ; "
|
CONSTANT ASCII_NUMBER_SIGN , 23 ; #
|
CONSTANT ASCII_NUMBER_SIGN , 23 ; #
|
CONSTANT ASCII_DOLLAR_SIGN , 24 ; $
|
CONSTANT ASCII_DOLLAR_SIGN , 24 ; $
|
CONSTANT ASCII_PERCENT_SIGN , 25 ; %
|
CONSTANT ASCII_PERCENT_SIGN , 25 ; %
|
CONSTANT ASCII_AMPERSAND_SIGN , 26 ; &
|
CONSTANT ASCII_AMPERSAND_SIGN , 26 ; &
|
CONSTANT ASCII_SINGLE_QUOTE_SIGN , 27 ; '
|
CONSTANT ASCII_SINGLE_QUOTE_SIGN , 27 ; '
|
CONSTANT ASCII_OPN_PARENTHESIS_SIGN , 28 ; (
|
CONSTANT ASCII_OPN_PARENTHESIS_SIGN , 28 ; (
|
CONSTANT ASCII_CLS_PARENTHESIS_SIGN , 29 ; )
|
CONSTANT ASCII_CLS_PARENTHESIS_SIGN , 29 ; )
|
CONSTANT ASCII_ASTERISK_SIGN , 2A ; *
|
CONSTANT ASCII_ASTERISK_SIGN , 2A ; *
|
CONSTANT ASCII_PLUS_SIGN , 2B ; +
|
CONSTANT ASCII_PLUS_SIGN , 2B ; +
|
CONSTANT ASCII_COMMA_SIGN , 2C ; ,
|
CONSTANT ASCII_COMMA_SIGN , 2C ; ,
|
CONSTANT ASCII_MINUS_SIGN , 2D ; -
|
CONSTANT ASCII_MINUS_SIGN , 2D ; -
|
CONSTANT ASCII_DOT_SIGN , 2E ; .
|
CONSTANT ASCII_DOT_SIGN , 2E ; .
|
CONSTANT ASCII_SLASH_SIGN , 2F ; /
|
CONSTANT ASCII_SLASH_SIGN , 2F ; /
|
CONSTANT ASCII_0_DIGIT , 30 ; 0
|
CONSTANT ASCII_0_DIGIT , 30 ; 0
|
CONSTANT ASCII_1_DIGIT , 31 ; 1
|
CONSTANT ASCII_1_DIGIT , 31 ; 1
|
CONSTANT ASCII_2_DIGIT , 32 ; 2
|
CONSTANT ASCII_2_DIGIT , 32 ; 2
|
CONSTANT ASCII_3_DIGIT , 33 ; 3
|
CONSTANT ASCII_3_DIGIT , 33 ; 3
|
CONSTANT ASCII_4_DIGIT , 34 ; 4
|
CONSTANT ASCII_4_DIGIT , 34 ; 4
|
CONSTANT ASCII_5_DIGIT , 35 ; 5
|
CONSTANT ASCII_5_DIGIT , 35 ; 5
|
CONSTANT ASCII_6_DIGIT , 36 ; 6
|
CONSTANT ASCII_6_DIGIT , 36 ; 6
|
CONSTANT ASCII_7_DIGIT , 37 ; 7
|
CONSTANT ASCII_7_DIGIT , 37 ; 7
|
CONSTANT ASCII_8_DIGIT , 38 ; 8
|
CONSTANT ASCII_8_DIGIT , 38 ; 8
|
CONSTANT ASCII_9_DIGIT , 39 ; 9
|
CONSTANT ASCII_9_DIGIT , 39 ; 9
|
CONSTANT ASCII_COLON_SIGN , 3A ; :
|
CONSTANT ASCII_COLON_SIGN , 3A ; :
|
CONSTANT ASCII_SEMICOLON_SIGN , 3B ; ;
|
CONSTANT ASCII_SEMICOLON_SIGN , 3B ; ;
|
CONSTANT ASCII_LESS_THAN_SIGN , 3C ; <
|
CONSTANT ASCII_LESS_THAN_SIGN , 3C ; <
|
CONSTANT ASCII_EQUAL_SIGN , 3D ; =
|
CONSTANT ASCII_EQUAL_SIGN , 3D ; =
|
CONSTANT ASCII_GREATER_THAN_SIGN , 3E ; >
|
CONSTANT ASCII_GREATER_THAN_SIGN , 3E ; >
|
CONSTANT ASCII_QUESTION_MARK_SIGN , 3F ; ?
|
CONSTANT ASCII_QUESTION_MARK_SIGN , 3F ; ?
|
CONSTANT ASCII_AT_SIGN , 40 ; @
|
CONSTANT ASCII_AT_SIGN , 40 ; @
|
CONSTANT ASCII_A_UC , 41 ; A
|
CONSTANT ASCII_A_UC , 41 ; A
|
CONSTANT ASCII_B_UC , 42 ; B
|
CONSTANT ASCII_B_UC , 42 ; B
|
CONSTANT ASCII_C_UC , 43 ; C
|
CONSTANT ASCII_C_UC , 43 ; C
|
CONSTANT ASCII_D_UC , 44 ; D
|
CONSTANT ASCII_D_UC , 44 ; D
|
CONSTANT ASCII_E_UC , 45 ; E
|
CONSTANT ASCII_E_UC , 45 ; E
|
CONSTANT ASCII_F_UC , 46 ; F
|
CONSTANT ASCII_F_UC , 46 ; F
|
CONSTANT ASCII_G_UC , 47 ; G
|
CONSTANT ASCII_G_UC , 47 ; G
|
CONSTANT ASCII_H_UC , 48 ; H
|
CONSTANT ASCII_H_UC , 48 ; H
|
CONSTANT ASCII_I_UC , 49 ; I
|
CONSTANT ASCII_I_UC , 49 ; I
|
CONSTANT ASCII_J_UC , 4A ; J
|
CONSTANT ASCII_J_UC , 4A ; J
|
CONSTANT ASCII_K_UC , 4B ; K
|
CONSTANT ASCII_K_UC , 4B ; K
|
CONSTANT ASCII_L_UC , 4C ; L
|
CONSTANT ASCII_L_UC , 4C ; L
|
CONSTANT ASCII_M_UC , 4D ; M
|
CONSTANT ASCII_M_UC , 4D ; M
|
CONSTANT ASCII_N_UC , 4E ; N
|
CONSTANT ASCII_N_UC , 4E ; N
|
CONSTANT ASCII_O_UC , 4F ; O
|
CONSTANT ASCII_O_UC , 4F ; O
|
CONSTANT ASCII_P_UC , 50 ; P
|
CONSTANT ASCII_P_UC , 50 ; P
|
CONSTANT ASCII_Q_UC , 51 ; Q
|
CONSTANT ASCII_Q_UC , 51 ; Q
|
CONSTANT ASCII_R_UC , 52 ; R
|
CONSTANT ASCII_R_UC , 52 ; R
|
CONSTANT ASCII_S_UC , 53 ; S
|
CONSTANT ASCII_S_UC , 53 ; S
|
CONSTANT ASCII_T_UC , 54 ; T
|
CONSTANT ASCII_T_UC , 54 ; T
|
CONSTANT ASCII_U_UC , 55 ; U
|
CONSTANT ASCII_U_UC , 55 ; U
|
CONSTANT ASCII_V_UC , 56 ; V
|
CONSTANT ASCII_V_UC , 56 ; V
|
CONSTANT ASCII_W_UC , 57 ; W
|
CONSTANT ASCII_W_UC , 57 ; W
|
CONSTANT ASCII_X_UC , 58 ; X
|
CONSTANT ASCII_X_UC , 58 ; X
|
CONSTANT ASCII_Y_UC , 59 ; Y
|
CONSTANT ASCII_Y_UC , 59 ; Y
|
CONSTANT ASCII_Z_UC , 5A ; Z
|
CONSTANT ASCII_Z_UC , 5A ; Z
|
CONSTANT ASCII_OPN_BRACKET_SIGN , 5B ; [
|
CONSTANT ASCII_OPN_BRACKET_SIGN , 5B ; [
|
CONSTANT ASCII_BACKSLASH_SIGN , 5C ; \
|
CONSTANT ASCII_BACKSLASH_SIGN , 5C ; \
|
CONSTANT ASCII_CLS_BRACKET_SIGN , 5D ; ]
|
CONSTANT ASCII_CLS_BRACKET_SIGN , 5D ; ]
|
CONSTANT ASCII_CARET_SIGN , 5E ; ^
|
CONSTANT ASCII_CARET_SIGN , 5E ; ^
|
CONSTANT ASCII_UNDERSCORE_SIGN , 5F ; _
|
CONSTANT ASCII_UNDERSCORE_SIGN , 5F ; _
|
CONSTANT ASCII_ACCENT_SIGN , 60 ; `
|
CONSTANT ASCII_ACCENT_SIGN , 60 ; `
|
CONSTANT ASCII_A_LC , 61 ; a
|
CONSTANT ASCII_A_LC , 61 ; a
|
CONSTANT ASCII_B_LC , 62 ; b
|
CONSTANT ASCII_B_LC , 62 ; b
|
CONSTANT ASCII_C_LC , 63 ; c
|
CONSTANT ASCII_C_LC , 63 ; c
|
CONSTANT ASCII_D_LC , 64 ; d
|
CONSTANT ASCII_D_LC , 64 ; d
|
CONSTANT ASCII_E_LC , 65 ; e
|
CONSTANT ASCII_E_LC , 65 ; e
|
CONSTANT ASCII_F_LC , 66 ; f
|
CONSTANT ASCII_F_LC , 66 ; f
|
CONSTANT ASCII_G_LC , 67 ; g
|
CONSTANT ASCII_G_LC , 67 ; g
|
CONSTANT ASCII_H_LC , 68 ; h
|
CONSTANT ASCII_H_LC , 68 ; h
|
CONSTANT ASCII_I_LC , 69 ; i
|
CONSTANT ASCII_I_LC , 69 ; i
|
CONSTANT ASCII_J_LC , 6A ; j
|
CONSTANT ASCII_J_LC , 6A ; j
|
CONSTANT ASCII_K_LC , 6B ; k
|
CONSTANT ASCII_K_LC , 6B ; k
|
CONSTANT ASCII_L_LC , 6C ; l
|
CONSTANT ASCII_L_LC , 6C ; l
|
CONSTANT ASCII_M_LC , 6D ; m
|
CONSTANT ASCII_M_LC , 6D ; m
|
CONSTANT ASCII_N_LC , 6E ; n
|
CONSTANT ASCII_N_LC , 6E ; n
|
CONSTANT ASCII_O_LC , 6F ; o
|
CONSTANT ASCII_O_LC , 6F ; o
|
CONSTANT ASCII_P_LC , 70 ; p
|
CONSTANT ASCII_P_LC , 70 ; p
|
CONSTANT ASCII_Q_LC , 71 ; q
|
CONSTANT ASCII_Q_LC , 71 ; q
|
CONSTANT ASCII_R_LC , 72 ; r
|
CONSTANT ASCII_R_LC , 72 ; r
|
CONSTANT ASCII_S_LC , 73 ; s
|
CONSTANT ASCII_S_LC , 73 ; s
|
CONSTANT ASCII_T_LC , 74 ; t
|
CONSTANT ASCII_T_LC , 74 ; t
|
CONSTANT ASCII_U_LC , 75 ; u
|
CONSTANT ASCII_U_LC , 75 ; u
|
CONSTANT ASCII_V_LC , 76 ; v
|
CONSTANT ASCII_V_LC , 76 ; v
|
CONSTANT ASCII_W_LC , 77 ; w
|
CONSTANT ASCII_W_LC , 77 ; w
|
CONSTANT ASCII_X_LC , 78 ; x
|
CONSTANT ASCII_X_LC , 78 ; x
|
CONSTANT ASCII_Y_LC , 79 ; y
|
CONSTANT ASCII_Y_LC , 79 ; y
|
CONSTANT ASCII_Z_LC , 7A ; z
|
CONSTANT ASCII_Z_LC , 7A ; z
|
CONSTANT ASCII_OPN_BRACE_SIGN , 7B ; {
|
CONSTANT ASCII_OPN_BRACE_SIGN , 7B ; {
|
CONSTANT ASCII_VERTICAL_BAR_SIGN , 7C ; |
|
CONSTANT ASCII_VERTICAL_BAR_SIGN , 7C ; |
|
CONSTANT ASCII_CLS_BRACE_SIGN , 7D ; }
|
CONSTANT ASCII_CLS_BRACE_SIGN , 7D ; }
|
CONSTANT ASCII_TILDE_SIGN , 7E ; ~
|
CONSTANT ASCII_TILDE_SIGN , 7E ; ~
|
CONSTANT ASCII_DEL_CHAR , 7F ; DEL
|
CONSTANT ASCII_DEL_CHAR , 7F ; DEL
|
|
|