--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This sourcecode is released under BSD license.
|
-- This sourcecode is released under BSD license.
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright (c) 2011, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- Copyright (c) 2011, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- All rights reserved.
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-- All rights reserved.
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--
|
--
|
-- Redistribution and use in source and binary forms, with or without
|
-- Redistribution and use in source and binary forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
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--
|
--
|
-- * Redistributions of source code must retain the above copyright notice,
|
-- * Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
-- * Redistributions in binary form must reproduce the above copyright notice,
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-- * Redistributions in binary form must reproduce the above copyright notice,
|
-- this list of conditions and the following disclaimer in the documentation
|
-- this list of conditions and the following disclaimer in the documentation
|
-- and/or other materials provided with the distribution.
|
-- and/or other materials provided with the distribution.
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-- * Neither the name of the author nor the names of his contributors may be
|
|
-- used to endorse or promote products derived from this software without
|
|
-- specific prior written permission.
|
|
--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- filename: avnet_sp3a_eval_gpio_vhd.vhd
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-- filename: avnet_sp3a_eval_gpio_vhd.vhd
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-- description: synthesizable PicoBlaze (TM) general purpose i/o example using
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-- description: synthesizable PicoBlaze (TM) general purpose i/o example using
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-- wishbone / AVNET (R) Sp3A-Eval-Kit version
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-- wishbone / AVNET (R) Sp3A-Eval-Kit version
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-- todo4user: add other modules as needed
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-- todo4user: add other modules as needed
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-- version: 0.0.0
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-- version: 0.0.0
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-- changelog: - 0.0.0, initial release
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-- changelog: - 0.0.0, initial release
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-- - ...
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-- - ...
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity avnet_sp3a_eval_gpio_vhd is
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entity avnet_sp3a_eval_gpio_vhd is
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port
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port
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(
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(
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FPGA_RESET : in std_logic;
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FPGA_RESET : in std_logic;
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CLK_16MHZ : in std_logic;
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CLK_16MHZ : in std_logic;
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FPGA_PUSH_A : in std_logic;
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FPGA_PUSH_A : in std_logic;
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FPGA_PUSH_B : in std_logic;
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FPGA_PUSH_B : in std_logic;
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FPGA_PUSH_C : in std_logic;
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FPGA_PUSH_C : in std_logic;
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|
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LED1 : out std_logic;
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LED1 : out std_logic;
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LED2 : out std_logic;
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LED2 : out std_logic;
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LED3 : out std_logic;
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LED3 : out std_logic;
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LED4 : out std_logic
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LED4 : out std_logic
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);
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);
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end avnet_sp3a_eval_gpio_vhd;
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end avnet_sp3a_eval_gpio_vhd;
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architecture rtl of avnet_sp3a_eval_gpio_vhd is
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architecture rtl of avnet_sp3a_eval_gpio_vhd is
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component kcpsm3 is
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component kcpsm3 is
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port
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port
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(
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(
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address : out std_logic_vector(9 downto 0);
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address : out std_logic_vector(9 downto 0);
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instruction : in std_logic_vector(17 downto 0);
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instruction : in std_logic_vector(17 downto 0);
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port_id : out std_logic_vector(7 downto 0);
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port_id : out std_logic_vector(7 downto 0);
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write_strobe : out std_logic;
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write_strobe : out std_logic;
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out_port : out std_logic_vector(7 downto 0);
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out_port : out std_logic_vector(7 downto 0);
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read_strobe : out std_logic;
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read_strobe : out std_logic;
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in_port : in std_logic_vector(7 downto 0);
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in_port : in std_logic_vector(7 downto 0);
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interrupt : in std_logic;
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interrupt : in std_logic;
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interrupt_ack : out std_logic;
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interrupt_ack : out std_logic;
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic
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clk : in std_logic
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);
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);
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end component;
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end component;
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component pbwbgpio is
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component pbwbgpio is
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port
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port
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(
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(
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address : in std_logic_vector(9 downto 0);
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address : in std_logic_vector(9 downto 0);
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instruction : out std_logic_vector(17 downto 0);
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instruction : out std_logic_vector(17 downto 0);
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clk : in std_logic
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clk : in std_logic
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);
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);
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end component;
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end component;
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component wbm_picoblaze is
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component wbm_picoblaze is
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port
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port
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(
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(
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rst : in std_logic;
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rst : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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wbm_cyc_o : out std_logic;
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wbm_cyc_o : out std_logic;
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wbm_stb_o : out std_logic;
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wbm_stb_o : out std_logic;
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wbm_we_o : out std_logic;
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wbm_we_o : out std_logic;
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wbm_adr_o : out std_logic_vector(7 downto 0);
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wbm_adr_o : out std_logic_vector(7 downto 0);
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wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
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wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
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wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
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wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
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wbm_ack_i : in std_logic;
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wbm_ack_i : in std_logic;
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pb_port_id_i : in std_logic_vector(7 downto 0);
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pb_port_id_i : in std_logic_vector(7 downto 0);
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pb_write_strobe_i : in std_logic;
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pb_write_strobe_i : in std_logic;
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pb_out_port_i : in std_logic_vector(7 downto 0);
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pb_out_port_i : in std_logic_vector(7 downto 0);
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pb_read_strobe_i : in std_logic;
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pb_read_strobe_i : in std_logic;
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pb_in_port_o : out std_logic_vector(7 downto 0)
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pb_in_port_o : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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component wbs_gpio is
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component wbs_gpio is
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port
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port
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(
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(
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rst : in std_logic;
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rst : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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|
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wbs_cyc_i : in std_logic;
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wbs_cyc_i : in std_logic;
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wbs_stb_i : in std_logic;
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wbs_stb_i : in std_logic;
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wbs_we_i : in std_logic;
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wbs_we_i : in std_logic;
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wbs_adr_i : in std_logic_vector(7 downto 0);
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wbs_adr_i : in std_logic_vector(7 downto 0);
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wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
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wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
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wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
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wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
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wbs_ack_o : out std_logic;
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wbs_ack_o : out std_logic;
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|
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gpio_in_i : in std_logic_vector(7 downto 0);
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gpio_in_i : in std_logic_vector(7 downto 0);
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gpio_out_o : out std_logic_vector(7 downto 0);
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gpio_out_o : out std_logic_vector(7 downto 0);
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gpio_oe_o : out std_logic_vector(7 downto 0)
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gpio_oe_o : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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signal rst : std_logic := '1';
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal clk : std_logic := '1';
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|
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signal wb_cyc : std_logic := '0';
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signal wb_cyc : std_logic := '0';
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signal wb_stb : std_logic := '0';
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signal wb_stb : std_logic := '0';
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signal wb_we : std_logic := '0';
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signal wb_we : std_logic := '0';
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signal wb_adr : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_adr : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_ack : std_logic := '0';
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signal wb_ack : std_logic := '0';
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|
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signal pb_write_strobe : std_logic := '0';
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signal pb_write_strobe : std_logic := '0';
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signal pb_read_strobe : std_logic := '0';
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signal pb_read_strobe : std_logic := '0';
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signal pb_port_id : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_port_id : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_out_port : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_out_port : std_logic_vector(7 downto 0) := (others => '0');
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|
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signal instruction : std_logic_vector(17 downto 0) := (others => '0');
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signal instruction : std_logic_vector(17 downto 0) := (others => '0');
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signal address : std_logic_vector(9 downto 0) := (others => '0');
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signal address : std_logic_vector(9 downto 0) := (others => '0');
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|
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal interrupt_ack : std_logic := '0';
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signal interrupt_ack : std_logic := '0';
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|
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signal gpio_in : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_in : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_out : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_out : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0');
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|
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signal timer : unsigned(23 downto 0) := (others => '0');
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signal timer : unsigned(23 downto 0) := (others => '0');
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begin
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begin
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|
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-- reset synchronisation
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-- reset synchronisation
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process(clk)
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process(clk)
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begin
|
begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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rst <= FPGA_RESET;
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rst <= FPGA_RESET;
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end if;
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end if;
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end process;
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end process;
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clk <= CLK_16MHZ;
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clk <= CLK_16MHZ;
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-- module instances
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-- module instances
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-------------------
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-------------------
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inst_kcpsm3 : kcpsm3
|
inst_kcpsm3 : kcpsm3
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port map
|
port map
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(
|
(
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address => address,
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address => address,
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instruction => instruction,
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instruction => instruction,
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port_id => pb_port_id,
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port_id => pb_port_id,
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write_strobe => pb_write_strobe,
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write_strobe => pb_write_strobe,
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out_port => pb_out_port,
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out_port => pb_out_port,
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read_strobe => pb_read_strobe,
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read_strobe => pb_read_strobe,
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in_port => pb_in_port,
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in_port => pb_in_port,
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interrupt => interrupt,
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interrupt => interrupt,
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interrupt_ack => interrupt_ack,
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interrupt_ack => interrupt_ack,
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reset => rst,
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reset => rst,
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clk => clk
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clk => clk
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);
|
);
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|
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inst_pbwbgpio : pbwbgpio
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inst_pbwbgpio : pbwbgpio
|
port map
|
port map
|
(
|
(
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address => address,
|
address => address,
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instruction => instruction,
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instruction => instruction,
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clk => clk
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clk => clk
|
);
|
);
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|
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inst_wbm_picoblaze : wbm_picoblaze
|
inst_wbm_picoblaze : wbm_picoblaze
|
port map
|
port map
|
(
|
(
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rst => rst,
|
rst => rst,
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clk => clk,
|
clk => clk,
|
|
|
wbm_cyc_o => wb_cyc,
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wbm_cyc_o => wb_cyc,
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wbm_stb_o => wb_stb,
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wbm_stb_o => wb_stb,
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wbm_we_o => wb_we,
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wbm_we_o => wb_we,
|
wbm_adr_o => wb_adr,
|
wbm_adr_o => wb_adr,
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wbm_dat_m2s_o => wb_dat_m2s,
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wbm_dat_m2s_o => wb_dat_m2s,
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wbm_dat_s2m_i => wb_dat_s2m,
|
wbm_dat_s2m_i => wb_dat_s2m,
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wbm_ack_i => wb_ack,
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wbm_ack_i => wb_ack,
|
|
|
pb_port_id_i => pb_port_id,
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pb_port_id_i => pb_port_id,
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pb_write_strobe_i => pb_write_strobe,
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pb_write_strobe_i => pb_write_strobe,
|
pb_out_port_i => pb_out_port,
|
pb_out_port_i => pb_out_port,
|
pb_read_strobe_i => pb_read_strobe,
|
pb_read_strobe_i => pb_read_strobe,
|
pb_in_port_o => pb_in_port
|
pb_in_port_o => pb_in_port
|
);
|
);
|
|
|
inst_wbs_gpio : wbs_gpio
|
inst_wbs_gpio : wbs_gpio
|
port map
|
port map
|
(
|
(
|
rst => rst,
|
rst => rst,
|
clk => clk,
|
clk => clk,
|
|
|
wbs_cyc_i => wb_cyc,
|
wbs_cyc_i => wb_cyc,
|
wbs_stb_i => wb_stb,
|
wbs_stb_i => wb_stb,
|
wbs_we_i => wb_we,
|
wbs_we_i => wb_we,
|
wbs_adr_i => wb_adr,
|
wbs_adr_i => wb_adr,
|
wbs_dat_m2s_i => wb_dat_m2s,
|
wbs_dat_m2s_i => wb_dat_m2s,
|
wbs_dat_s2m_o => wb_dat_s2m,
|
wbs_dat_s2m_o => wb_dat_s2m,
|
wbs_ack_o => wb_ack,
|
wbs_ack_o => wb_ack,
|
|
|
gpio_in_i => gpio_in,
|
gpio_in_i => gpio_in,
|
gpio_out_o => gpio_out,
|
gpio_out_o => gpio_out,
|
gpio_oe_o => gpio_oe
|
gpio_oe_o => gpio_oe
|
);
|
);
|
|
|
-- i/o buffer generation
|
-- i/o buffer generation
|
|
|
gpio_in <= (
|
gpio_in <= (
|
4 => FPGA_PUSH_A,
|
4 => FPGA_PUSH_A,
|
5 => FPGA_PUSH_B,
|
5 => FPGA_PUSH_B,
|
6 => FPGA_PUSH_C,
|
6 => FPGA_PUSH_C,
|
others => '0'
|
others => '0'
|
);
|
);
|
|
|
LED1 <= gpio_out(0);
|
LED1 <= gpio_out(0);
|
LED2 <= gpio_out(1);
|
LED2 <= gpio_out(1);
|
LED3 <= gpio_out(2);
|
LED3 <= gpio_out(2);
|
LED4 <= timer(23);
|
LED4 <= timer(23);
|
|
|
led_blinker : process(clk)
|
led_blinker : process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
timer <= timer + 1;
|
timer <= timer + 1;
|
if rst = '1' then
|
if rst = '1' then
|
timer <= (others => '0');
|
timer <= (others => '0');
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end rtl;
|
end rtl;
|
|
|
