////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// This sourcecode is released under BSD license.
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// This sourcecode is released under BSD license.
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// Please see http://www.opensource.org/licenses/bsd-license.php for details!
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// Please see http://www.opensource.org/licenses/bsd-license.php for details!
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// * Redistributions of source code must retain the above copyright notice,
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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// * Neither the name of the author nor the names of his contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// filename: wbm_picoblaze.v
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// filename: wbm_picoblaze.v
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// description: synthesizable wishbone master adapter for PicoBlaze (TM),
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// description: synthesizable wishbone master adapter for PicoBlaze (TM),
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// working together with "wb_wr" and "wb_rd" assembler subroutines
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// working together with "wb_wr" and "wb_rd" assembler subroutines
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// todo4user: module should not be changed!
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// todo4user: module should not be changed!
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// version: 0.0.0
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// version: 0.0.0
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// changelog: - 0.0.0, initial release
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// changelog: - 0.0.0, initial release
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// - ...
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// - ...
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module wbm_picoblaze (
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module wbm_picoblaze (
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rst,
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rst,
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clk,
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clk,
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wbm_cyc_o,
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wbm_cyc_o,
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wbm_stb_o,
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wbm_stb_o,
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wbm_we_o,
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wbm_we_o,
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wbm_adr_o,
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wbm_adr_o,
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wbm_dat_m2s_o,
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wbm_dat_m2s_o,
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wbm_dat_s2m_i,
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wbm_dat_s2m_i,
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wbm_ack_i,
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wbm_ack_i,
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pb_port_id_i,
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pb_port_id_i,
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pb_write_strobe_i,
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pb_write_strobe_i,
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pb_out_port_i,
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pb_out_port_i,
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pb_read_strobe_i,
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pb_read_strobe_i,
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pb_in_port_o
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pb_in_port_o
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);
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);
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input rst;
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input rst;
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wire rst;
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wire rst;
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input clk;
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input clk;
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wire clk;
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wire clk;
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output wbm_cyc_o;
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output wbm_cyc_o;
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wire wbm_cyc_o;
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wire wbm_cyc_o;
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output wbm_stb_o;
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output wbm_stb_o;
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reg wbm_stb_o;
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reg wbm_stb_o;
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output wbm_we_o;
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output wbm_we_o;
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reg wbm_we_o;
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reg wbm_we_o;
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output[7:0] wbm_adr_o;
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output[7:0] wbm_adr_o;
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reg [7:0] wbm_adr_o;
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reg [7:0] wbm_adr_o;
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output[7:0] wbm_dat_m2s_o;
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output[7:0] wbm_dat_m2s_o;
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reg [7:0] wbm_dat_m2s_o;
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reg [7:0] wbm_dat_m2s_o;
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input[7:0] wbm_dat_s2m_i;
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input[7:0] wbm_dat_s2m_i;
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wire [7:0] wbm_dat_s2m_i;
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wire [7:0] wbm_dat_s2m_i;
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input wbm_ack_i;
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input wbm_ack_i;
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wire wbm_ack_i;
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wire wbm_ack_i;
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input[7:0] pb_port_id_i;
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input[7:0] pb_port_id_i;
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wire [7:0] pb_port_id_i;
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wire [7:0] pb_port_id_i;
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input pb_write_strobe_i;
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input pb_write_strobe_i;
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wire pb_write_strobe_i;
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wire pb_write_strobe_i;
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input[7:0] pb_out_port_i;
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input[7:0] pb_out_port_i;
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wire [7:0] pb_out_port_i;
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wire [7:0] pb_out_port_i;
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input pb_read_strobe_i;
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input pb_read_strobe_i;
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wire pb_read_strobe_i;
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wire pb_read_strobe_i;
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output[7:0] pb_in_port_o;
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output[7:0] pb_in_port_o;
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reg [7:0] pb_in_port_o;
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reg [7:0] pb_in_port_o;
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reg[7:0] wb_buffer;
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reg[7:0] wb_buffer;
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parameter[7:0] WB_ACK_FLAG = 8'h01;
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parameter[7:0] WB_ACK_FLAG = 8'h01;
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parameter[1:0]
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parameter[1:0]
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S_IDLE = 2'b00,
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S_IDLE = 2'b00,
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S_WAIT_ON_WB_ACK = 2'b01,
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S_WAIT_ON_WB_ACK = 2'b01,
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S_SOFTWARE_HANDSHAKE = 2'b10,
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S_SOFTWARE_HANDSHAKE = 2'b10,
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S_SOFTWARE_READ = 2'b11
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S_SOFTWARE_READ = 2'b11
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;
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;
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reg[1:0] state;
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reg[1:0] state;
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assign wbm_cyc_o = wbm_stb_o;
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assign wbm_cyc_o = wbm_stb_o;
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always@(posedge clk) begin
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always@(posedge clk) begin
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case(state)
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case(state)
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S_IDLE:
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S_IDLE:
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// setting up wishbone address, data and control signals from
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// setting up wishbone address, data and control signals from
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// PicoBlaze (TM) signals
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// PicoBlaze (TM) signals
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if (pb_write_strobe_i) begin
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if (pb_write_strobe_i) begin
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wbm_stb_o <= 1'b1;
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wbm_stb_o <= 1'b1;
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wbm_we_o <= 1'b1;
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wbm_we_o <= 1'b1;
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wbm_adr_o <= pb_port_id_i;
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wbm_adr_o <= pb_port_id_i;
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wbm_dat_m2s_o <= pb_out_port_i;
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wbm_dat_m2s_o <= pb_out_port_i;
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state <= S_WAIT_ON_WB_ACK;
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state <= S_WAIT_ON_WB_ACK;
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end else if (pb_read_strobe_i) begin
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end else if (pb_read_strobe_i) begin
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wbm_stb_o <= 1'b1;
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wbm_stb_o <= 1'b1;
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wbm_we_o <= 1'b0;
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wbm_we_o <= 1'b0;
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wbm_adr_o <= pb_port_id_i;
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wbm_adr_o <= pb_port_id_i;
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state <= S_WAIT_ON_WB_ACK;
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state <= S_WAIT_ON_WB_ACK;
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end
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end
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S_WAIT_ON_WB_ACK:
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S_WAIT_ON_WB_ACK:
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// waiting on slave peripheral to complete wishbone transfer cycle
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// waiting on slave peripheral to complete wishbone transfer cycle
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if (wbm_ack_i) begin
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if (wbm_ack_i) begin
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wbm_stb_o <= 1'b0;
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wbm_stb_o <= 1'b0;
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wb_buffer <= wbm_dat_s2m_i;
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wb_buffer <= wbm_dat_s2m_i;
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pb_in_port_o <= WB_ACK_FLAG;
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pb_in_port_o <= WB_ACK_FLAG;
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state <= S_SOFTWARE_HANDSHAKE;
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state <= S_SOFTWARE_HANDSHAKE;
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end
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end
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S_SOFTWARE_HANDSHAKE:
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S_SOFTWARE_HANDSHAKE:
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// software recognition of wishbone handshake
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// software recognition of wishbone handshake
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if (pb_read_strobe_i)
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if (pb_read_strobe_i)
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// transfer complete for a write access
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// transfer complete for a write access
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if (wbm_we_o) begin
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if (wbm_we_o) begin
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pb_in_port_o <= 8'h00;
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pb_in_port_o <= 8'h00;
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state <= S_IDLE;
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state <= S_IDLE;
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// presenting valid wishbone data to PicoBlaze (TM) port in read
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// presenting valid wishbone data to PicoBlaze (TM) port in read
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// access
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// access
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end else begin
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end else begin
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pb_in_port_o <= wb_buffer;
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pb_in_port_o <= wb_buffer;
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state <= S_SOFTWARE_READ;
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state <= S_SOFTWARE_READ;
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end
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end
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S_SOFTWARE_READ:
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S_SOFTWARE_READ:
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// transfer complete for a read access after software recognition of
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// transfer complete for a read access after software recognition of
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// wishbone data
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// wishbone data
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if (pb_read_strobe_i) begin
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if (pb_read_strobe_i) begin
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pb_in_port_o <= 8'h00;
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pb_in_port_o <= 8'h00;
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state <= S_IDLE;
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state <= S_IDLE;
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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if (rst) begin
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if (rst) begin
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wbm_stb_o <= 1'b0;
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wbm_stb_o <= 1'b0;
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pb_in_port_o <= 8'h00;
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pb_in_port_o <= 8'h00;
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state <= S_IDLE;
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state <= S_IDLE;
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end
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end
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end
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end
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endmodule
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endmodule
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