--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This sourcecode is released under BSD license.
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-- This sourcecode is released under BSD license.
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- * Redistributions of source code must retain the above copyright notice,
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- and/or other materials provided with the distribution.
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-- * Neither the name of the author nor the names of his contributors may be
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-- used to endorse or promote products derived from this software without
|
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- filename: wbm_picoblaze.vhd
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-- filename: wbm_picoblaze.vhd
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-- description: synthesizable wishbone master adapter for PicoBlaze (TM),
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-- description: synthesizable wishbone master adapter for PicoBlaze (TM),
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-- working together with "wb_wr" and "wb_rd" assembler subroutines
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-- working together with "wb_wr" and "wb_rd" assembler subroutines
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-- todo4user: module should not be changed!
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-- todo4user: module should not be changed!
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-- version: 0.0.0
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-- version: 0.0.0
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-- changelog: - 0.0.0, initial release
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-- changelog: - 0.0.0, initial release
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-- - ...
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-- - ...
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity wbm_picoblaze is
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entity wbm_picoblaze is
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port
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port
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(
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(
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rst : in std_logic;
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rst : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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wbm_cyc_o : out std_logic;
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wbm_cyc_o : out std_logic;
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wbm_stb_o : out std_logic;
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wbm_stb_o : out std_logic;
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wbm_we_o : out std_logic;
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wbm_we_o : out std_logic;
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wbm_adr_o : out std_logic_vector(7 downto 0);
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wbm_adr_o : out std_logic_vector(7 downto 0);
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wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
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wbm_dat_m2s_o : out std_logic_vector(7 downto 0);
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wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
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wbm_dat_s2m_i : in std_logic_vector(7 downto 0);
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wbm_ack_i : in std_logic;
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wbm_ack_i : in std_logic;
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pb_port_id_i : in std_logic_vector(7 downto 0);
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pb_port_id_i : in std_logic_vector(7 downto 0);
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pb_write_strobe_i : in std_logic;
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pb_write_strobe_i : in std_logic;
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pb_out_port_i : in std_logic_vector(7 downto 0);
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pb_out_port_i : in std_logic_vector(7 downto 0);
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pb_read_strobe_i : in std_logic;
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pb_read_strobe_i : in std_logic;
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pb_in_port_o : out std_logic_vector(7 downto 0)
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pb_in_port_o : out std_logic_vector(7 downto 0)
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);
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);
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end wbm_picoblaze;
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end wbm_picoblaze;
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architecture rtl of wbm_picoblaze is
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architecture rtl of wbm_picoblaze is
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signal wbm_cyc : std_logic := '0';
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signal wbm_cyc : std_logic := '0';
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signal wbm_stb : std_logic := '0';
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signal wbm_stb : std_logic := '0';
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signal wbm_we : std_logic := '0';
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signal wbm_we : std_logic := '0';
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signal wbm_adr : std_logic_vector(7 downto 0) := (others => '0');
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signal wbm_adr : std_logic_vector(7 downto 0) := (others => '0');
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signal wbm_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
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signal wbm_dat_m2s : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
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signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_buffer : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_buffer : std_logic_vector(7 downto 0) := (others => '0');
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constant WB_ACK_FLAG : std_logic_vector(7 downto 0) := x"01";
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constant WB_ACK_FLAG : std_logic_vector(7 downto 0) := x"01";
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type t_states is
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type t_states is
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(
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(
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S_IDLE,
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S_IDLE,
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S_WAIT_ON_WB_ACK,
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S_WAIT_ON_WB_ACK,
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S_SOFTWARE_HANDSHAKE,
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S_SOFTWARE_HANDSHAKE,
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S_SOFTWARE_READ
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S_SOFTWARE_READ
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);
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);
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signal state : t_states := S_IDLE;
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signal state : t_states := S_IDLE;
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begin
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begin
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wbm_cyc_o <= wbm_cyc;
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wbm_cyc_o <= wbm_cyc;
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wbm_stb_o <= wbm_stb;
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wbm_stb_o <= wbm_stb;
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wbm_we_o <= wbm_we;
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wbm_we_o <= wbm_we;
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wbm_adr_o <= wbm_adr;
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wbm_adr_o <= wbm_adr;
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wbm_dat_m2s_o <= wbm_dat_m2s;
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wbm_dat_m2s_o <= wbm_dat_m2s;
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pb_in_port_o <= pb_in_port;
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pb_in_port_o <= pb_in_port;
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wbm_cyc <= wbm_stb;
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wbm_cyc <= wbm_stb;
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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case state is
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case state is
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when S_IDLE =>
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when S_IDLE =>
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-- setting up wishbone address, data and control signals from
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-- setting up wishbone address, data and control signals from
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-- PicoBlaze (TM) signals
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-- PicoBlaze (TM) signals
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if pb_write_strobe_i = '1' then
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if pb_write_strobe_i = '1' then
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wbm_stb <= '1';
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wbm_stb <= '1';
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wbm_we <= '1';
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wbm_we <= '1';
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wbm_adr <= pb_port_id_i;
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wbm_adr <= pb_port_id_i;
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wbm_dat_m2s <= pb_out_port_i;
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wbm_dat_m2s <= pb_out_port_i;
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state <= S_WAIT_ON_WB_ACK;
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state <= S_WAIT_ON_WB_ACK;
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elsif pb_read_strobe_i = '1' then
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elsif pb_read_strobe_i = '1' then
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wbm_stb <= '1';
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wbm_stb <= '1';
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wbm_we <= '0';
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wbm_we <= '0';
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wbm_adr <= pb_port_id_i;
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wbm_adr <= pb_port_id_i;
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state <= S_WAIT_ON_WB_ACK;
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state <= S_WAIT_ON_WB_ACK;
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end if;
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end if;
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when S_WAIT_ON_WB_ACK =>
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when S_WAIT_ON_WB_ACK =>
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-- waiting on slave peripheral to complete wishbone transfer cycle
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-- waiting on slave peripheral to complete wishbone transfer cycle
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if wbm_ack_i = '1' then
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if wbm_ack_i = '1' then
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wbm_stb <= '0';
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wbm_stb <= '0';
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wb_buffer <= wbm_dat_s2m_i;
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wb_buffer <= wbm_dat_s2m_i;
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pb_in_port <= WB_ACK_FLAG;
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pb_in_port <= WB_ACK_FLAG;
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state <= S_SOFTWARE_HANDSHAKE;
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state <= S_SOFTWARE_HANDSHAKE;
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end if;
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end if;
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when S_SOFTWARE_HANDSHAKE =>
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when S_SOFTWARE_HANDSHAKE =>
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-- software recognition of wishbone handshake
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-- software recognition of wishbone handshake
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if pb_read_strobe_i = '1' then
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if pb_read_strobe_i = '1' then
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-- transfer complete for a write access
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-- transfer complete for a write access
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if wbm_we = '1' then
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if wbm_we = '1' then
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pb_in_port <= (others => '0');
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pb_in_port <= (others => '0');
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state <= S_IDLE;
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state <= S_IDLE;
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-- presenting valid wishbone data to PicoBlaze (TM) port in read
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-- presenting valid wishbone data to PicoBlaze (TM) port in read
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-- access
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-- access
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else
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else
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pb_in_port <= wb_buffer;
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pb_in_port <= wb_buffer;
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state <= S_SOFTWARE_READ;
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state <= S_SOFTWARE_READ;
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end if;
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end if;
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end if;
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end if;
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when S_SOFTWARE_READ =>
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when S_SOFTWARE_READ =>
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-- transfer complete for a read access after software recognition of
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-- transfer complete for a read access after software recognition of
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-- wishbone data
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-- wishbone data
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if pb_read_strobe_i = '1' then
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if pb_read_strobe_i = '1' then
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pb_in_port <= (others => '0');
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pb_in_port <= (others => '0');
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state <= S_IDLE;
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state <= S_IDLE;
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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if rst = '1' then
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if rst = '1' then
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wbm_stb <= '0';
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wbm_stb <= '0';
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pb_in_port <= (others => '0');
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pb_in_port <= (others => '0');
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state <= S_IDLE;
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state <= S_IDLE;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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