--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This sourcecode is released under BSD license.
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-- This sourcecode is released under BSD license.
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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-- Please see http://www.opensource.org/licenses/bsd-license.php for details!
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- * Redistributions of source code must retain the above copyright notice,
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- and/or other materials provided with the distribution.
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-- * Neither the name of the author nor the names of his contributors may be
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-- used to endorse or promote products derived from this software without
|
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- filename: wbs_gpio.vhd
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-- filename: wbs_gpio.vhd
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-- description: synthesizable wishbone slave general purpose i/o module
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-- description: synthesizable wishbone slave general purpose i/o module
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-- todo4user: add more i/o ports as needed
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-- todo4user: add more i/o ports as needed
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-- version: 0.0.0
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-- version: 0.0.0
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-- changelog: - 0.0.0, initial release
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-- changelog: - 0.0.0, initial release
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-- - ...
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-- - ...
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity wbs_gpio is
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entity wbs_gpio is
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port
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port
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(
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(
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rst : in std_logic;
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rst : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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wbs_cyc_i : in std_logic;
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wbs_cyc_i : in std_logic;
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wbs_stb_i : in std_logic;
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wbs_stb_i : in std_logic;
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wbs_we_i : in std_logic;
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wbs_we_i : in std_logic;
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wbs_adr_i : in std_logic_vector(7 downto 0);
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wbs_adr_i : in std_logic_vector(7 downto 0);
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wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
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wbs_dat_m2s_i : in std_logic_vector(7 downto 0);
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wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
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wbs_dat_s2m_o : out std_logic_vector(7 downto 0);
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wbs_ack_o : out std_logic;
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wbs_ack_o : out std_logic;
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gpio_in_i : in std_logic_vector(7 downto 0);
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gpio_in_i : in std_logic_vector(7 downto 0);
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gpio_out_o : out std_logic_vector(7 downto 0);
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gpio_out_o : out std_logic_vector(7 downto 0);
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gpio_oe_o : out std_logic_vector(7 downto 0)
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gpio_oe_o : out std_logic_vector(7 downto 0)
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);
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);
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end wbs_gpio;
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end wbs_gpio;
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architecture rtl of wbs_gpio is
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architecture rtl of wbs_gpio is
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signal wbs_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
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signal wbs_dat_s2m : std_logic_vector(7 downto 0) := (others => '0');
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signal wbs_ack : std_logic := '0';
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signal wbs_ack : std_logic := '0';
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signal gpio_out : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_out : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0');
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signal wb_reg_we : std_logic := '0';
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signal wb_reg_we : std_logic := '0';
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signal gpio_in : std_logic_vector(7 downto 0) := (others => '0');
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signal gpio_in : std_logic_vector(7 downto 0) := (others => '0');
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constant IS_INPUT : std_logic := '0';
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constant IS_INPUT : std_logic := '0';
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constant IS_OUTPUT : std_logic := not IS_INPUT;
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constant IS_OUTPUT : std_logic := not IS_INPUT;
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constant ADDR_MSB : natural := 0;
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constant ADDR_MSB : natural := 0;
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constant GPIO_IO_ADDR : std_logic_vector(7 downto 0) := x"00";
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constant GPIO_IO_ADDR : std_logic_vector(7 downto 0) := x"00";
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constant GPIO_OE_ADDR : std_logic_vector(7 downto 0) := x"01";
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constant GPIO_OE_ADDR : std_logic_vector(7 downto 0) := x"01";
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begin
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begin
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wbs_dat_s2m_o <= wbs_dat_s2m;
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wbs_dat_s2m_o <= wbs_dat_s2m;
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wbs_ack_o <= wbs_ack;
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wbs_ack_o <= wbs_ack;
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gpio_out_o <= gpio_out;
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gpio_out_o <= gpio_out;
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gpio_oe_o <= gpio_oe;
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gpio_oe_o <= gpio_oe;
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-- internal register write enable signal
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-- internal register write enable signal
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wb_reg_we <= wbs_cyc_i and wbs_stb_i and wbs_we_i;
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wb_reg_we <= wbs_cyc_i and wbs_stb_i and wbs_we_i;
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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gpio_in <= gpio_in_i;
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gpio_in <= gpio_in_i;
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wbs_dat_s2m <= (others => '0');
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wbs_dat_s2m <= (others => '0');
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-- registered wishbone slave handshake
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-- registered wishbone slave handshake
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wbs_ack <= wbs_cyc_i and wbs_stb_i and (not wbs_ack);
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wbs_ack <= wbs_cyc_i and wbs_stb_i and (not wbs_ack);
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case wbs_adr_i(ADDR_MSB downto 0) is
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case wbs_adr_i(ADDR_MSB downto 0) is
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-- i/o register access
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-- i/o register access
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when GPIO_IO_ADDR(ADDR_MSB downto 0) =>
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when GPIO_IO_ADDR(ADDR_MSB downto 0) =>
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if wb_reg_we = '1' then
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if wb_reg_we = '1' then
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gpio_out <= wbs_dat_m2s_i;
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gpio_out <= wbs_dat_m2s_i;
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end if;
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end if;
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wbs_dat_s2m <= gpio_in;
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wbs_dat_s2m <= gpio_in;
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-- output enable register access
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-- output enable register access
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when GPIO_OE_ADDR(ADDR_MSB downto 0) =>
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when GPIO_OE_ADDR(ADDR_MSB downto 0) =>
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if wb_reg_we = '1' then
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if wb_reg_we = '1' then
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gpio_oe <= wbs_dat_m2s_i;
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gpio_oe <= wbs_dat_m2s_i;
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end if;
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end if;
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wbs_dat_s2m <= gpio_oe;
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wbs_dat_s2m <= gpio_oe;
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when others => null;
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when others => null;
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end case;
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end case;
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if rst = '1' then
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if rst = '1' then
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wbs_ack <= '0';
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wbs_ack <= '0';
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gpio_oe <= (others => IS_INPUT);
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gpio_oe <= (others => IS_INPUT);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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