////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// This sourcecode is released under BSD license.
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// This sourcecode is released under BSD license.
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// Please see http://www.opensource.org/licenses/bsd-license.php for details!
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// Please see http://www.opensource.org/licenses/bsd-license.php for details!
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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// Copyright (c) 2010, Stefan Fischer <Ste.Fis@OpenCores.org>
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// * Redistributions of source code must retain the above copyright notice,
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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// * Neither the name of the author nor the names of his contributors may be
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// * Neither the name of the author nor the names of his contributors may be
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// used to endorse or promote products derived from this software without
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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// specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// filename: wbs_uart.v
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// filename: wbs_uart.v
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// description: synthesizable wishbone slave uart sio module using Xilinx (R)
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// description: synthesizable wishbone slave uart sio module using Xilinx (R)
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// macros and adding some functionality like a configurable
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// macros and adding some functionality like a configurable
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// baud rate and buffer level checking
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// baud rate and buffer level checking
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// todo4user: add other uart functionality as needed, i. e. interrupt logic or
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// todo4user: add other uart functionality as needed, i. e. interrupt logic or
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// modem control signals
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// modem control signals
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// version: 0.0.0
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// version: 0.0.0
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// changelog: - 0.0.0, initial release
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// changelog: - 0.0.0, initial release
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// - ...
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// - ...
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module wbs_uart (
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module wbs_uart (
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rst,
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rst,
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clk,
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clk,
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wbs_cyc_i,
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wbs_cyc_i,
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wbs_stb_i,
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wbs_stb_i,
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wbs_we_i,
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wbs_we_i,
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wbs_adr_i,
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wbs_adr_i,
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wbs_dat_m2s_i,
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wbs_dat_m2s_i,
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wbs_dat_s2m_o,
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wbs_dat_s2m_o,
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wbs_ack_o,
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wbs_ack_o,
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uart_rx_si_i,
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uart_rx_si_i,
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uart_tx_so_o
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uart_tx_so_o
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);
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);
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input rst;
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input rst;
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wire rst;
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wire rst;
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input clk;
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input clk;
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wire clk;
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wire clk;
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input wbs_cyc_i;
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input wbs_cyc_i;
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wire wbs_cyc_i;
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wire wbs_cyc_i;
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input wbs_stb_i;
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input wbs_stb_i;
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wire wbs_stb_i;
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wire wbs_stb_i;
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input wbs_we_i;
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input wbs_we_i;
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wire wbs_we_i;
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wire wbs_we_i;
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input[7:0] wbs_adr_i;
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input[7:0] wbs_adr_i;
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wire [7:0] wbs_adr_i;
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wire [7:0] wbs_adr_i;
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input[7:0] wbs_dat_m2s_i;
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input[7:0] wbs_dat_m2s_i;
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wire [7:0] wbs_dat_m2s_i;
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wire [7:0] wbs_dat_m2s_i;
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output[7:0] wbs_dat_s2m_o;
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output[7:0] wbs_dat_s2m_o;
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reg [7:0] wbs_dat_s2m_o;
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reg [7:0] wbs_dat_s2m_o;
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output wbs_ack_o;
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output wbs_ack_o;
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reg wbs_ack_o;
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reg wbs_ack_o;
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input uart_rx_si_i;
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input uart_rx_si_i;
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wire uart_rx_si_i;
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wire uart_rx_si_i;
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output uart_tx_so_o;
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output uart_tx_so_o;
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wire uart_tx_so_o;
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wire uart_tx_so_o;
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wire wb_reg_we;
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wire wb_reg_we;
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parameter ADDR_MSB = 1;
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parameter ADDR_MSB = 1;
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parameter[7:0] UART_RXTX_ADDR = 8'h00;
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parameter[7:0] UART_RXTX_ADDR = 8'h00;
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parameter[7:0] UART_SR_ADDR = 8'h01;
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parameter[7:0] UART_SR_ADDR = 8'h01;
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parameter UART_SR_RX_F_FLAG = 0;
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parameter UART_SR_RX_F_FLAG = 0;
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parameter UART_SR_RX_HF_FLAG = 1;
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parameter UART_SR_RX_HF_FLAG = 1;
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parameter UART_SR_RX_DP_FLAG = 2;
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parameter UART_SR_RX_DP_FLAG = 2;
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parameter UART_SR_TX_F_FLAG = 4;
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parameter UART_SR_TX_F_FLAG = 4;
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parameter UART_SR_TX_HF_FLAG = 5;
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parameter UART_SR_TX_HF_FLAG = 5;
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parameter[7:0] UART_BAUD_LO_ADDR = 8'h02;
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parameter[7:0] UART_BAUD_LO_ADDR = 8'h02;
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parameter[7:0] UART_BAUD_HI_ADDR = 8'h03;
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parameter[7:0] UART_BAUD_HI_ADDR = 8'h03;
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reg[15:0] baud_count;
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reg[15:0] baud_count;
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reg[15:0] baud_limit;
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reg[15:0] baud_limit;
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reg en_16_x_baud;
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reg en_16_x_baud;
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reg rx_read_buffer;
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reg rx_read_buffer;
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wire rx_buffer_full;
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wire rx_buffer_full;
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wire rx_buffer_half_full;
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wire rx_buffer_half_full;
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wire rx_buffer_data_present;
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wire rx_buffer_data_present;
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wire[7:0] rx_data_out;
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wire[7:0] rx_data_out;
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reg tx_write_buffer;
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reg tx_write_buffer;
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wire tx_buffer_full;
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wire tx_buffer_full;
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wire tx_buffer_half_full;
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wire tx_buffer_half_full;
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// internal register write enable signal
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// internal register write enable signal
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assign wb_reg_we = wbs_cyc_i && wbs_stb_i && wbs_we_i;
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assign wb_reg_we = wbs_cyc_i && wbs_stb_i && wbs_we_i;
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always@(posedge clk) begin
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always@(posedge clk) begin
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// baud rate configuration:
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// baud rate configuration:
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// baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
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// baud_limit = round( system clock frequency / (16 * baud rate) ) - 1
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// i. e. 9600 baud at 50 MHz system clock =>
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// i. e. 9600 baud at 50 MHz system clock =>
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// baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
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// baud_limit = round( 50.0E6 / (16 * 9600) ) - 1 = 325 = 0x0145
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// baud timer
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// baud timer
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if (baud_count == baud_limit) begin
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if (baud_count == baud_limit) begin
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baud_count <= 16'h0000;
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baud_count <= 16'h0000;
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en_16_x_baud <= 1'b1;
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en_16_x_baud <= 1'b1;
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end else begin
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end else begin
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baud_count <= baud_count + 1;
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baud_count <= baud_count + 1;
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en_16_x_baud <= 1'b0;
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en_16_x_baud <= 1'b0;
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end
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end
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rx_read_buffer <= 1'b0;
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rx_read_buffer <= 1'b0;
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tx_write_buffer <= 1'b0;
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tx_write_buffer <= 1'b0;
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wbs_dat_s2m_o <= 8'h00;
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wbs_dat_s2m_o <= 8'h00;
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// registered wishbone slave handshake (default)
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// registered wishbone slave handshake (default)
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wbs_ack_o <= wbs_cyc_i && wbs_stb_i && (! wbs_ack_o);
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wbs_ack_o <= wbs_cyc_i && wbs_stb_i && (! wbs_ack_o);
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case(wbs_adr_i[ADDR_MSB:0])
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case(wbs_adr_i[ADDR_MSB:0])
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// receive/transmit buffer access
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// receive/transmit buffer access
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UART_RXTX_ADDR[ADDR_MSB:0]: begin
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UART_RXTX_ADDR[ADDR_MSB:0]: begin
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if (wbs_cyc_i && wbs_stb_i)
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if (wbs_cyc_i && wbs_stb_i)
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// overwriting wishbone slave handshake for blocking transactions
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// overwriting wishbone slave handshake for blocking transactions
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// to rx/tx fifos by using buffer status flags
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// to rx/tx fifos by using buffer status flags
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if (wbs_we_i) begin
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if (wbs_we_i) begin
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tx_write_buffer <= (! tx_buffer_full) && (! wbs_ack_o);
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tx_write_buffer <= (! tx_buffer_full) && (! wbs_ack_o);
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wbs_ack_o <= (! tx_buffer_full) && (! wbs_ack_o);
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wbs_ack_o <= (! tx_buffer_full) && (! wbs_ack_o);
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end else begin
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end else begin
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rx_read_buffer <= rx_buffer_data_present && (! wbs_ack_o);
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rx_read_buffer <= rx_buffer_data_present && (! wbs_ack_o);
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wbs_ack_o <= rx_buffer_data_present && (! wbs_ack_o);
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wbs_ack_o <= rx_buffer_data_present && (! wbs_ack_o);
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end
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end
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wbs_dat_s2m_o <= rx_data_out;
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wbs_dat_s2m_o <= rx_data_out;
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end
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end
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// status register access
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// status register access
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UART_SR_ADDR[ADDR_MSB:0]: begin
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UART_SR_ADDR[ADDR_MSB:0]: begin
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wbs_dat_s2m_o[UART_SR_RX_F_FLAG] <= rx_buffer_full;
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wbs_dat_s2m_o[UART_SR_RX_F_FLAG] <= rx_buffer_full;
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wbs_dat_s2m_o[UART_SR_RX_HF_FLAG] <= rx_buffer_half_full;
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wbs_dat_s2m_o[UART_SR_RX_HF_FLAG] <= rx_buffer_half_full;
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wbs_dat_s2m_o[UART_SR_RX_DP_FLAG] <= rx_buffer_data_present;
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wbs_dat_s2m_o[UART_SR_RX_DP_FLAG] <= rx_buffer_data_present;
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wbs_dat_s2m_o[UART_SR_TX_F_FLAG] <= tx_buffer_full;
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wbs_dat_s2m_o[UART_SR_TX_F_FLAG] <= tx_buffer_full;
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wbs_dat_s2m_o[UART_SR_TX_HF_FLAG] <= tx_buffer_half_full;
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wbs_dat_s2m_o[UART_SR_TX_HF_FLAG] <= tx_buffer_half_full;
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end
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end
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// baud rate register access / low byte
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// baud rate register access / low byte
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UART_BAUD_LO_ADDR[ADDR_MSB:0]: begin
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UART_BAUD_LO_ADDR[ADDR_MSB:0]: begin
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if (wb_reg_we) begin
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if (wb_reg_we) begin
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baud_limit[7:0] <= wbs_dat_m2s_i;
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baud_limit[7:0] <= wbs_dat_m2s_i;
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baud_count <= 16'h0000;
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baud_count <= 16'h0000;
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end
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end
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wbs_dat_s2m_o <= baud_limit[7:0];
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wbs_dat_s2m_o <= baud_limit[7:0];
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end
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end
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// baud rate register access / high byte
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// baud rate register access / high byte
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UART_BAUD_HI_ADDR[ADDR_MSB:0]: begin
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UART_BAUD_HI_ADDR[ADDR_MSB:0]: begin
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if (wb_reg_we) begin
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if (wb_reg_we) begin
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baud_limit[15:8] <= wbs_dat_m2s_i;
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baud_limit[15:8] <= wbs_dat_m2s_i;
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baud_count <= 16'h0000;
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baud_count <= 16'h0000;
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end
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end
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wbs_dat_s2m_o <= baud_limit[15:8];
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wbs_dat_s2m_o <= baud_limit[15:8];
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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if (rst) begin
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if (rst)
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wbs_ack_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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end
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end
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end
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// Xilinx (R) uart macro instances
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// Xilinx (R) uart macro instances
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//////////////////////////////////
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//////////////////////////////////
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uart_rx inst_uart_rx (
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uart_rx inst_uart_rx (
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.serial_in(uart_rx_si_i),
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.serial_in(uart_rx_si_i),
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.data_out(rx_data_out),
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.data_out(rx_data_out),
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.read_buffer(rx_read_buffer),
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.read_buffer(rx_read_buffer),
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.reset_buffer(rst),
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.reset_buffer(rst),
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.en_16_x_baud(en_16_x_baud),
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.en_16_x_baud(en_16_x_baud),
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.buffer_data_present(rx_buffer_data_present),
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.buffer_data_present(rx_buffer_data_present),
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.buffer_full(rx_buffer_full),
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.buffer_full(rx_buffer_full),
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.buffer_half_full(rx_buffer_half_full),
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.buffer_half_full(rx_buffer_half_full),
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.clk(clk)
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.clk(clk)
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);
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);
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uart_tx inst_uart_tx (
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uart_tx inst_uart_tx (
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.data_in(wbs_dat_m2s_i),
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.data_in(wbs_dat_m2s_i),
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.write_buffer(tx_write_buffer),
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.write_buffer(tx_write_buffer),
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.reset_buffer(rst),
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.reset_buffer(rst),
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.en_16_x_baud(en_16_x_baud),
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.en_16_x_baud(en_16_x_baud),
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.serial_out(uart_tx_so_o),
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.serial_out(uart_tx_so_o),
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.buffer_full(tx_buffer_full),
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.buffer_full(tx_buffer_full),
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.buffer_half_full(tx_buffer_half_full),
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.buffer_half_full(tx_buffer_half_full),
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.clk(clk)
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.clk(clk)
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);
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);
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endmodule
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endmodule
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