//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// File name : s29al032d_00.v
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// File name : s29al032d_00.v
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2005 Spansion, LLC.
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// Copyright (C) 2005 Spansion, LLC.
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//
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//
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// MODIFICATION HISTORY :
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// MODIFICATION HISTORY :
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//
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//
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//
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//
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// version: | author: | mod date: | changes made:
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// version: | author: | mod date: | changes made:
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// V1.0 D.Lukovic 05 May 17 Initial release
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// V1.0 D.Lukovic 05 May 17 Initial release
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//
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//
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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//
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//
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// PART DESCRIPTION:
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// PART DESCRIPTION:
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//
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//
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// Library: FLASH
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// Library: FLASH
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// Technology: Flash memory
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// Technology: Flash memory
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// Part: s29al032d_00
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// Part: s29al032d_00
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//
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//
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// Description: 32Mbit (4M x 8-Bit) Flash Memory
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// Description: 32Mbit (4M x 8-Bit) Flash Memory
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//
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//
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Known Bugs:
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// Known Bugs:
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ns/1 ns
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`timescale 1 ns/1 ns
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|
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module s29al032d_00
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module s29al032d_00
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(
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(
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A21 ,
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A21 ,
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A20 ,
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A20 ,
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A19 ,
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A19 ,
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A18 ,
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A18 ,
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A17 ,
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A17 ,
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A16 ,
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A16 ,
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A15 ,
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A15 ,
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A14 ,
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A14 ,
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A13 ,
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A13 ,
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A12 ,
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A12 ,
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A11 ,
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A11 ,
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A10 ,
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A10 ,
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A9 ,
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A9 ,
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A8 ,
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A8 ,
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A7 ,
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A7 ,
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A6 ,
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A6 ,
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A5 ,
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A5 ,
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A4 ,
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A4 ,
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A3 ,
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A3 ,
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A2 ,
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A2 ,
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A1 ,
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A1 ,
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A0 ,
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A0 ,
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|
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DQ7 ,
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DQ7 ,
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DQ6 ,
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DQ6 ,
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DQ5 ,
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DQ5 ,
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DQ4 ,
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DQ4 ,
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DQ3 ,
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DQ3 ,
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DQ2 ,
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DQ2 ,
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DQ1 ,
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DQ1 ,
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DQ0 ,
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DQ0 ,
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|
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CENeg ,
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CENeg ,
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OENeg ,
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OENeg ,
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WENeg ,
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WENeg ,
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RESETNeg ,
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RESETNeg ,
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ACC ,
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ACC ,
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RY
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RY
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|
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);
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);
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Port / Part Pin Declarations
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// Port / Part Pin Declarations
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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input A21 ;
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input A21 ;
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input A20 ;
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input A20 ;
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input A19 ;
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input A19 ;
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input A18 ;
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input A18 ;
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input A17 ;
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input A17 ;
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input A16 ;
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input A16 ;
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input A15 ;
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input A15 ;
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input A14 ;
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input A14 ;
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input A13 ;
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input A13 ;
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input A12 ;
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input A12 ;
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input A11 ;
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input A11 ;
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input A10 ;
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input A10 ;
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input A9 ;
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input A9 ;
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input A8 ;
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input A8 ;
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input A7 ;
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input A7 ;
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input A6 ;
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input A6 ;
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input A5 ;
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input A5 ;
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input A4 ;
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input A4 ;
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input A3 ;
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input A3 ;
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input A2 ;
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input A2 ;
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input A1 ;
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input A1 ;
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input A0 ;
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input A0 ;
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|
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inout DQ7 ;
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inout DQ7 ;
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inout DQ6 ;
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inout DQ6 ;
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inout DQ5 ;
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inout DQ5 ;
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inout DQ4 ;
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inout DQ4 ;
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inout DQ3 ;
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inout DQ3 ;
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inout DQ2 ;
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inout DQ2 ;
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inout DQ1 ;
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inout DQ1 ;
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inout DQ0 ;
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inout DQ0 ;
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|
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input CENeg ;
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input CENeg ;
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input OENeg ;
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input OENeg ;
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input WENeg ;
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input WENeg ;
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input RESETNeg ;
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input RESETNeg ;
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input ACC ;
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input ACC ;
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output RY ;
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output RY ;
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|
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// interconnect path delay signals
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// interconnect path delay signals
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|
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wire A21_ipd ;
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wire A21_ipd ;
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wire A20_ipd ;
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wire A20_ipd ;
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wire A19_ipd ;
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wire A19_ipd ;
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wire A18_ipd ;
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wire A18_ipd ;
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wire A17_ipd ;
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wire A17_ipd ;
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wire A16_ipd ;
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wire A16_ipd ;
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wire A15_ipd ;
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wire A15_ipd ;
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wire A14_ipd ;
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wire A14_ipd ;
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wire A13_ipd ;
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wire A13_ipd ;
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wire A12_ipd ;
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wire A12_ipd ;
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wire A11_ipd ;
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wire A11_ipd ;
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wire A10_ipd ;
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wire A10_ipd ;
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wire A9_ipd ;
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wire A9_ipd ;
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wire A8_ipd ;
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wire A8_ipd ;
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wire A7_ipd ;
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wire A7_ipd ;
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wire A6_ipd ;
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wire A6_ipd ;
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wire A5_ipd ;
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wire A5_ipd ;
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wire A4_ipd ;
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wire A4_ipd ;
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wire A3_ipd ;
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wire A3_ipd ;
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wire A2_ipd ;
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wire A2_ipd ;
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wire A1_ipd ;
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wire A1_ipd ;
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wire A0_ipd ;
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wire A0_ipd ;
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wire [21 : 0] A;
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wire [21 : 0] A;
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assign A = {
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assign A = {
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A21_ipd,
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A21_ipd,
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A20_ipd,
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A20_ipd,
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A19_ipd,
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A19_ipd,
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A18_ipd,
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A18_ipd,
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A17_ipd,
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A17_ipd,
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A16_ipd,
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A16_ipd,
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A15_ipd,
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A15_ipd,
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A14_ipd,
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A14_ipd,
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A13_ipd,
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A13_ipd,
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A12_ipd,
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A12_ipd,
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A11_ipd,
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A11_ipd,
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A10_ipd,
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A10_ipd,
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A9_ipd,
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A9_ipd,
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A8_ipd,
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A8_ipd,
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A7_ipd,
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A7_ipd,
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A6_ipd,
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A6_ipd,
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A5_ipd,
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A5_ipd,
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A4_ipd,
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A4_ipd,
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A3_ipd,
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A3_ipd,
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A2_ipd,
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A2_ipd,
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A1_ipd,
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A1_ipd,
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A0_ipd };
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A0_ipd };
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wire DQ7_ipd ;
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wire DQ7_ipd ;
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wire DQ6_ipd ;
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wire DQ6_ipd ;
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wire DQ5_ipd ;
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wire DQ5_ipd ;
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wire DQ4_ipd ;
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wire DQ4_ipd ;
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wire DQ3_ipd ;
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wire DQ3_ipd ;
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wire DQ2_ipd ;
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wire DQ2_ipd ;
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wire DQ1_ipd ;
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wire DQ1_ipd ;
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wire DQ0_ipd ;
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wire DQ0_ipd ;
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|
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wire [7 : 0 ] DIn;
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wire [7 : 0 ] DIn;
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assign DIn = {DQ7_ipd,
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assign DIn = {DQ7_ipd,
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DQ6_ipd,
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DQ6_ipd,
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DQ5_ipd,
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DQ5_ipd,
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DQ4_ipd,
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DQ4_ipd,
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DQ3_ipd,
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DQ3_ipd,
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DQ2_ipd,
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DQ2_ipd,
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DQ1_ipd,
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DQ1_ipd,
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DQ0_ipd };
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DQ0_ipd };
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wire [7 : 0 ] DOut;
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wire [7 : 0 ] DOut;
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assign DOut = {DQ7,
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assign DOut = {DQ7,
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DQ6,
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DQ6,
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DQ5,
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DQ5,
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DQ4,
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DQ4,
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DQ3,
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DQ3,
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DQ2,
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DQ2,
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DQ1,
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DQ1,
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DQ0 };
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DQ0 };
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wire CENeg_ipd ;
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wire CENeg_ipd ;
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wire OENeg_ipd ;
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wire OENeg_ipd ;
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wire WENeg_ipd ;
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wire WENeg_ipd ;
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wire RESETNeg_ipd ;
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wire RESETNeg_ipd ;
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wire ACC_ipd ;
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wire ACC_ipd ;
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wire VIO_ipd ;
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wire VIO_ipd ;
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// internal delays
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// internal delays
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reg HANG_out ; // Program/Erase Timing Limit
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reg HANG_out ; // Program/Erase Timing Limit
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reg HANG_in ;
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reg HANG_in ;
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reg START_T1 ; // Start TimeOut
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reg START_T1 ; // Start TimeOut
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reg START_T1_in ;
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reg START_T1_in ;
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reg CTMOUT ; // Sector Erase TimeOut
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reg CTMOUT ; // Sector Erase TimeOut
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reg CTMOUT_in ;
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reg CTMOUT_in ;
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reg READY_in ;
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reg READY_in ;
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reg READY ; // Device ready after reset
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reg READY ; // Device ready after reset
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reg [7 : 0] DOut_zd;
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reg [7 : 0] DOut_zd;
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wire DQ7_Pass ;
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wire DQ7_Pass ;
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wire DQ6_Pass ;
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wire DQ6_Pass ;
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wire DQ5_Pass ;
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wire DQ5_Pass ;
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wire DQ4_Pass ;
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wire DQ4_Pass ;
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wire DQ3_Pass ;
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wire DQ3_Pass ;
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wire DQ2_Pass ;
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wire DQ2_Pass ;
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wire DQ1_Pass ;
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wire DQ1_Pass ;
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wire DQ0_Pass ;
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wire DQ0_Pass ;
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reg [7 : 0] DOut_Pass;
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reg [7 : 0] DOut_Pass;
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assign {DQ7_Pass,
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assign {DQ7_Pass,
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DQ6_Pass,
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DQ6_Pass,
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DQ5_Pass,
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DQ5_Pass,
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DQ4_Pass,
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DQ4_Pass,
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DQ3_Pass,
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DQ3_Pass,
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DQ2_Pass,
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DQ2_Pass,
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DQ1_Pass,
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DQ1_Pass,
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DQ0_Pass } = DOut_Pass;
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DQ0_Pass } = DOut_Pass;
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reg RY_zd;
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reg RY_zd;
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parameter UserPreload = 1'b0;
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parameter UserPreload = 1'b0;
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parameter mem_file_name = "none";
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parameter mem_file_name = "none";
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parameter prot_file_name = "none";
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parameter prot_file_name = "none";
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parameter secsi_file_name = "none";
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parameter secsi_file_name = "none";
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parameter TimingModel = "DefaultTimingModel";
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parameter TimingModel = "DefaultTimingModel";
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parameter DelayValues = "FROM_PLI";
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parameter DelayValues = "FROM_PLI";
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parameter PartID = "s29al032d";
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parameter PartID = "s29al032d";
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parameter MaxData = 255;
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parameter MaxData = 255;
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parameter SecSize = 65535;
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parameter SecSize = 65535;
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parameter SecNum = 63;
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parameter SecNum = 63;
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parameter HiAddrBit = 21;
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parameter HiAddrBit = 21;
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parameter SecSiSize = 255;
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parameter SecSiSize = 255;
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// powerup
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// powerup
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reg PoweredUp;
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reg PoweredUp;
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//FSM control signals
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//FSM control signals
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reg ULBYPASS ; ////Unlock Bypass Active
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reg ULBYPASS ; ////Unlock Bypass Active
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reg ESP_ACT ; ////Erase Suspend
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reg ESP_ACT ; ////Erase Suspend
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reg OTP_ACT ; ////SecSi Access
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reg OTP_ACT ; ////SecSi Access
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reg PDONE ; ////Prog. Done
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reg PDONE ; ////Prog. Done
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reg PSTART ; ////Start Programming
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reg PSTART ; ////Start Programming
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//Program location is in protected sector
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//Program location is in protected sector
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reg PERR ;
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reg PERR ;
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reg EDONE ; ////Ers. Done
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reg EDONE ; ////Ers. Done
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reg ESTART ; ////Start Erase
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reg ESTART ; ////Start Erase
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reg ESUSP ; ////Suspend Erase
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reg ESUSP ; ////Suspend Erase
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reg ERES ; ////Resume Erase
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reg ERES ; ////Resume Erase
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//All sectors selected for erasure are protected
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//All sectors selected for erasure are protected
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reg EERR ;
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reg EERR ;
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//Sectors selected for erasure
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//Sectors selected for erasure
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reg [SecNum:0] Ers_queue; // = SecNum'b0;
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reg [SecNum:0] Ers_queue; // = SecNum'b0;
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|
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//Command Register
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//Command Register
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reg write ;
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reg write ;
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reg read ;
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reg read ;
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//Sector Address
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//Sector Address
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integer SecAddr = 0;
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integer SecAddr = 0;
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integer SA = 0;
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integer SA = 0;
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//Address within sector
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//Address within sector
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integer Address = 0;
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integer Address = 0;
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integer MemAddress = 0;
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integer MemAddress = 0;
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integer SecSiAddr = 0;
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integer SecSiAddr = 0;
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|
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integer AS_ID = 0;
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integer AS_ID = 0;
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integer AS_SecSi_FP = 0;
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integer AS_SecSi_FP = 0;
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integer AS_ID2 = 0;
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integer AS_ID2 = 0;
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//A19:A11 Don't Care
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//A19:A11 Don't Care
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integer Addr ;
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integer Addr ;
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|
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//glitch protection
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//glitch protection
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wire gWE_n ;
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wire gWE_n ;
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wire gCE_n ;
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wire gCE_n ;
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wire gOE_n ;
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wire gOE_n ;
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|
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reg RST ;
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reg RST ;
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reg reseted ;
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reg reseted ;
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integer Mem[0:(SecNum+1)*(SecSize+1)-1];
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integer Mem[0:(SecNum+1)*(SecSize+1)-1];
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//Sector Protection Status
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//Sector Protection Status
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reg [SecNum:0] Sec_Prot;
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reg [SecNum:0] Sec_Prot;
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|
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// timing check violation
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// timing check violation
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reg Viol = 1'b0;
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reg Viol = 1'b0;
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// CFI query address
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// CFI query address
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integer SecSi[0:SecSiSize];
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integer SecSi[0:SecSiSize];
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integer CFI_array[16:79];
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integer CFI_array[16:79];
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|
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reg FactoryProt = 0;
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reg FactoryProt = 0;
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|
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integer WBData;
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integer WBData;
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integer WBAddr;
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integer WBAddr;
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|
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reg oe = 1'b0;
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reg oe = 1'b0;
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event oe_event;
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event oe_event;
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|
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event initOK;
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event initOK;
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event MergeE;
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event MergeE;
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|
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//Status reg.
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//Status reg.
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reg[15:0] Status = 8'b0;
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reg[15:0] Status = 8'b0;
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|
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reg[7:0] old_bit, new_bit;
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reg[7:0] old_bit, new_bit;
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integer old_int, new_int;
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integer old_int, new_int;
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integer wr_cnt;
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integer wr_cnt;
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reg[7:0] temp;
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reg[7:0] temp;
|
|
|
integer S_ind = 0;
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integer S_ind = 0;
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integer ind = 0;
|
integer ind = 0;
|
|
|
integer i,j,k;
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integer i,j,k;
|
|
|
integer Debug;
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integer Debug;
|
|
|
//TPD_XX_DATA
|
//TPD_XX_DATA
|
time OEDQ_t;
|
time OEDQ_t;
|
time CEDQ_t;
|
time CEDQ_t;
|
time ADDRDQ_t;
|
time ADDRDQ_t;
|
time OENeg_event;
|
time OENeg_event;
|
time CENeg_event;
|
time CENeg_event;
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time OENeg_posEvent;
|
time OENeg_posEvent;
|
time CENeg_posEvent;
|
time CENeg_posEvent;
|
time ADDR_event;
|
time ADDR_event;
|
reg FROMOE;
|
reg FROMOE;
|
reg FROMCE;
|
reg FROMCE;
|
reg FROMADDR;
|
reg FROMADDR;
|
integer OEDQ_01;
|
integer OEDQ_01;
|
integer CEDQ_01;
|
integer CEDQ_01;
|
integer ADDRDQ_01;
|
integer ADDRDQ_01;
|
|
|
reg[7:0] TempData;
|
reg[7:0] TempData;
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
//Interconnect Path Delay Section
|
//Interconnect Path Delay Section
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
buf (A21_ipd, A21);
|
buf (A21_ipd, A21);
|
buf (A20_ipd, A20);
|
buf (A20_ipd, A20);
|
buf (A19_ipd, A19);
|
buf (A19_ipd, A19);
|
buf (A18_ipd, A18);
|
buf (A18_ipd, A18);
|
buf (A17_ipd, A17);
|
buf (A17_ipd, A17);
|
buf (A16_ipd, A16);
|
buf (A16_ipd, A16);
|
buf (A15_ipd, A15);
|
buf (A15_ipd, A15);
|
buf (A14_ipd, A14);
|
buf (A14_ipd, A14);
|
buf (A13_ipd, A13);
|
buf (A13_ipd, A13);
|
buf (A12_ipd, A12);
|
buf (A12_ipd, A12);
|
buf (A11_ipd, A11);
|
buf (A11_ipd, A11);
|
buf (A10_ipd, A10);
|
buf (A10_ipd, A10);
|
buf (A9_ipd , A9 );
|
buf (A9_ipd , A9 );
|
buf (A8_ipd , A8 );
|
buf (A8_ipd , A8 );
|
buf (A7_ipd , A7 );
|
buf (A7_ipd , A7 );
|
buf (A6_ipd , A6 );
|
buf (A6_ipd , A6 );
|
buf (A5_ipd , A5 );
|
buf (A5_ipd , A5 );
|
buf (A4_ipd , A4 );
|
buf (A4_ipd , A4 );
|
buf (A3_ipd , A3 );
|
buf (A3_ipd , A3 );
|
buf (A2_ipd , A2 );
|
buf (A2_ipd , A2 );
|
buf (A1_ipd , A1 );
|
buf (A1_ipd , A1 );
|
buf (A0_ipd , A0 );
|
buf (A0_ipd , A0 );
|
|
|
buf (DQ7_ipd , DQ7 );
|
buf (DQ7_ipd , DQ7 );
|
buf (DQ6_ipd , DQ6 );
|
buf (DQ6_ipd , DQ6 );
|
buf (DQ5_ipd , DQ5 );
|
buf (DQ5_ipd , DQ5 );
|
buf (DQ4_ipd , DQ4 );
|
buf (DQ4_ipd , DQ4 );
|
buf (DQ3_ipd , DQ3 );
|
buf (DQ3_ipd , DQ3 );
|
buf (DQ2_ipd , DQ2 );
|
buf (DQ2_ipd , DQ2 );
|
buf (DQ1_ipd , DQ1 );
|
buf (DQ1_ipd , DQ1 );
|
buf (DQ0_ipd , DQ0 );
|
buf (DQ0_ipd , DQ0 );
|
|
|
buf (CENeg_ipd , CENeg );
|
buf (CENeg_ipd , CENeg );
|
buf (OENeg_ipd , OENeg );
|
buf (OENeg_ipd , OENeg );
|
buf (WENeg_ipd , WENeg );
|
buf (WENeg_ipd , WENeg );
|
buf (RESETNeg_ipd , RESETNeg );
|
buf (RESETNeg_ipd , RESETNeg );
|
buf (ACC_ipd , ACC );
|
buf (ACC_ipd , ACC );
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Propagation delay Section
|
// Propagation delay Section
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
nmos (DQ7 , DQ7_Pass , 1);
|
nmos (DQ7 , DQ7_Pass , 1);
|
nmos (DQ6 , DQ6_Pass , 1);
|
nmos (DQ6 , DQ6_Pass , 1);
|
nmos (DQ5 , DQ5_Pass , 1);
|
nmos (DQ5 , DQ5_Pass , 1);
|
nmos (DQ4 , DQ4_Pass , 1);
|
nmos (DQ4 , DQ4_Pass , 1);
|
nmos (DQ3 , DQ3_Pass , 1);
|
nmos (DQ3 , DQ3_Pass , 1);
|
nmos (DQ2 , DQ2_Pass , 1);
|
nmos (DQ2 , DQ2_Pass , 1);
|
nmos (DQ1 , DQ1_Pass , 1);
|
nmos (DQ1 , DQ1_Pass , 1);
|
nmos (DQ0 , DQ0_Pass , 1);
|
nmos (DQ0 , DQ0_Pass , 1);
|
nmos (RY , 1'b0 , ~RY_zd);
|
nmos (RY , 1'b0 , ~RY_zd);
|
|
|
wire deg;
|
wire deg;
|
|
|
//VHDL VITAL CheckEnable equivalents
|
//VHDL VITAL CheckEnable equivalents
|
// Address setup/hold near WE# falling edge
|
// Address setup/hold near WE# falling edge
|
wire CheckEnable_A0_WE;
|
wire CheckEnable_A0_WE;
|
assign CheckEnable_A0_WE = ~CENeg && OENeg;
|
assign CheckEnable_A0_WE = ~CENeg && OENeg;
|
// Data setup/hold near WE# rising edge
|
// Data setup/hold near WE# rising edge
|
wire CheckEnable_DQ0_WE;
|
wire CheckEnable_DQ0_WE;
|
assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
|
assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
|
// Address setup/hold near CE# falling edge
|
// Address setup/hold near CE# falling edge
|
wire CheckEnable_A0_CE;
|
wire CheckEnable_A0_CE;
|
assign CheckEnable_A0_CE = ~WENeg && OENeg;
|
assign CheckEnable_A0_CE = ~WENeg && OENeg;
|
// Data setup/hold near CE# rising edge
|
// Data setup/hold near CE# rising edge
|
wire CheckEnable_DQ0_CE;
|
wire CheckEnable_DQ0_CE;
|
assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
|
assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
|
|
|
specify
|
specify
|
|
|
// tipd delays: interconnect path delays , mapped to input port delays.
|
// tipd delays: interconnect path delays , mapped to input port delays.
|
// In Verilog is not necessary to declare any tipd_ delay variables,
|
// In Verilog is not necessary to declare any tipd_ delay variables,
|
// they can be taken from SDF file
|
// they can be taken from SDF file
|
// With all the other delays real delays would be taken from SDF file
|
// With all the other delays real delays would be taken from SDF file
|
|
|
// tpd delays
|
// tpd delays
|
specparam tpd_RESETNeg_DQ0 =1;
|
specparam tpd_RESETNeg_DQ0 =1;
|
specparam tpd_A0_DQ0 =1;//tacc ok
|
specparam tpd_A0_DQ0 =1;//tacc ok
|
specparam tpd_CENeg_DQ0 =1;//ok
|
specparam tpd_CENeg_DQ0 =1;//ok
|
//(tCE,tCE,tDF,-,tDF,-)
|
//(tCE,tCE,tDF,-,tDF,-)
|
specparam tpd_OENeg_DQ0 =1;//ok
|
specparam tpd_OENeg_DQ0 =1;//ok
|
//(tOE,tOE,tDF,-,tDF,-)
|
//(tOE,tOE,tDF,-,tDF,-)
|
specparam tpd_WENeg_RY =1; //tBUSY
|
specparam tpd_WENeg_RY =1; //tBUSY
|
specparam tpd_CENeg_RY =1; //tBUSY
|
specparam tpd_CENeg_RY =1; //tBUSY
|
|
|
// tsetup values: setup time
|
// tsetup values: setup time
|
specparam tsetup_A0_WENeg =1; //tAS edge \
|
specparam tsetup_A0_WENeg =1; //tAS edge \
|
specparam tsetup_DQ0_WENeg =1; //tDS edge /
|
specparam tsetup_DQ0_WENeg =1; //tDS edge /
|
|
|
// thold values: hold times
|
// thold values: hold times
|
specparam thold_A0_WENeg =1; //tAH edge \
|
specparam thold_A0_WENeg =1; //tAH edge \
|
specparam thold_DQ0_CENeg =1; //tDH edge /
|
specparam thold_DQ0_CENeg =1; //tDH edge /
|
specparam thold_OENeg_WENeg =1; //tOEH edge /
|
specparam thold_OENeg_WENeg =1; //tOEH edge /
|
specparam thold_CENeg_RESETNeg =1; //tRH edge /
|
specparam thold_CENeg_RESETNeg =1; //tRH edge /
|
specparam thold_WENeg_OENeg =1; //tGHVL edge /
|
specparam thold_WENeg_OENeg =1; //tGHVL edge /
|
|
|
// tpw values: pulse width
|
// tpw values: pulse width
|
specparam tpw_RESETNeg_negedge =1; //tRP
|
specparam tpw_RESETNeg_negedge =1; //tRP
|
specparam tpw_WENeg_negedge =1; //tWP
|
specparam tpw_WENeg_negedge =1; //tWP
|
specparam tpw_WENeg_posedge =1; //tWPH
|
specparam tpw_WENeg_posedge =1; //tWPH
|
specparam tpw_CENeg_negedge =1; //tCP
|
specparam tpw_CENeg_negedge =1; //tCP
|
specparam tpw_CENeg_posedge =1; //tCEPH
|
specparam tpw_CENeg_posedge =1; //tCEPH
|
specparam tpw_A0_negedge =1; //tWC tRC ok
|
specparam tpw_A0_negedge =1; //tWC tRC ok
|
specparam tpw_A0_posedge =1; //tWC tRC ok
|
specparam tpw_A0_posedge =1; //tWC tRC ok
|
|
|
// tdevice values: values for internal delays
|
// tdevice values: values for internal delays
|
//Program Operation
|
//Program Operation
|
specparam tdevice_POB = 9000; //9 us;
|
specparam tdevice_POB = 9000; //9 us;
|
//Sector Erase Operation
|
//Sector Erase Operation
|
specparam tdevice_SEO = 700000000; //700 ms;
|
specparam tdevice_SEO = 700000000; //700 ms;
|
//Timing Limit Exceeded
|
//Timing Limit Exceeded
|
specparam tdevice_HANG = 400000000; //400 ms;
|
specparam tdevice_HANG = 400000000; //400 ms;
|
//Erase suspend time
|
//Erase suspend time
|
specparam tdevice_START_T1 = 20000; //20 us;
|
specparam tdevice_START_T1 = 20000; //20 us;
|
//sector erase command sequence timeout
|
//sector erase command sequence timeout
|
specparam tdevice_CTMOUT = 50000; //50 us;
|
specparam tdevice_CTMOUT = 50000; //50 us;
|
//device ready after Hardware reset(during embeded algorithm)
|
//device ready after Hardware reset(during embeded algorithm)
|
specparam tdevice_READY = 20000; //20 us; //tReady
|
specparam tdevice_READY = 20000; //20 us; //tReady
|
|
|
// If tpd values are fetched from specify block, these parameters
|
// If tpd values are fetched from specify block, these parameters
|
// must change along with SDF values, SDF values change will NOT
|
// must change along with SDF values, SDF values change will NOT
|
// imlicitly apply here !
|
// imlicitly apply here !
|
// If you want tpd values to be fetched by the model itself, please
|
// If you want tpd values to be fetched by the model itself, please
|
// use the PLI routine approach but be shure to set parameter
|
// use the PLI routine approach but be shure to set parameter
|
// DelayValues to "FROM_PLI" as default
|
// DelayValues to "FROM_PLI" as default
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Input Port Delays don't require Verilog description
|
// Input Port Delays don't require Verilog description
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
// Path delays //
|
// Path delays //
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
//for DQ signals
|
//for DQ signals
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ0 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ0 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ1 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ1 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ2 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ2 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ3 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ3 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ4 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ4 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ5 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ5 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ6 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ6 ) = tpd_CENeg_DQ0;
|
if (FROMCE)
|
if (FROMCE)
|
( CENeg => DQ7 ) = tpd_CENeg_DQ0;
|
( CENeg => DQ7 ) = tpd_CENeg_DQ0;
|
|
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ0 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ0 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ1 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ1 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ2 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ2 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ3 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ3 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ4 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ4 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ5 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ5 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ6 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ6 ) = tpd_OENeg_DQ0;
|
if (FROMOE)
|
if (FROMOE)
|
( OENeg => DQ7 ) = tpd_OENeg_DQ0;
|
( OENeg => DQ7 ) = tpd_OENeg_DQ0;
|
|
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ0 ) = tpd_A0_DQ0;
|
( A0 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ1 ) = tpd_A0_DQ0;
|
( A0 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ2 ) = tpd_A0_DQ0;
|
( A0 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ3 ) = tpd_A0_DQ0;
|
( A0 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ4 ) = tpd_A0_DQ0;
|
( A0 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ5 ) = tpd_A0_DQ0;
|
( A0 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ6 ) = tpd_A0_DQ0;
|
( A0 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A0 => DQ7 ) = tpd_A0_DQ0;
|
( A0 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ0 ) = tpd_A0_DQ0;
|
( A1 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ1 ) = tpd_A0_DQ0;
|
( A1 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ2 ) = tpd_A0_DQ0;
|
( A1 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ3 ) = tpd_A0_DQ0;
|
( A1 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ4 ) = tpd_A0_DQ0;
|
( A1 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ5 ) = tpd_A0_DQ0;
|
( A1 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ6 ) = tpd_A0_DQ0;
|
( A1 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A1 => DQ7 ) = tpd_A0_DQ0;
|
( A1 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ0 ) = tpd_A0_DQ0;
|
( A2 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ1 ) = tpd_A0_DQ0;
|
( A2 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ2 ) = tpd_A0_DQ0;
|
( A2 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ3 ) = tpd_A0_DQ0;
|
( A2 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ4 ) = tpd_A0_DQ0;
|
( A2 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ5 ) = tpd_A0_DQ0;
|
( A2 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ6 ) = tpd_A0_DQ0;
|
( A2 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A2 => DQ7 ) = tpd_A0_DQ0;
|
( A2 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ0 ) = tpd_A0_DQ0;
|
( A3 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ1 ) = tpd_A0_DQ0;
|
( A3 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ2 ) = tpd_A0_DQ0;
|
( A3 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ3 ) = tpd_A0_DQ0;
|
( A3 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ4 ) = tpd_A0_DQ0;
|
( A3 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ5 ) = tpd_A0_DQ0;
|
( A3 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ6 ) = tpd_A0_DQ0;
|
( A3 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A3 => DQ7 ) = tpd_A0_DQ0;
|
( A3 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ0 ) = tpd_A0_DQ0;
|
( A4 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ1 ) = tpd_A0_DQ0;
|
( A4 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ2 ) = tpd_A0_DQ0;
|
( A4 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ3 ) = tpd_A0_DQ0;
|
( A4 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ4 ) = tpd_A0_DQ0;
|
( A4 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ5 ) = tpd_A0_DQ0;
|
( A4 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ6 ) = tpd_A0_DQ0;
|
( A4 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A4 => DQ7 ) = tpd_A0_DQ0;
|
( A4 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ0 ) = tpd_A0_DQ0;
|
( A5 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ1 ) = tpd_A0_DQ0;
|
( A5 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ2 ) = tpd_A0_DQ0;
|
( A5 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ3 ) = tpd_A0_DQ0;
|
( A5 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ4 ) = tpd_A0_DQ0;
|
( A5 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ5 ) = tpd_A0_DQ0;
|
( A5 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ6 ) = tpd_A0_DQ0;
|
( A5 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A5 => DQ7 ) = tpd_A0_DQ0;
|
( A5 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ0 ) = tpd_A0_DQ0;
|
( A6 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ1 ) = tpd_A0_DQ0;
|
( A6 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ2 ) = tpd_A0_DQ0;
|
( A6 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ3 ) = tpd_A0_DQ0;
|
( A6 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ4 ) = tpd_A0_DQ0;
|
( A6 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ5 ) = tpd_A0_DQ0;
|
( A6 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ6 ) = tpd_A0_DQ0;
|
( A6 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A6 => DQ7 ) = tpd_A0_DQ0;
|
( A6 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ0 ) = tpd_A0_DQ0;
|
( A7 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ1 ) = tpd_A0_DQ0;
|
( A7 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ2 ) = tpd_A0_DQ0;
|
( A7 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ3 ) = tpd_A0_DQ0;
|
( A7 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ4 ) = tpd_A0_DQ0;
|
( A7 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ5 ) = tpd_A0_DQ0;
|
( A7 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ6 ) = tpd_A0_DQ0;
|
( A7 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A7 => DQ7 ) = tpd_A0_DQ0;
|
( A7 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ0 ) = tpd_A0_DQ0;
|
( A8 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ1 ) = tpd_A0_DQ0;
|
( A8 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ2 ) = tpd_A0_DQ0;
|
( A8 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ3 ) = tpd_A0_DQ0;
|
( A8 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ4 ) = tpd_A0_DQ0;
|
( A8 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ5 ) = tpd_A0_DQ0;
|
( A8 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ6 ) = tpd_A0_DQ0;
|
( A8 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A8 => DQ7 ) = tpd_A0_DQ0;
|
( A8 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ0 ) = tpd_A0_DQ0;
|
( A9 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ1 ) = tpd_A0_DQ0;
|
( A9 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ2 ) = tpd_A0_DQ0;
|
( A9 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ3 ) = tpd_A0_DQ0;
|
( A9 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ4 ) = tpd_A0_DQ0;
|
( A9 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ5 ) = tpd_A0_DQ0;
|
( A9 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ6 ) = tpd_A0_DQ0;
|
( A9 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A9 => DQ7 ) = tpd_A0_DQ0;
|
( A9 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ0 ) = tpd_A0_DQ0;
|
( A10 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ1 ) = tpd_A0_DQ0;
|
( A10 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ2 ) = tpd_A0_DQ0;
|
( A10 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ3 ) = tpd_A0_DQ0;
|
( A10 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ4 ) = tpd_A0_DQ0;
|
( A10 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ5 ) = tpd_A0_DQ0;
|
( A10 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ6 ) = tpd_A0_DQ0;
|
( A10 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A10 => DQ7 ) = tpd_A0_DQ0;
|
( A10 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ0 ) = tpd_A0_DQ0;
|
( A11 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ1 ) = tpd_A0_DQ0;
|
( A11 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ2 ) = tpd_A0_DQ0;
|
( A11 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ3 ) = tpd_A0_DQ0;
|
( A11 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ4 ) = tpd_A0_DQ0;
|
( A11 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ5 ) = tpd_A0_DQ0;
|
( A11 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ6 ) = tpd_A0_DQ0;
|
( A11 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A11 => DQ7 ) = tpd_A0_DQ0;
|
( A11 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ0 ) = tpd_A0_DQ0;
|
( A12 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ1 ) = tpd_A0_DQ0;
|
( A12 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ2 ) = tpd_A0_DQ0;
|
( A12 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ3 ) = tpd_A0_DQ0;
|
( A12 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ4 ) = tpd_A0_DQ0;
|
( A12 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ5 ) = tpd_A0_DQ0;
|
( A12 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ6 ) = tpd_A0_DQ0;
|
( A12 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A12 => DQ7 ) = tpd_A0_DQ0;
|
( A12 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ0 ) = tpd_A0_DQ0;
|
( A13 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ1 ) = tpd_A0_DQ0;
|
( A13 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ2 ) = tpd_A0_DQ0;
|
( A13 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ3 ) = tpd_A0_DQ0;
|
( A13 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ4 ) = tpd_A0_DQ0;
|
( A13 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ5 ) = tpd_A0_DQ0;
|
( A13 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ6 ) = tpd_A0_DQ0;
|
( A13 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A13 => DQ7 ) = tpd_A0_DQ0;
|
( A13 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ0 ) = tpd_A0_DQ0;
|
( A14 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ1 ) = tpd_A0_DQ0;
|
( A14 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ2 ) = tpd_A0_DQ0;
|
( A14 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ3 ) = tpd_A0_DQ0;
|
( A14 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ4 ) = tpd_A0_DQ0;
|
( A14 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ5 ) = tpd_A0_DQ0;
|
( A14 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ6 ) = tpd_A0_DQ0;
|
( A14 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A14 => DQ7 ) = tpd_A0_DQ0;
|
( A14 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ0 ) = tpd_A0_DQ0;
|
( A15 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ1 ) = tpd_A0_DQ0;
|
( A15 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ2 ) = tpd_A0_DQ0;
|
( A15 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ3 ) = tpd_A0_DQ0;
|
( A15 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ4 ) = tpd_A0_DQ0;
|
( A15 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ5 ) = tpd_A0_DQ0;
|
( A15 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ6 ) = tpd_A0_DQ0;
|
( A15 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A15 => DQ7 ) = tpd_A0_DQ0;
|
( A15 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ0 ) = tpd_A0_DQ0;
|
( A16 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ1 ) = tpd_A0_DQ0;
|
( A16 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ2 ) = tpd_A0_DQ0;
|
( A16 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ3 ) = tpd_A0_DQ0;
|
( A16 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ4 ) = tpd_A0_DQ0;
|
( A16 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ5 ) = tpd_A0_DQ0;
|
( A16 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ6 ) = tpd_A0_DQ0;
|
( A16 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A16 => DQ7 ) = tpd_A0_DQ0;
|
( A16 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ0 ) = tpd_A0_DQ0;
|
( A17 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ1 ) = tpd_A0_DQ0;
|
( A17 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ2 ) = tpd_A0_DQ0;
|
( A17 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ3 ) = tpd_A0_DQ0;
|
( A17 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ4 ) = tpd_A0_DQ0;
|
( A17 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ5 ) = tpd_A0_DQ0;
|
( A17 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ6 ) = tpd_A0_DQ0;
|
( A17 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A17 => DQ7 ) = tpd_A0_DQ0;
|
( A17 => DQ7 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ0 ) = tpd_A0_DQ0;
|
( A18 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ1 ) = tpd_A0_DQ0;
|
( A18 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ2 ) = tpd_A0_DQ0;
|
( A18 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ3 ) = tpd_A0_DQ0;
|
( A18 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ4 ) = tpd_A0_DQ0;
|
( A18 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ5 ) = tpd_A0_DQ0;
|
( A18 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ6 ) = tpd_A0_DQ0;
|
( A18 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A18 => DQ7 ) = tpd_A0_DQ0;
|
( A18 => DQ7 ) = tpd_A0_DQ0;
|
|
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ0 ) = tpd_A0_DQ0;
|
( A19 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ1 ) = tpd_A0_DQ0;
|
( A19 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ2 ) = tpd_A0_DQ0;
|
( A19 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ3 ) = tpd_A0_DQ0;
|
( A19 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ4 ) = tpd_A0_DQ0;
|
( A19 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ5 ) = tpd_A0_DQ0;
|
( A19 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ6 ) = tpd_A0_DQ0;
|
( A19 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A19 => DQ7 ) = tpd_A0_DQ0;
|
( A19 => DQ7 ) = tpd_A0_DQ0;
|
|
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ0 ) = tpd_A0_DQ0;
|
( A20 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ1 ) = tpd_A0_DQ0;
|
( A20 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ2 ) = tpd_A0_DQ0;
|
( A20 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ3 ) = tpd_A0_DQ0;
|
( A20 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ4 ) = tpd_A0_DQ0;
|
( A20 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ5 ) = tpd_A0_DQ0;
|
( A20 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ6 ) = tpd_A0_DQ0;
|
( A20 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A20 => DQ7 ) = tpd_A0_DQ0;
|
( A20 => DQ7 ) = tpd_A0_DQ0;
|
|
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ0 ) = tpd_A0_DQ0;
|
( A21 => DQ0 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ1 ) = tpd_A0_DQ0;
|
( A21 => DQ1 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ2 ) = tpd_A0_DQ0;
|
( A21 => DQ2 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ3 ) = tpd_A0_DQ0;
|
( A21 => DQ3 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ4 ) = tpd_A0_DQ0;
|
( A21 => DQ4 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ5 ) = tpd_A0_DQ0;
|
( A21 => DQ5 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ6 ) = tpd_A0_DQ0;
|
( A21 => DQ6 ) = tpd_A0_DQ0;
|
if (FROMADDR)
|
if (FROMADDR)
|
( A21 => DQ7 ) = tpd_A0_DQ0;
|
( A21 => DQ7 ) = tpd_A0_DQ0;
|
|
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
|
if (~RESETNeg)
|
if (~RESETNeg)
|
( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
|
( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
|
|
|
//for RY signal
|
//for RY signal
|
(WENeg => RY) = tpd_WENeg_RY;
|
(WENeg => RY) = tpd_WENeg_RY;
|
(CENeg => RY) = tpd_CENeg_RY;
|
(CENeg => RY) = tpd_CENeg_RY;
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// Timing Violation //
|
// Timing Violation //
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
$setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
$setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
|
|
|
$setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
$setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
|
|
|
$setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
|
|
|
$setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
$setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
|
|
|
$hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol);
|
$hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol);
|
$hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol);
|
$hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol);
|
$hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol);
|
$hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol);
|
$hold ( posedge OENeg, WENeg, thold_WENeg_OENeg, Viol);
|
$hold ( posedge OENeg, WENeg, thold_WENeg_OENeg, Viol);
|
$hold ( posedge WENeg, OENeg, thold_OENeg_WENeg, Viol);
|
$hold ( posedge WENeg, OENeg, thold_OENeg_WENeg, Viol);
|
|
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol);
|
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol);
|
|
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol);
|
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol);
|
|
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol);
|
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol);
|
|
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_CENeg, Viol);
|
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_CENeg, Viol);
|
|
|
$width (negedge RESETNeg, tpw_RESETNeg_negedge);
|
$width (negedge RESETNeg, tpw_RESETNeg_negedge);
|
$width (posedge WENeg, tpw_WENeg_posedge);
|
$width (posedge WENeg, tpw_WENeg_posedge);
|
$width (negedge WENeg, tpw_WENeg_negedge);
|
$width (negedge WENeg, tpw_WENeg_negedge);
|
$width (posedge CENeg, tpw_CENeg_posedge);
|
$width (posedge CENeg, tpw_CENeg_posedge);
|
$width (negedge CENeg, tpw_CENeg_negedge);
|
$width (negedge CENeg, tpw_CENeg_negedge);
|
$width (negedge A0, tpw_A0_negedge);//ok
|
$width (negedge A0, tpw_A0_negedge);//ok
|
$width (negedge A1, tpw_A0_negedge);//ok
|
$width (negedge A1, tpw_A0_negedge);//ok
|
$width (negedge A2, tpw_A0_negedge);//ok
|
$width (negedge A2, tpw_A0_negedge);//ok
|
$width (negedge A3, tpw_A0_negedge);//ok
|
$width (negedge A3, tpw_A0_negedge);//ok
|
$width (negedge A4, tpw_A0_negedge);//ok
|
$width (negedge A4, tpw_A0_negedge);//ok
|
$width (negedge A5, tpw_A0_negedge);//ok
|
$width (negedge A5, tpw_A0_negedge);//ok
|
$width (negedge A6, tpw_A0_negedge);//ok
|
$width (negedge A6, tpw_A0_negedge);//ok
|
$width (negedge A7, tpw_A0_negedge);//ok
|
$width (negedge A7, tpw_A0_negedge);//ok
|
$width (negedge A8, tpw_A0_negedge);//ok
|
$width (negedge A8, tpw_A0_negedge);//ok
|
$width (negedge A9, tpw_A0_negedge);//ok
|
$width (negedge A9, tpw_A0_negedge);//ok
|
$width (negedge A10, tpw_A0_negedge);//ok
|
$width (negedge A10, tpw_A0_negedge);//ok
|
$width (negedge A11, tpw_A0_negedge);//ok
|
$width (negedge A11, tpw_A0_negedge);//ok
|
$width (negedge A12, tpw_A0_negedge);//ok
|
$width (negedge A12, tpw_A0_negedge);//ok
|
$width (negedge A13, tpw_A0_negedge);//ok
|
$width (negedge A13, tpw_A0_negedge);//ok
|
$width (negedge A14, tpw_A0_negedge);//ok
|
$width (negedge A14, tpw_A0_negedge);//ok
|
$width (negedge A15, tpw_A0_negedge);//ok
|
$width (negedge A15, tpw_A0_negedge);//ok
|
$width (negedge A16, tpw_A0_negedge);//ok
|
$width (negedge A16, tpw_A0_negedge);//ok
|
$width (negedge A17, tpw_A0_negedge);//ok
|
$width (negedge A17, tpw_A0_negedge);//ok
|
$width (negedge A18, tpw_A0_negedge);//ok
|
$width (negedge A18, tpw_A0_negedge);//ok
|
$width (negedge A19, tpw_A0_negedge);//ok
|
$width (negedge A19, tpw_A0_negedge);//ok
|
$width (negedge A20, tpw_A0_negedge);//ok
|
$width (negedge A20, tpw_A0_negedge);//ok
|
$width (negedge A21, tpw_A0_negedge);//ok
|
$width (negedge A21, tpw_A0_negedge);//ok
|
$width (posedge A0, tpw_A0_posedge);//ok
|
$width (posedge A0, tpw_A0_posedge);//ok
|
$width (posedge A1, tpw_A0_posedge);//ok
|
$width (posedge A1, tpw_A0_posedge);//ok
|
$width (posedge A2, tpw_A0_posedge);//ok
|
$width (posedge A2, tpw_A0_posedge);//ok
|
$width (posedge A3, tpw_A0_posedge);//ok
|
$width (posedge A3, tpw_A0_posedge);//ok
|
$width (posedge A4, tpw_A0_posedge);//ok
|
$width (posedge A4, tpw_A0_posedge);//ok
|
$width (posedge A5, tpw_A0_posedge);//ok
|
$width (posedge A5, tpw_A0_posedge);//ok
|
$width (posedge A6, tpw_A0_posedge);//ok
|
$width (posedge A6, tpw_A0_posedge);//ok
|
$width (posedge A7, tpw_A0_posedge);//ok
|
$width (posedge A7, tpw_A0_posedge);//ok
|
$width (posedge A8, tpw_A0_posedge);//ok
|
$width (posedge A8, tpw_A0_posedge);//ok
|
$width (posedge A9, tpw_A0_posedge);//ok
|
$width (posedge A9, tpw_A0_posedge);//ok
|
$width (posedge A10, tpw_A0_posedge);//ok
|
$width (posedge A10, tpw_A0_posedge);//ok
|
$width (posedge A11, tpw_A0_posedge);//ok
|
$width (posedge A11, tpw_A0_posedge);//ok
|
$width (posedge A12, tpw_A0_posedge);//ok
|
$width (posedge A12, tpw_A0_posedge);//ok
|
$width (posedge A13, tpw_A0_posedge);//ok
|
$width (posedge A13, tpw_A0_posedge);//ok
|
$width (posedge A14, tpw_A0_posedge);//ok
|
$width (posedge A14, tpw_A0_posedge);//ok
|
$width (posedge A15, tpw_A0_posedge);//ok
|
$width (posedge A15, tpw_A0_posedge);//ok
|
$width (posedge A16, tpw_A0_posedge);//ok
|
$width (posedge A16, tpw_A0_posedge);//ok
|
$width (posedge A17, tpw_A0_posedge);//ok
|
$width (posedge A17, tpw_A0_posedge);//ok
|
$width (posedge A18, tpw_A0_posedge);//ok
|
$width (posedge A18, tpw_A0_posedge);//ok
|
$width (posedge A19, tpw_A0_posedge);//ok
|
$width (posedge A19, tpw_A0_posedge);//ok
|
$width (posedge A20, tpw_A0_posedge);//ok
|
$width (posedge A20, tpw_A0_posedge);//ok
|
$width (posedge A21, tpw_A0_posedge);//ok
|
$width (posedge A21, tpw_A0_posedge);//ok
|
|
|
endspecify
|
endspecify
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// Main Behavior Block //
|
// Main Behavior Block //
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
// FSM states
|
// FSM states
|
parameter RESET =6'd0;
|
parameter RESET =6'd0;
|
parameter Z001 =6'd1;
|
parameter Z001 =6'd1;
|
parameter PREL_SETBWB =6'd2;
|
parameter PREL_SETBWB =6'd2;
|
parameter PREL_ULBYPASS =6'd3;
|
parameter PREL_ULBYPASS =6'd3;
|
parameter PREL_ULBYPASS_RESET =6'd4;
|
parameter PREL_ULBYPASS_RESET =6'd4;
|
parameter AS =6'd5;
|
parameter AS =6'd5;
|
parameter A0SEEN =6'd6;
|
parameter A0SEEN =6'd6;
|
parameter OTP =6'd7;
|
parameter OTP =6'd7;
|
parameter OTP_Z001 =6'd8;
|
parameter OTP_Z001 =6'd8;
|
parameter OTP_PREL =6'd9;
|
parameter OTP_PREL =6'd9;
|
parameter OTP_AS =6'd10;
|
parameter OTP_AS =6'd10;
|
parameter OTP_AS_CFI =6'd11;
|
parameter OTP_AS_CFI =6'd11;
|
parameter OTP_A0SEEN =6'd12;
|
parameter OTP_A0SEEN =6'd12;
|
parameter C8 =6'd13;
|
parameter C8 =6'd13;
|
parameter C8_Z001 =6'd14;
|
parameter C8_Z001 =6'd14;
|
parameter C8_PREL =6'd15;
|
parameter C8_PREL =6'd15;
|
parameter ERS =6'd16;
|
parameter ERS =6'd16;
|
parameter SERS =6'd17;
|
parameter SERS =6'd17;
|
parameter ESPS =6'd18;
|
parameter ESPS =6'd18;
|
parameter SERS_EXEC =6'd19;
|
parameter SERS_EXEC =6'd19;
|
parameter ESP =6'd20;
|
parameter ESP =6'd20;
|
parameter ESP_Z001 =6'd21;
|
parameter ESP_Z001 =6'd21;
|
parameter ESP_PREL =6'd22;
|
parameter ESP_PREL =6'd22;
|
parameter ESP_A0SEEN =6'd23;
|
parameter ESP_A0SEEN =6'd23;
|
parameter ESP_AS =6'd24;
|
parameter ESP_AS =6'd24;
|
parameter PGMS =6'd25;
|
parameter PGMS =6'd25;
|
parameter CFI =6'd26;
|
parameter CFI =6'd26;
|
parameter AS_CFI =6'd27;
|
parameter AS_CFI =6'd27;
|
parameter ESP_CFI =6'd28;
|
parameter ESP_CFI =6'd28;
|
parameter ESP_AS_CFI =6'd29;
|
parameter ESP_AS_CFI =6'd29;
|
|
|
reg [5:0] current_state;
|
reg [5:0] current_state;
|
reg [5:0] next_state;
|
reg [5:0] next_state;
|
|
|
reg deq;
|
reg deq;
|
|
|
always @(DIn, DOut)
|
always @(DIn, DOut)
|
begin
|
begin
|
if (DIn==DOut)
|
if (DIn==DOut)
|
deq=1'b1;
|
deq=1'b1;
|
else
|
else
|
deq=1'b0;
|
deq=1'b0;
|
end
|
end
|
// check when data is generated from model to avoid setuphold check in
|
// check when data is generated from model to avoid setuphold check in
|
// those occasion
|
// those occasion
|
assign deg =deq;
|
assign deg =deq;
|
|
|
// initialize memory and load preoload files if any
|
// initialize memory and load preoload files if any
|
initial
|
initial
|
begin : NBlck
|
begin : NBlck
|
integer i,j;
|
integer i,j;
|
integer tmp1,tmp2,tmp3;
|
integer tmp1,tmp2,tmp3;
|
integer secure_silicon[0:SecSiSize];
|
integer secure_silicon[0:SecSiSize];
|
reg sector_prot[0:SecNum];
|
reg sector_prot[0:SecNum];
|
|
|
for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
|
for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
|
begin
|
begin
|
Mem[i]=MaxData;
|
Mem[i]=MaxData;
|
end
|
end
|
for (i=0;i<=SecSiSize;i=i+1)
|
for (i=0;i<=SecSiSize;i=i+1)
|
begin
|
begin
|
secure_silicon[i]=MaxData;
|
secure_silicon[i]=MaxData;
|
end
|
end
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
begin
|
begin
|
sector_prot[i]=0;
|
sector_prot[i]=0;
|
end
|
end
|
if (UserPreload && !(prot_file_name == "none"))
|
if (UserPreload && !(prot_file_name == "none"))
|
begin
|
begin
|
//s29al032d_00_prot sector protect file
|
//s29al032d_00_prot sector protect file
|
// // - comment
|
// // - comment
|
// @aa - <aa> stands for sector address
|
// @aa - <aa> stands for sector address
|
// (aa is incremented at every load)
|
// (aa is incremented at every load)
|
// b - <b> is 1 for protected sector <aa>, 0 for unprotect.
|
// b - <b> is 1 for protected sector <aa>, 0 for unprotect.
|
$readmemb(prot_file_name,sector_prot);
|
$readmemb(prot_file_name,sector_prot);
|
end
|
end
|
if (UserPreload && !(mem_file_name == "none"))
|
if (UserPreload && !(mem_file_name == "none"))
|
begin
|
begin
|
//s29al032d_00_memory preload file
|
//s29al032d_00_memory preload file
|
// @aaaaaa - <aaaaaa> stands for address within last defined sector
|
// @aaaaaa - <aaaaaa> stands for address within last defined sector
|
// dd - <dd> is byte to be written at Mem(nn)(aaaaaa++)
|
// dd - <dd> is byte to be written at Mem(nn)(aaaaaa++)
|
// (aaaaaa is incremented at every load)
|
// (aaaaaa is incremented at every load)
|
$readmemh(mem_file_name,Mem);
|
$readmemh(mem_file_name,Mem);
|
end
|
end
|
if (UserPreload && !(secsi_file_name == "none"))
|
if (UserPreload && !(secsi_file_name == "none"))
|
begin
|
begin
|
//s29al032d_00_secsi memory preload file
|
//s29al032d_00_secsi memory preload file
|
// @aaaa - <aaaa> stands for address within last defined sector
|
// @aaaa - <aaaa> stands for address within last defined sector
|
// dd - <dd> is byte to be written at Mem(nn)(aaaa++)
|
// dd - <dd> is byte to be written at Mem(nn)(aaaa++)
|
// (aaaa is incremented at every load)
|
// (aaaa is incremented at every load)
|
$readmemh(secsi_file_name,secure_silicon);
|
$readmemh(secsi_file_name,secure_silicon);
|
end
|
end
|
|
|
for (i=0;i<=SecSiSize;i=i+1)
|
for (i=0;i<=SecSiSize;i=i+1)
|
begin
|
begin
|
SecSi[i] = secure_silicon[i];
|
SecSi[i] = secure_silicon[i];
|
end
|
end
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
Ers_queue[i] = 0;
|
Ers_queue[i] = 0;
|
// every 4-group sectors protect bit must equel
|
// every 4-group sectors protect bit must equel
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
Sec_Prot[i] = sector_prot[i];
|
Sec_Prot[i] = sector_prot[i];
|
|
|
if ((Sec_Prot[3:0] != 4'h0 && Sec_Prot[3:0] != 4'hF)
|
if ((Sec_Prot[3:0] != 4'h0 && Sec_Prot[3:0] != 4'hF)
|
|| (Sec_Prot[7:4] != 4'h0 && Sec_Prot[7:4] != 4'hF)
|
|| (Sec_Prot[7:4] != 4'h0 && Sec_Prot[7:4] != 4'hF)
|
|| (Sec_Prot[11:8] != 4'h0 && Sec_Prot[11:8] != 4'hF)
|
|| (Sec_Prot[11:8] != 4'h0 && Sec_Prot[11:8] != 4'hF)
|
|| (Sec_Prot[15:12] != 4'h0 && Sec_Prot[15:12] != 4'hF)
|
|| (Sec_Prot[15:12] != 4'h0 && Sec_Prot[15:12] != 4'hF)
|
|| (Sec_Prot[19:16] != 4'h0 && Sec_Prot[19:16] != 4'hF)
|
|| (Sec_Prot[19:16] != 4'h0 && Sec_Prot[19:16] != 4'hF)
|
|| (Sec_Prot[23:20] != 4'h0 && Sec_Prot[23:20] != 4'hF)
|
|| (Sec_Prot[23:20] != 4'h0 && Sec_Prot[23:20] != 4'hF)
|
|| (Sec_Prot[27:24] != 4'h0 && Sec_Prot[27:24] != 4'hF)
|
|| (Sec_Prot[27:24] != 4'h0 && Sec_Prot[27:24] != 4'hF)
|
|| (Sec_Prot[31:28] != 4'h0 && Sec_Prot[31:28] != 4'hF)
|
|| (Sec_Prot[31:28] != 4'h0 && Sec_Prot[31:28] != 4'hF)
|
|| (Sec_Prot[35:32] != 4'h0 && Sec_Prot[35:32] != 4'hF)
|
|| (Sec_Prot[35:32] != 4'h0 && Sec_Prot[35:32] != 4'hF)
|
|| (Sec_Prot[39:36] != 4'h0 && Sec_Prot[39:36] != 4'hF)
|
|| (Sec_Prot[39:36] != 4'h0 && Sec_Prot[39:36] != 4'hF)
|
|| (Sec_Prot[43:40] != 4'h0 && Sec_Prot[43:40] != 4'hF)
|
|| (Sec_Prot[43:40] != 4'h0 && Sec_Prot[43:40] != 4'hF)
|
|| (Sec_Prot[47:44] != 4'h0 && Sec_Prot[47:44] != 4'hF)
|
|| (Sec_Prot[47:44] != 4'h0 && Sec_Prot[47:44] != 4'hF)
|
|| (Sec_Prot[51:48] != 4'h0 && Sec_Prot[51:48] != 4'hF)
|
|| (Sec_Prot[51:48] != 4'h0 && Sec_Prot[51:48] != 4'hF)
|
|| (Sec_Prot[55:52] != 4'h0 && Sec_Prot[55:52] != 4'hF)
|
|| (Sec_Prot[55:52] != 4'h0 && Sec_Prot[55:52] != 4'hF)
|
|| (Sec_Prot[59:56] != 4'h0 && Sec_Prot[59:56] != 4'hF)
|
|| (Sec_Prot[59:56] != 4'h0 && Sec_Prot[59:56] != 4'hF)
|
|| (Sec_Prot[63:60] != 4'h0 && Sec_Prot[63:60] != 4'hF))
|
|| (Sec_Prot[63:60] != 4'h0 && Sec_Prot[63:60] != 4'hF))
|
|
|
$display("Bad sector protect group preload");
|
$display("Bad sector protect group preload");
|
|
|
WBData = -1;
|
WBData = -1;
|
|
|
end
|
end
|
|
|
//Power Up time 100 ns;
|
//Power Up time 100 ns;
|
initial
|
initial
|
begin
|
begin
|
PoweredUp = 1'b0;
|
PoweredUp = 1'b0;
|
#100 PoweredUp = 1'b1;
|
#100 PoweredUp = 1'b1;
|
end
|
end
|
|
|
always @(RESETNeg)
|
always @(RESETNeg)
|
begin
|
begin
|
RST <= #499 RESETNeg;
|
RST <= #499 RESETNeg;
|
end
|
end
|
|
|
initial
|
initial
|
begin
|
begin
|
write = 1'b0;
|
write = 1'b0;
|
read = 1'b0;
|
read = 1'b0;
|
Addr = 0;
|
Addr = 0;
|
|
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
ESP_ACT = 1'b0;
|
ESP_ACT = 1'b0;
|
OTP_ACT = 1'b0;
|
OTP_ACT = 1'b0;
|
|
|
PDONE = 1'b1;
|
PDONE = 1'b1;
|
PSTART = 1'b0;
|
PSTART = 1'b0;
|
|
|
PERR = 1'b0;
|
PERR = 1'b0;
|
|
|
EDONE = 1'b1;
|
EDONE = 1'b1;
|
ESTART = 1'b0;
|
ESTART = 1'b0;
|
ESUSP = 1'b0;
|
ESUSP = 1'b0;
|
ERES = 1'b0;
|
ERES = 1'b0;
|
|
|
EERR = 1'b0;
|
EERR = 1'b0;
|
READY_in = 1'b0;
|
READY_in = 1'b0;
|
READY = 1'b0;
|
READY = 1'b0;
|
end
|
end
|
|
|
always @(posedge START_T1_in)
|
always @(posedge START_T1_in)
|
begin:TESTARTT1r
|
begin:TESTARTT1r
|
#tdevice_START_T1 START_T1 = START_T1_in;
|
#tdevice_START_T1 START_T1 = START_T1_in;
|
end
|
end
|
always @(negedge START_T1_in)
|
always @(negedge START_T1_in)
|
begin:TESTARTT1f
|
begin:TESTARTT1f
|
#1 START_T1 = START_T1_in;
|
#1 START_T1 = START_T1_in;
|
end
|
end
|
|
|
always @(posedge CTMOUT_in)
|
always @(posedge CTMOUT_in)
|
begin:TCTMOUTr
|
begin:TCTMOUTr
|
#tdevice_CTMOUT CTMOUT = CTMOUT_in;
|
#tdevice_CTMOUT CTMOUT = CTMOUT_in;
|
end
|
end
|
always @(negedge CTMOUT_in)
|
always @(negedge CTMOUT_in)
|
begin:TCTMOUTf
|
begin:TCTMOUTf
|
#1 CTMOUT = CTMOUT_in;
|
#1 CTMOUT = CTMOUT_in;
|
end
|
end
|
|
|
always @(posedge READY_in)
|
always @(posedge READY_in)
|
begin:TREADYr
|
begin:TREADYr
|
#tdevice_READY READY = READY_in;
|
#tdevice_READY READY = READY_in;
|
end
|
end
|
always @(negedge READY_in)
|
always @(negedge READY_in)
|
begin:TREADYf
|
begin:TREADYf
|
#1 READY = READY_in;
|
#1 READY = READY_in;
|
end
|
end
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
//// obtain 'LAST_EVENT information
|
//// obtain 'LAST_EVENT information
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
always @(negedge OENeg)
|
always @(negedge OENeg)
|
begin
|
begin
|
OENeg_event = $time;
|
OENeg_event = $time;
|
end
|
end
|
always @(negedge CENeg)
|
always @(negedge CENeg)
|
begin
|
begin
|
CENeg_event = $time;
|
CENeg_event = $time;
|
end
|
end
|
|
|
always @(posedge OENeg)
|
always @(posedge OENeg)
|
begin
|
begin
|
OENeg_posEvent = $time;
|
OENeg_posEvent = $time;
|
end
|
end
|
always @(posedge CENeg)
|
always @(posedge CENeg)
|
begin
|
begin
|
CENeg_posEvent = $time;
|
CENeg_posEvent = $time;
|
end
|
end
|
|
|
always @(A)
|
always @(A)
|
begin
|
begin
|
ADDR_event = $time;
|
ADDR_event = $time;
|
end
|
end
|
|
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
//// sequential process for reset control and FSM state transition
|
//// sequential process for reset control and FSM state transition
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
always @(negedge RST)
|
always @(negedge RST)
|
begin
|
begin
|
ESP_ACT = 1'b0;
|
ESP_ACT = 1'b0;
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
OTP_ACT = 1'b0;
|
OTP_ACT = 1'b0;
|
end
|
end
|
|
|
reg R;
|
reg R;
|
reg E;
|
reg E;
|
always @(RESETNeg)
|
always @(RESETNeg)
|
begin
|
begin
|
if (PoweredUp)
|
if (PoweredUp)
|
begin
|
begin
|
//Hardware reset timing control
|
//Hardware reset timing control
|
if (~RESETNeg)
|
if (~RESETNeg)
|
begin
|
begin
|
E = 1'b0;
|
E = 1'b0;
|
if (~PDONE || ~EDONE)
|
if (~PDONE || ~EDONE)
|
begin
|
begin
|
//if program or erase in progress
|
//if program or erase in progress
|
READY_in = 1'b1;
|
READY_in = 1'b1;
|
R = 1'b1;
|
R = 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
READY_in = 1'b0;
|
READY_in = 1'b0;
|
R = 1'b0; //prog or erase not in progress
|
R = 1'b0; //prog or erase not in progress
|
end
|
end
|
end
|
end
|
else if (RESETNeg && RST)
|
else if (RESETNeg && RST)
|
begin
|
begin
|
//RESET# pulse < tRP
|
//RESET# pulse < tRP
|
READY_in = 1'b0;
|
READY_in = 1'b0;
|
R = 1'b0;
|
R = 1'b0;
|
E = 1'b1;
|
E = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(next_state or RESETNeg or CENeg or RST or
|
always @(next_state or RESETNeg or CENeg or RST or
|
READY or PoweredUp)
|
READY or PoweredUp)
|
begin: StateTransition
|
begin: StateTransition
|
|
|
if (PoweredUp)
|
if (PoweredUp)
|
begin
|
begin
|
if (RESETNeg && (~R || (R && READY)))
|
if (RESETNeg && (~R || (R && READY)))
|
begin
|
begin
|
current_state = next_state;
|
current_state = next_state;
|
READY_in = 1'b0;
|
READY_in = 1'b0;
|
E = 1'b0;
|
E = 1'b0;
|
R = 1'b0;
|
R = 1'b0;
|
reseted = 1'b1;
|
reseted = 1'b1;
|
end
|
end
|
else if ((~R && ~RESETNeg && ~RST) ||
|
else if ((~R && ~RESETNeg && ~RST) ||
|
(R && ~RESETNeg && ~RST && ~READY) ||
|
(R && ~RESETNeg && ~RST && ~READY) ||
|
(R && RESETNeg && ~RST && ~READY))
|
(R && RESETNeg && ~RST && ~READY))
|
begin
|
begin
|
//no state transition while RESET# low
|
//no state transition while RESET# low
|
current_state = RESET; //reset start
|
current_state = RESET; //reset start
|
reseted = 1'b0;
|
reseted = 1'b0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
current_state = RESET; // reset
|
current_state = RESET; // reset
|
reseted = 1'b0;
|
reseted = 1'b0;
|
E = 1'b0;
|
E = 1'b0;
|
R = 1'b0;
|
R = 1'b0;
|
end
|
end
|
end
|
end
|
|
|
// /////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////
|
// //Glitch Protection: Inertial Delay does not propagate pulses <5ns
|
// //Glitch Protection: Inertial Delay does not propagate pulses <5ns
|
// /////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////
|
assign #5 gWE_n = WENeg_ipd;
|
assign #5 gWE_n = WENeg_ipd;
|
assign #5 gCE_n = CENeg_ipd;
|
assign #5 gCE_n = CENeg_ipd;
|
assign #5 gOE_n = OENeg_ipd;
|
assign #5 gOE_n = OENeg_ipd;
|
|
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//Process that reports warning when changes on signals WE#, CE#, OE# are
|
//Process that reports warning when changes on signals WE#, CE#, OE# are
|
//discarded
|
//discarded
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
always @(WENeg)
|
always @(WENeg)
|
begin: PulseWatch1
|
begin: PulseWatch1
|
if (gWE_n == WENeg)
|
if (gWE_n == WENeg)
|
$display("Glitch on WE#");
|
$display("Glitch on WE#");
|
end
|
end
|
always @(CENeg)
|
always @(CENeg)
|
begin: PulseWatch2
|
begin: PulseWatch2
|
if (gCE_n == CENeg)
|
if (gCE_n == CENeg)
|
$display("Glitch on CE#");
|
$display("Glitch on CE#");
|
end
|
end
|
always @(OENeg)
|
always @(OENeg)
|
begin: PulseWatch3
|
begin: PulseWatch3
|
if (gOE_n == OENeg)
|
if (gOE_n == OENeg)
|
$display("Glitch on OE#");
|
$display("Glitch on OE#");
|
end
|
end
|
|
|
//latch address on rising edge and data on falling edge of write
|
//latch address on rising edge and data on falling edge of write
|
always @(gWE_n or gCE_n or gOE_n )
|
always @(gWE_n or gCE_n or gOE_n )
|
begin: write_dc
|
begin: write_dc
|
if (RESETNeg!=1'b0)
|
if (RESETNeg!=1'b0)
|
begin
|
begin
|
if (~gWE_n && ~gCE_n && gOE_n)
|
if (~gWE_n && ~gCE_n && gOE_n)
|
write = 1'b1;
|
write = 1'b1;
|
else
|
else
|
write = 1'b0;
|
write = 1'b0;
|
end
|
end
|
|
|
if (gWE_n && ~gCE_n && ~gOE_n)
|
if (gWE_n && ~gCE_n && ~gOE_n)
|
read = 1'b1;
|
read = 1'b1;
|
else
|
else
|
read = 1'b0;
|
read = 1'b0;
|
end
|
end
|
|
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
////Latch address on falling edge of WE# or CE# what ever comes later
|
////Latch address on falling edge of WE# or CE# what ever comes later
|
////Latch data on rising edge of WE# or CE# what ever comes first
|
////Latch data on rising edge of WE# or CE# what ever comes first
|
//// also Write cycle decode
|
//// also Write cycle decode
|
////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////
|
integer A_tmp ;
|
integer A_tmp ;
|
integer SA_tmp ;
|
integer SA_tmp ;
|
integer A_tmp1 ;
|
integer A_tmp1 ;
|
integer Mem_tmp;
|
integer Mem_tmp;
|
integer AS_addr;
|
integer AS_addr;
|
reg CE;
|
reg CE;
|
|
|
always @(WENeg_ipd)
|
always @(WENeg_ipd)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd )
|
if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd )
|
begin
|
begin
|
A_tmp = A[10:0];
|
A_tmp = A[10:0];
|
SA_tmp = A[HiAddrBit:16];
|
SA_tmp = A[HiAddrBit:16];
|
A_tmp1 = A[15:0];
|
A_tmp1 = A[15:0];
|
Mem_tmp = A;
|
Mem_tmp = A;
|
AS_addr = A[21];
|
AS_addr = A[21];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(CENeg_ipd)
|
always @(CENeg_ipd)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) )
|
if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) )
|
begin
|
begin
|
A_tmp = A[10:0];
|
A_tmp = A[10:0];
|
SA_tmp = A[HiAddrBit:16];
|
SA_tmp = A[HiAddrBit:16];
|
A_tmp1 = A[15:0];
|
A_tmp1 = A[15:0];
|
Mem_tmp = A;
|
Mem_tmp = A;
|
AS_addr = A[21];
|
AS_addr = A[21];
|
end
|
end
|
if (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd)
|
if (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd)
|
begin
|
begin
|
SecAddr = SA_tmp;
|
SecAddr = SA_tmp;
|
Address = A_tmp1;
|
Address = A_tmp1;
|
MemAddress = Mem_tmp;
|
MemAddress = Mem_tmp;
|
Addr = A_tmp;
|
Addr = A_tmp;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(negedge OENeg_ipd )
|
always @(negedge OENeg_ipd )
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd)
|
if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd)
|
begin
|
begin
|
A_tmp = A[10:0];
|
A_tmp = A[10:0];
|
SA_tmp = A[HiAddrBit:16];
|
SA_tmp = A[HiAddrBit:16];
|
A_tmp1 = A[15:0];
|
A_tmp1 = A[15:0];
|
Mem_tmp = A;
|
Mem_tmp = A;
|
SecAddr = SA_tmp;
|
SecAddr = SA_tmp;
|
Address = A_tmp1;
|
Address = A_tmp1;
|
MemAddress = Mem_tmp;
|
MemAddress = Mem_tmp;
|
Addr = A_tmp;
|
Addr = A_tmp;
|
AS_addr = A[21];
|
AS_addr = A[21];
|
end
|
end
|
|
|
SecAddr = SA_tmp;
|
SecAddr = SA_tmp;
|
Address = A_tmp1;
|
Address = A_tmp1;
|
MemAddress = Mem_tmp;
|
MemAddress = Mem_tmp;
|
CE = CENeg;
|
CE = CENeg;
|
Addr = A_tmp;
|
Addr = A_tmp;
|
end
|
end
|
end
|
end
|
|
|
always @(A)
|
always @(A)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
if (WENeg_ipd && ~CENeg_ipd && ~OENeg_ipd)
|
if (WENeg_ipd && ~CENeg_ipd && ~OENeg_ipd)
|
begin
|
begin
|
A_tmp = A[10:0];
|
A_tmp = A[10:0];
|
SA_tmp = A[HiAddrBit:16];
|
SA_tmp = A[HiAddrBit:16];
|
A_tmp1 = A[15:0];
|
A_tmp1 = A[15:0];
|
Mem_tmp = A;
|
Mem_tmp = A;
|
AS_addr = A[21];
|
AS_addr = A[21];
|
SecAddr = SA_tmp;
|
SecAddr = SA_tmp;
|
Address = A_tmp1;
|
Address = A_tmp1;
|
MemAddress = Mem_tmp;
|
MemAddress = Mem_tmp;
|
Addr = A_tmp;
|
Addr = A_tmp;
|
CE = CENeg;
|
CE = CENeg;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge write)
|
always @(posedge write)
|
begin
|
begin
|
SecAddr = SA_tmp;
|
SecAddr = SA_tmp;
|
Address = A_tmp1;
|
Address = A_tmp1;
|
MemAddress = Mem_tmp;
|
MemAddress = Mem_tmp;
|
Addr = A_tmp;
|
Addr = A_tmp;
|
CE = CENeg;
|
CE = CENeg;
|
end
|
end
|
|
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
// Timing control for the Program Operations
|
// Timing control for the Program Operations
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
|
|
integer cnt_write = 0;
|
integer cnt_write = 0;
|
//time elapsed_write ;
|
//time elapsed_write ;
|
time duration_write ;
|
time duration_write ;
|
//time start_write ;
|
//time start_write ;
|
event pdone_event;
|
event pdone_event;
|
|
|
always @(posedge reseted)
|
always @(posedge reseted)
|
begin
|
begin
|
PDONE = 1'b1;
|
PDONE = 1'b1;
|
end
|
end
|
|
|
always @(reseted or PSTART)
|
always @(reseted or PSTART)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
if (PSTART && PDONE)
|
if (PSTART && PDONE)
|
begin
|
begin
|
if ((~FactoryProt && OTP_ACT)||
|
if ((~FactoryProt && OTP_ACT)||
|
( ~Sec_Prot[SA] &&(~Ers_queue[SA] || ~ESP_ACT )&& ~OTP_ACT))
|
( ~Sec_Prot[SA] &&(~Ers_queue[SA] || ~ESP_ACT )&& ~OTP_ACT))
|
begin
|
begin
|
duration_write = tdevice_POB + 5;
|
duration_write = tdevice_POB + 5;
|
PDONE = 1'b0;
|
PDONE = 1'b0;
|
->pdone_event;
|
->pdone_event;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
PERR = 1'b1;
|
PERR = 1'b1;
|
PERR <= #1005 1'b0;
|
PERR <= #1005 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(pdone_event)
|
always @(pdone_event)
|
begin:pdone_process
|
begin:pdone_process
|
PDONE = 1'b0;
|
PDONE = 1'b0;
|
#duration_write PDONE = 1'b1;
|
#duration_write PDONE = 1'b1;
|
end
|
end
|
|
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
// Timing control for the Erase Operations
|
// Timing control for the Erase Operations
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
integer cnt_erase = 0;
|
integer cnt_erase = 0;
|
time elapsed_erase;
|
time elapsed_erase;
|
time duration_erase;
|
time duration_erase;
|
time start_erase;
|
time start_erase;
|
|
|
always @(posedge reseted)
|
always @(posedge reseted)
|
begin
|
begin
|
disable edone_process;
|
disable edone_process;
|
EDONE = 1'b1;
|
EDONE = 1'b1;
|
end
|
end
|
event edone_event;
|
event edone_event;
|
always @(reseted or ESTART)
|
always @(reseted or ESTART)
|
begin: erase
|
begin: erase
|
integer i;
|
integer i;
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
if (ESTART && EDONE)
|
if (ESTART && EDONE)
|
begin
|
begin
|
cnt_erase = 0;
|
cnt_erase = 0;
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
begin
|
begin
|
if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]!=1'b1))
|
if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]!=1'b1))
|
cnt_erase = cnt_erase + 1;
|
cnt_erase = cnt_erase + 1;
|
end
|
end
|
|
|
if (cnt_erase>0)
|
if (cnt_erase>0)
|
begin
|
begin
|
elapsed_erase = 0;
|
elapsed_erase = 0;
|
duration_erase = cnt_erase* tdevice_SEO + 4;
|
duration_erase = cnt_erase* tdevice_SEO + 4;
|
->edone_event;
|
->edone_event;
|
start_erase = $time;
|
start_erase = $time;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
EERR = 1'b1;
|
EERR = 1'b1;
|
EERR <= #100005 1'b0;
|
EERR <= #100005 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(edone_event)
|
always @(edone_event)
|
begin : edone_process
|
begin : edone_process
|
EDONE = 1'b0;
|
EDONE = 1'b0;
|
#duration_erase EDONE = 1'b1;
|
#duration_erase EDONE = 1'b1;
|
end
|
end
|
|
|
always @(reseted or ESUSP)
|
always @(reseted or ESUSP)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
if (ESUSP && ~EDONE)
|
if (ESUSP && ~EDONE)
|
begin
|
begin
|
disable edone_process;
|
disable edone_process;
|
elapsed_erase = $time - start_erase;
|
elapsed_erase = $time - start_erase;
|
duration_erase = duration_erase - elapsed_erase;
|
duration_erase = duration_erase - elapsed_erase;
|
EDONE = 1'b0;
|
EDONE = 1'b0;
|
end
|
end
|
end
|
end
|
always @(reseted or ERES)
|
always @(reseted or ERES)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
if (ERES && ~EDONE)
|
if (ERES && ~EDONE)
|
begin
|
begin
|
start_erase = $time;
|
start_erase = $time;
|
EDONE = 1'b0;
|
EDONE = 1'b0;
|
->edone_event;
|
->edone_event;
|
end
|
end
|
end
|
end
|
|
|
// /////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////
|
// // Main Behavior Process
|
// // Main Behavior Process
|
// // combinational process for next state generation
|
// // combinational process for next state generation
|
// /////////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////////
|
reg PATTERN_1 = 1'b0;
|
reg PATTERN_1 = 1'b0;
|
reg PATTERN_2 = 1'b0;
|
reg PATTERN_2 = 1'b0;
|
reg A_PAT_1 = 1'b0;
|
reg A_PAT_1 = 1'b0;
|
reg A_PAT_2 = 1'b0;
|
reg A_PAT_2 = 1'b0;
|
reg A_PAT_3 = 1'b0;
|
reg A_PAT_3 = 1'b0;
|
integer DataByte ;
|
integer DataByte ;
|
|
|
always @(negedge write)
|
always @(negedge write)
|
begin
|
begin
|
DataByte = DIn;
|
DataByte = DIn;
|
PATTERN_1 = DataByte==8'hAA ;
|
PATTERN_1 = DataByte==8'hAA ;
|
PATTERN_2 = DataByte==8'h55 ;
|
PATTERN_2 = DataByte==8'h55 ;
|
A_PAT_1 = 1'b1;
|
A_PAT_1 = 1'b1;
|
A_PAT_2 = Address==16'hAAA ;
|
A_PAT_2 = Address==16'hAAA ;
|
A_PAT_3 = Address==16'h555 ;
|
A_PAT_3 = Address==16'h555 ;
|
|
|
end
|
end
|
|
|
always @(write or reseted)
|
always @(write or reseted)
|
begin: StateGen1
|
begin: StateGen1
|
if (reseted!=1'b1)
|
if (reseted!=1'b1)
|
next_state = current_state;
|
next_state = current_state;
|
else
|
else
|
if (~write)
|
if (~write)
|
case (current_state)
|
case (current_state)
|
RESET :
|
RESET :
|
begin
|
begin
|
if (PATTERN_1)
|
if (PATTERN_1)
|
next_state = Z001;
|
next_state = Z001;
|
else if ((Addr==8'h55) && (DataByte==8'h98))
|
else if ((Addr==8'h55) && (DataByte==8'h98))
|
next_state = CFI;
|
next_state = CFI;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
CFI:
|
CFI:
|
begin
|
begin
|
if (DataByte==8'hF0)
|
if (DataByte==8'hF0)
|
next_state = RESET;
|
next_state = RESET;
|
else
|
else
|
next_state = CFI;
|
next_state = CFI;
|
end
|
end
|
|
|
Z001 :
|
Z001 :
|
begin
|
begin
|
if (PATTERN_2)
|
if (PATTERN_2)
|
next_state = PREL_SETBWB;
|
next_state = PREL_SETBWB;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
PREL_SETBWB :
|
PREL_SETBWB :
|
begin
|
begin
|
if (A_PAT_1 && (DataByte==16'h20))
|
if (A_PAT_1 && (DataByte==16'h20))
|
next_state = PREL_ULBYPASS;
|
next_state = PREL_ULBYPASS;
|
else if (A_PAT_1 && (DataByte==16'h90))
|
else if (A_PAT_1 && (DataByte==16'h90))
|
next_state = AS;
|
next_state = AS;
|
else if (A_PAT_1 && (DataByte==16'hA0))
|
else if (A_PAT_1 && (DataByte==16'hA0))
|
next_state = A0SEEN;
|
next_state = A0SEEN;
|
else if (A_PAT_1 && (DataByte==16'h80))
|
else if (A_PAT_1 && (DataByte==16'h80))
|
next_state = C8;
|
next_state = C8;
|
else if (A_PAT_1 && (DataByte==16'h88))
|
else if (A_PAT_1 && (DataByte==16'h88))
|
next_state = OTP;
|
next_state = OTP;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
PREL_ULBYPASS :
|
PREL_ULBYPASS :
|
begin
|
begin
|
if (DataByte == 16'h90 )
|
if (DataByte == 16'h90 )
|
next_state <= PREL_ULBYPASS_RESET;
|
next_state <= PREL_ULBYPASS_RESET;
|
if (A_PAT_1 && (DataByte == 16'hA0))
|
if (A_PAT_1 && (DataByte == 16'hA0))
|
next_state = A0SEEN;
|
next_state = A0SEEN;
|
else
|
else
|
next_state = PREL_ULBYPASS;
|
next_state = PREL_ULBYPASS;
|
end
|
end
|
|
|
PREL_ULBYPASS_RESET :
|
PREL_ULBYPASS_RESET :
|
begin
|
begin
|
if (DataByte == 16'h00 )
|
if (DataByte == 16'h00 )
|
if (ESP_ACT)
|
if (ESP_ACT)
|
next_state = ESP;
|
next_state = ESP;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
else
|
else
|
next_state <= PREL_ULBYPASS;
|
next_state <= PREL_ULBYPASS;
|
end
|
end
|
|
|
AS :
|
AS :
|
begin
|
begin
|
if (DataByte==16'hF0)
|
if (DataByte==16'hF0)
|
next_state = RESET;
|
next_state = RESET;
|
else if ((Addr==8'h55) && (DataByte==8'h98))
|
else if ((Addr==8'h55) && (DataByte==8'h98))
|
next_state = AS_CFI;
|
next_state = AS_CFI;
|
else
|
else
|
next_state = AS;
|
next_state = AS;
|
end
|
end
|
|
|
AS_CFI:
|
AS_CFI:
|
begin
|
begin
|
if (DataByte==8'hF0)
|
if (DataByte==8'hF0)
|
next_state = AS;
|
next_state = AS;
|
else
|
else
|
next_state = AS_CFI;
|
next_state = AS_CFI;
|
end
|
end
|
|
|
A0SEEN :
|
A0SEEN :
|
begin
|
begin
|
next_state = PGMS;
|
next_state = PGMS;
|
end
|
end
|
|
|
OTP :
|
OTP :
|
begin
|
begin
|
if (PATTERN_1)
|
if (PATTERN_1)
|
next_state = OTP_Z001;
|
next_state = OTP_Z001;
|
else
|
else
|
next_state = OTP;
|
next_state = OTP;
|
end
|
end
|
|
|
OTP_Z001 :
|
OTP_Z001 :
|
begin
|
begin
|
if (PATTERN_2)
|
if (PATTERN_2)
|
next_state = OTP_PREL;
|
next_state = OTP_PREL;
|
else
|
else
|
next_state = OTP;
|
next_state = OTP;
|
end
|
end
|
|
|
OTP_PREL :
|
OTP_PREL :
|
begin
|
begin
|
if (A_PAT_1 && (DataByte == 16'h90))
|
if (A_PAT_1 && (DataByte == 16'h90))
|
next_state = OTP_AS;
|
next_state = OTP_AS;
|
else if (A_PAT_1 && (DataByte == 16'hA0))
|
else if (A_PAT_1 && (DataByte == 16'hA0))
|
next_state = OTP_A0SEEN;
|
next_state = OTP_A0SEEN;
|
else
|
else
|
next_state = OTP;
|
next_state = OTP;
|
end
|
end
|
|
|
OTP_AS:
|
OTP_AS:
|
begin
|
begin
|
if (DataByte == 16'h00)
|
if (DataByte == 16'h00)
|
if (ESP_ACT)
|
if (ESP_ACT)
|
next_state = ESP;
|
next_state = ESP;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
else if (DataByte == 16'hF0)
|
else if (DataByte == 16'hF0)
|
next_state = OTP;
|
next_state = OTP;
|
else if (DataByte == 16'h98)
|
else if (DataByte == 16'h98)
|
next_state = OTP_AS_CFI;
|
next_state = OTP_AS_CFI;
|
else
|
else
|
next_state = OTP_AS;
|
next_state = OTP_AS;
|
end
|
end
|
|
|
OTP_AS_CFI:
|
OTP_AS_CFI:
|
begin
|
begin
|
if (DataByte == 16'hF0)
|
if (DataByte == 16'hF0)
|
next_state = OTP_AS;
|
next_state = OTP_AS;
|
else
|
else
|
next_state = OTP_AS_CFI;
|
next_state = OTP_AS_CFI;
|
end
|
end
|
|
|
OTP_A0SEEN :
|
OTP_A0SEEN :
|
begin
|
begin
|
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
|
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
|
(Address >= 16'hFF00))
|
(Address >= 16'hFF00))
|
next_state = PGMS;
|
next_state = PGMS;
|
else
|
else
|
next_state = OTP;
|
next_state = OTP;
|
end
|
end
|
|
|
C8 :
|
C8 :
|
begin
|
begin
|
if (PATTERN_1)
|
if (PATTERN_1)
|
next_state = C8_Z001;
|
next_state = C8_Z001;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
C8_Z001 :
|
C8_Z001 :
|
begin
|
begin
|
if (PATTERN_2)
|
if (PATTERN_2)
|
next_state = C8_PREL;
|
next_state = C8_PREL;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
C8_PREL :
|
C8_PREL :
|
begin
|
begin
|
if (A_PAT_1 && (DataByte==16'h10))
|
if (A_PAT_1 && (DataByte==16'h10))
|
next_state = ERS;
|
next_state = ERS;
|
else if (DataByte==16'h30)
|
else if (DataByte==16'h30)
|
next_state = SERS;
|
next_state = SERS;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
ERS :
|
ERS :
|
begin
|
begin
|
end
|
end
|
|
|
SERS :
|
SERS :
|
begin
|
begin
|
if (~CTMOUT && DataByte == 16'hB0)
|
if (~CTMOUT && DataByte == 16'hB0)
|
next_state = ESP; // ESP according to datasheet
|
next_state = ESP; // ESP according to datasheet
|
else if (DataByte==16'h30)
|
else if (DataByte==16'h30)
|
next_state = SERS;
|
next_state = SERS;
|
else
|
else
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
|
|
SERS_EXEC :
|
SERS_EXEC :
|
begin
|
begin
|
end
|
end
|
|
|
ESP :
|
ESP :
|
begin
|
begin
|
if (DataByte == 16'h30)
|
if (DataByte == 16'h30)
|
next_state = SERS_EXEC;
|
next_state = SERS_EXEC;
|
else
|
else
|
begin
|
begin
|
if (PATTERN_1)
|
if (PATTERN_1)
|
next_state = ESP_Z001;
|
next_state = ESP_Z001;
|
if (Addr == 8'h55 && DataByte == 8'h98)
|
if (Addr == 8'h55 && DataByte == 8'h98)
|
next_state = ESP_CFI;
|
next_state = ESP_CFI;
|
end
|
end
|
end
|
end
|
|
|
ESP_CFI:
|
ESP_CFI:
|
begin
|
begin
|
if (DataByte == 8'hF0)
|
if (DataByte == 8'hF0)
|
next_state = ESP;
|
next_state = ESP;
|
else
|
else
|
next_state = ESP_CFI;
|
next_state = ESP_CFI;
|
end
|
end
|
|
|
ESP_Z001 :
|
ESP_Z001 :
|
begin
|
begin
|
if (PATTERN_2)
|
if (PATTERN_2)
|
next_state = ESP_PREL;
|
next_state = ESP_PREL;
|
else
|
else
|
next_state = ESP;
|
next_state = ESP;
|
end
|
end
|
|
|
ESP_PREL :
|
ESP_PREL :
|
begin
|
begin
|
if (A_PAT_1 && DataByte == 16'hA0)
|
if (A_PAT_1 && DataByte == 16'hA0)
|
next_state = ESP_A0SEEN;
|
next_state = ESP_A0SEEN;
|
else if (A_PAT_1 && DataByte == 16'h20)
|
else if (A_PAT_1 && DataByte == 16'h20)
|
next_state <= PREL_ULBYPASS;
|
next_state <= PREL_ULBYPASS;
|
else if (A_PAT_1 && DataByte == 16'h88)
|
else if (A_PAT_1 && DataByte == 16'h88)
|
next_state <= OTP;
|
next_state <= OTP;
|
else if (A_PAT_1 && DataByte == 16'h90)
|
else if (A_PAT_1 && DataByte == 16'h90)
|
next_state = ESP_AS;
|
next_state = ESP_AS;
|
else
|
else
|
next_state = ESP;
|
next_state = ESP;
|
end
|
end
|
|
|
ESP_A0SEEN :
|
ESP_A0SEEN :
|
begin
|
begin
|
next_state = PGMS; //set ESP
|
next_state = PGMS; //set ESP
|
end
|
end
|
|
|
ESP_AS :
|
ESP_AS :
|
begin
|
begin
|
if (DataByte == 16'hF0)
|
if (DataByte == 16'hF0)
|
next_state = ESP;
|
next_state = ESP;
|
else if ((Addr==8'h55) && (DataByte==8'h98))
|
else if ((Addr==8'h55) && (DataByte==8'h98))
|
next_state = ESP_AS_CFI;
|
next_state = ESP_AS_CFI;
|
end
|
end
|
|
|
ESP_AS_CFI:
|
ESP_AS_CFI:
|
begin
|
begin
|
if (DataByte == 8'hF0)
|
if (DataByte == 8'hF0)
|
next_state = ESP_AS;
|
next_state = ESP_AS;
|
else
|
else
|
next_state = ESP_AS_CFI;
|
next_state = ESP_AS_CFI;
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge PDONE or negedge PERR)
|
always @(posedge PDONE or negedge PERR)
|
begin: StateGen6
|
begin: StateGen6
|
if (reseted!=1'b1)
|
if (reseted!=1'b1)
|
next_state = current_state;
|
next_state = current_state;
|
else
|
else
|
begin
|
begin
|
if (current_state==PGMS && ULBYPASS)
|
if (current_state==PGMS && ULBYPASS)
|
next_state = PREL_ULBYPASS;
|
next_state = PREL_ULBYPASS;
|
else if (current_state==PGMS && OTP_ACT)
|
else if (current_state==PGMS && OTP_ACT)
|
next_state = OTP;
|
next_state = OTP;
|
else if (current_state==PGMS && ESP_ACT)
|
else if (current_state==PGMS && ESP_ACT)
|
next_state = ESP;
|
next_state = ESP;
|
else if (current_state==PGMS)
|
else if (current_state==PGMS)
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge EDONE or negedge EERR)
|
always @(posedge EDONE or negedge EERR)
|
begin: StateGen2
|
begin: StateGen2
|
if (reseted!=1'b1)
|
if (reseted!=1'b1)
|
next_state = current_state;
|
next_state = current_state;
|
else
|
else
|
begin
|
begin
|
if ((current_state==ERS) || (current_state==SERS_EXEC))
|
if ((current_state==ERS) || (current_state==SERS_EXEC))
|
next_state = RESET;
|
next_state = RESET;
|
end
|
end
|
end
|
end
|
|
|
always @(negedge write or reseted)
|
always @(negedge write or reseted)
|
begin: StateGen7 //ok
|
begin: StateGen7 //ok
|
integer i,j;
|
integer i,j;
|
if (reseted!=1'b1)
|
if (reseted!=1'b1)
|
next_state = current_state;
|
next_state = current_state;
|
else
|
else
|
begin
|
begin
|
if (current_state==SERS_EXEC && (write==1'b0) && (EERR!=1'b1))
|
if (current_state==SERS_EXEC && (write==1'b0) && (EERR!=1'b1))
|
if (DataByte==16'hB0)
|
if (DataByte==16'hB0)
|
begin
|
begin
|
next_state = ESPS;
|
next_state = ESPS;
|
ESUSP = 1'b1;
|
ESUSP = 1'b1;
|
ESUSP <= #1 1'b0;
|
ESUSP <= #1 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(CTMOUT or reseted)
|
always @(CTMOUT or reseted)
|
begin: StateGen4
|
begin: StateGen4
|
if (reseted!=1'b1)
|
if (reseted!=1'b1)
|
next_state = current_state;
|
next_state = current_state;
|
else
|
else
|
begin
|
begin
|
if (current_state==SERS && CTMOUT) next_state = SERS_EXEC;
|
if (current_state==SERS && CTMOUT) next_state = SERS_EXEC;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge START_T1 or reseted)
|
always @(posedge START_T1 or reseted)
|
begin: StateGen5
|
begin: StateGen5
|
if (reseted!=1'b1)
|
if (reseted!=1'b1)
|
next_state = current_state;
|
next_state = current_state;
|
else
|
else
|
if (current_state==ESPS && START_T1) next_state = ESP;
|
if (current_state==ESPS && START_T1) next_state = ESP;
|
end
|
end
|
|
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//FSM Output generation and general funcionality
|
//FSM Output generation and general funcionality
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
|
|
always @(posedge read)
|
always @(posedge read)
|
begin
|
begin
|
->oe_event;
|
->oe_event;
|
end
|
end
|
always @(MemAddress)
|
always @(MemAddress)
|
begin
|
begin
|
if (read)
|
if (read)
|
->oe_event;
|
->oe_event;
|
end
|
end
|
|
|
always @(oe_event)
|
always @(oe_event)
|
begin
|
begin
|
oe = 1'b1;
|
oe = 1'b1;
|
#1 oe = 1'b0;
|
#1 oe = 1'b0;
|
end
|
end
|
|
|
always @(DOut_zd)
|
always @(DOut_zd)
|
begin : OutputGen
|
begin : OutputGen
|
if (DOut_zd[0] !== 1'bz)
|
if (DOut_zd[0] !== 1'bz)
|
begin
|
begin
|
CEDQ_t = CENeg_event + CEDQ_01;
|
CEDQ_t = CENeg_event + CEDQ_01;
|
OEDQ_t = OENeg_event + OEDQ_01;
|
OEDQ_t = OENeg_event + OEDQ_01;
|
ADDRDQ_t = ADDR_event + ADDRDQ_01;
|
ADDRDQ_t = ADDR_event + ADDRDQ_01;
|
FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
|
FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
|
FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
|
FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
|
FROMADDR = 1'b1;
|
FROMADDR = 1'b1;
|
if ((ADDRDQ_t > $time )&&
|
if ((ADDRDQ_t > $time )&&
|
(((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
|
(((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
|
((ADDRDQ_t>CEDQ_t)&&FROMCE)))
|
((ADDRDQ_t>CEDQ_t)&&FROMCE)))
|
begin
|
begin
|
TempData = DOut_zd;
|
TempData = DOut_zd;
|
FROMADDR = 1'b0;
|
FROMADDR = 1'b0;
|
DOut_Pass = 8'bx;
|
DOut_Pass = 8'bx;
|
#(ADDRDQ_t - $time) DOut_Pass = TempData;
|
#(ADDRDQ_t - $time) DOut_Pass = TempData;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
DOut_Pass = DOut_zd;
|
DOut_Pass = DOut_zd;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(DOut_zd)
|
always @(DOut_zd)
|
begin
|
begin
|
if (DOut_zd[0] === 1'bz)
|
if (DOut_zd[0] === 1'bz)
|
begin
|
begin
|
disable OutputGen;
|
disable OutputGen;
|
FROMCE = 1'b1;
|
FROMCE = 1'b1;
|
FROMOE = 1'b1;
|
FROMOE = 1'b1;
|
if ((CENeg_posEvent <= OENeg_posEvent) &&
|
if ((CENeg_posEvent <= OENeg_posEvent) &&
|
( CENeg_posEvent + 5 >= $time))
|
( CENeg_posEvent + 5 >= $time))
|
FROMOE = 1'b0;
|
FROMOE = 1'b0;
|
if ((OENeg_posEvent < CENeg_posEvent) &&
|
if ((OENeg_posEvent < CENeg_posEvent) &&
|
( OENeg_posEvent + 5 >= $time))
|
( OENeg_posEvent + 5 >= $time))
|
FROMCE = 1'b0;
|
FROMCE = 1'b0;
|
FROMADDR = 1'b0;
|
FROMADDR = 1'b0;
|
DOut_Pass = DOut_zd;
|
DOut_Pass = DOut_zd;
|
end
|
end
|
end
|
end
|
|
|
always @(oe or reseted or current_state)
|
always @(oe or reseted or current_state)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
case (current_state)
|
case (current_state)
|
|
|
RESET :
|
RESET :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
MemRead(DOut_zd);
|
MemRead(DOut_zd);
|
end
|
end
|
|
|
AS, ESP_AS, OTP_AS :
|
AS, ESP_AS, OTP_AS :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
if (AS_addr == 1'b0)
|
if (AS_addr == 1'b0)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_ID = 1'b0;
|
AS_ID = 1'b0;
|
if ((Address[7:0] == 0) && (AS_ID == 1'b1))
|
if ((Address[7:0] == 0) && (AS_ID == 1'b1))
|
DOut_zd = 1;
|
DOut_zd = 1;
|
else if ((Address[7:0] == 1) && (AS_ID == 1'b1))
|
else if ((Address[7:0] == 1) && (AS_ID == 1'b1))
|
DOut_zd = 8'hA3;
|
DOut_zd = 8'hA3;
|
else if ((Address[7:0] == 2) &&
|
else if ((Address[7:0] == 2) &&
|
(((SecAddr < 32 ) && (AS_ID == 1'b1))
|
(((SecAddr < 32 ) && (AS_ID == 1'b1))
|
|| ((SecAddr > 31 ) && (AS_ID2 == 1'b1))))
|
|| ((SecAddr > 31 ) && (AS_ID2 == 1'b1))))
|
begin
|
begin
|
DOut_zd = 8'b00000000;
|
DOut_zd = 8'b00000000;
|
DOut_zd[0] = Sec_Prot[SecAddr];
|
DOut_zd[0] = Sec_Prot[SecAddr];
|
end
|
end
|
else if ((Address[7:0] == 6) && (AS_SecSi_FP == 1'b1))
|
else if ((Address[7:0] == 6) && (AS_SecSi_FP == 1'b1))
|
begin
|
begin
|
DOut_zd = 8'b0;
|
DOut_zd = 8'b0;
|
if (FactoryProt)
|
if (FactoryProt)
|
DOut_zd = 16'h99;
|
DOut_zd = 16'h99;
|
else
|
else
|
DOut_zd = 16'h19;
|
DOut_zd = 16'h19;
|
end
|
end
|
else
|
else
|
DOut_zd = 8'bz;
|
DOut_zd = 8'bz;
|
end
|
end
|
end
|
end
|
|
|
OTP :
|
OTP :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
|
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
|
(Address >= 16'hFF00))
|
(Address >= 16'hFF00))
|
begin
|
begin
|
SecSiAddr = Address%(SecSiSize +1);
|
SecSiAddr = Address%(SecSiSize +1);
|
if (SecSi[SecSiAddr]==-1)
|
if (SecSi[SecSiAddr]==-1)
|
DOut_zd = 8'bx;
|
DOut_zd = 8'bx;
|
else
|
else
|
DOut_zd = SecSi[SecSiAddr];
|
DOut_zd = SecSi[SecSiAddr];
|
end
|
end
|
else
|
else
|
$display ("Invalid SecSi query address");
|
$display ("Invalid SecSi query address");
|
end
|
end
|
end
|
end
|
|
|
CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, OTP_AS_CFI :
|
CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, OTP_AS_CFI :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
DOut_zd = 8'bZ;
|
DOut_zd = 8'bZ;
|
if (((MemAddress>=16'h10) && (MemAddress <= 16'h3C)) ||
|
if (((MemAddress>=16'h10) && (MemAddress <= 16'h3C)) ||
|
((MemAddress>=16'h40) && (MemAddress <= 16'h4F)))
|
((MemAddress>=16'h40) && (MemAddress <= 16'h4F)))
|
begin
|
begin
|
DOut_zd = CFI_array[MemAddress];
|
DOut_zd = CFI_array[MemAddress];
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display ("Invalid CFI query address");
|
$display ("Invalid CFI query address");
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
ERS :
|
ERS :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
// read status / embeded erase algorithm - Chip Erase
|
// read status / embeded erase algorithm - Chip Erase
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
Status[7] = 1'b0;
|
Status[7] = 1'b0;
|
Status[6] = ~Status[6]; //toggle
|
Status[6] = ~Status[6]; //toggle
|
Status[5] = 1'b0;
|
Status[5] = 1'b0;
|
Status[3] = 1'b1;
|
Status[3] = 1'b1;
|
Status[2] = ~Status[2]; //toggle
|
Status[2] = ~Status[2]; //toggle
|
|
|
DOut_zd = Status;
|
DOut_zd = Status;
|
end
|
end
|
end
|
end
|
|
|
SERS :
|
SERS :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
//read status - sector erase timeout
|
//read status - sector erase timeout
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
Status[3] = 1'b0;
|
Status[3] = 1'b0;
|
Status[7] = 1'b1;
|
Status[7] = 1'b1;
|
DOut_zd = Status;
|
DOut_zd = Status;
|
end
|
end
|
end
|
end
|
|
|
ESPS :
|
ESPS :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
//read status / erase suspend timeout - stil erasing
|
//read status / erase suspend timeout - stil erasing
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
if (Ers_queue[SecAddr]==1'b1)
|
if (Ers_queue[SecAddr]==1'b1)
|
begin
|
begin
|
Status[7] = 1'b0;
|
Status[7] = 1'b0;
|
Status[2] = ~Status[2]; //toggle
|
Status[2] = ~Status[2]; //toggle
|
end
|
end
|
else
|
else
|
Status[7] = 1'b1;
|
Status[7] = 1'b1;
|
Status[6] = ~Status[6]; //toggle
|
Status[6] = ~Status[6]; //toggle
|
Status[5] = 1'b0;
|
Status[5] = 1'b0;
|
Status[3] = 1'b1;
|
Status[3] = 1'b1;
|
DOut_zd = Status;
|
DOut_zd = Status;
|
end
|
end
|
end
|
end
|
|
|
SERS_EXEC:
|
SERS_EXEC:
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
///////////////////////////////////////////////////
|
///////////////////////////////////////////////////
|
//read status erase
|
//read status erase
|
///////////////////////////////////////////////////
|
///////////////////////////////////////////////////
|
if (Ers_queue[SecAddr]==1'b1)
|
if (Ers_queue[SecAddr]==1'b1)
|
begin
|
begin
|
Status[7] = 1'b0;
|
Status[7] = 1'b0;
|
Status[2] = ~Status[2]; //toggle
|
Status[2] = ~Status[2]; //toggle
|
end
|
end
|
else
|
else
|
Status[7] = 1'b1;
|
Status[7] = 1'b1;
|
Status[6] = ~Status[6]; //toggle
|
Status[6] = ~Status[6]; //toggle
|
Status[5] = 1'b0;
|
Status[5] = 1'b0;
|
Status[3] = 1'b1;
|
Status[3] = 1'b1;
|
DOut_zd = Status;
|
DOut_zd = Status;
|
end
|
end
|
end
|
end
|
|
|
ESP :
|
ESP :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
//read
|
//read
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
|
|
if (Ers_queue[SecAddr]!=1'b1)
|
if (Ers_queue[SecAddr]!=1'b1)
|
begin
|
begin
|
MemRead(DOut_zd);
|
MemRead(DOut_zd);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
///////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////
|
//read status
|
//read status
|
///////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////
|
Status[7] = 1'b1;
|
Status[7] = 1'b1;
|
// Status[6) No toggle
|
// Status[6) No toggle
|
Status[5] = 1'b0;
|
Status[5] = 1'b0;
|
Status[2] = ~Status[2]; //toggle
|
Status[2] = ~Status[2]; //toggle
|
DOut_zd = Status;
|
DOut_zd = Status;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
PGMS :
|
PGMS :
|
begin
|
begin
|
if (oe)
|
if (oe)
|
begin
|
begin
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
//read status
|
//read status
|
///////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////
|
Status[6] = ~Status[6]; //toggle
|
Status[6] = ~Status[6]; //toggle
|
Status[5] = 1'b0;
|
Status[5] = 1'b0;
|
//Status[2) no toggle
|
//Status[2) no toggle
|
Status[1] = 1'b0;
|
Status[1] = 1'b0;
|
DOut_zd = Status;
|
DOut_zd = Status;
|
if (SecAddr == SA)
|
if (SecAddr == SA)
|
DOut_zd[7] = Status[7];
|
DOut_zd[7] = Status[7];
|
else
|
else
|
DOut_zd[7] = ~Status[7];
|
DOut_zd[7] = ~Status[7];
|
end
|
end
|
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
always @(write or reseted)
|
always @(write or reseted)
|
begin : Output_generation
|
begin : Output_generation
|
if (reseted)
|
if (reseted)
|
begin
|
begin
|
case (current_state)
|
case (current_state)
|
RESET :
|
RESET :
|
begin
|
begin
|
ESP_ACT = 1'b0;
|
ESP_ACT = 1'b0;
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
OTP_ACT = 1'b0;
|
OTP_ACT = 1'b0;
|
if (~write)
|
if (~write)
|
if (A_PAT_2 && PATTERN_1)
|
if (A_PAT_2 && PATTERN_1)
|
AS_SecSi_FP = 1'b1;
|
AS_SecSi_FP = 1'b1;
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
end
|
end
|
|
|
Z001 :
|
Z001 :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_3 && PATTERN_2)
|
if (A_PAT_3 && PATTERN_2)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
end
|
end
|
|
|
PREL_SETBWB :
|
PREL_SETBWB :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
begin
|
begin
|
if (A_PAT_1 && (DataByte==16'h20))
|
if (A_PAT_1 && (DataByte==16'h20))
|
ULBYPASS = 1'b1;
|
ULBYPASS = 1'b1;
|
else if (A_PAT_1 && (DataByte==16'h90))
|
else if (A_PAT_1 && (DataByte==16'h90))
|
begin
|
begin
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
if (A_PAT_2)
|
if (A_PAT_2)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
if (AS_addr == 1'b0)
|
if (AS_addr == 1'b0)
|
begin
|
begin
|
AS_ID = 1'b1;
|
AS_ID = 1'b1;
|
AS_ID2= 1'b0;
|
AS_ID2= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
AS_ID = 1'b0;
|
AS_ID = 1'b0;
|
AS_ID2= 1'b1;
|
AS_ID2= 1'b1;
|
end
|
end
|
end
|
end
|
else if (A_PAT_1 && (DataByte==16'h88))
|
else if (A_PAT_1 && (DataByte==16'h88))
|
begin
|
begin
|
OTP_ACT = 1;
|
OTP_ACT = 1;
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
PREL_ULBYPASS :
|
PREL_ULBYPASS :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
begin
|
begin
|
ULBYPASS = 1'b1;
|
ULBYPASS = 1'b1;
|
if (A_PAT_1 && (DataByte==16'h90))
|
if (A_PAT_1 && (DataByte==16'h90))
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
end
|
end
|
end
|
end
|
|
|
PREL_ULBYPASS_RESET :
|
PREL_ULBYPASS_RESET :
|
if ((~write) && (DataByte != 16'h00 ))
|
if ((~write) && (DataByte != 16'h00 ))
|
ULBYPASS = 1'b1;
|
ULBYPASS = 1'b1;
|
|
|
OTP_A0SEEN :
|
OTP_A0SEEN :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
begin
|
begin
|
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
|
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
|
(Address >= 16'hFF00))
|
(Address >= 16'hFF00))
|
begin
|
begin
|
SecSiAddr = Address%(SecSiSize +1);
|
SecSiAddr = Address%(SecSiSize +1);
|
OTP_ACT = 1;
|
OTP_ACT = 1;
|
PSTART = 1'b1;
|
PSTART = 1'b1;
|
PSTART <= #1 1'b0;
|
PSTART <= #1 1'b0;
|
|
|
WBAddr = SecSiAddr;
|
WBAddr = SecSiAddr;
|
SA = SecAddr;
|
SA = SecAddr;
|
temp = DataByte;
|
temp = DataByte;
|
Status[7] = ~temp[7];
|
Status[7] = ~temp[7];
|
WBData = DataByte;
|
WBData = DataByte;
|
end
|
end
|
else
|
else
|
$display ("Invalid program address in SecSi region:"
|
$display ("Invalid program address in SecSi region:"
|
,Address);
|
,Address);
|
end
|
end
|
end
|
end
|
|
|
OTP_PREL :
|
OTP_PREL :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_1 && (DataByte==16'h90))
|
if (A_PAT_1 && (DataByte==16'h90))
|
begin
|
begin
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
if (A_PAT_2)
|
if (A_PAT_2)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
if (AS_addr == 1'b0)
|
if (AS_addr == 1'b0)
|
begin
|
begin
|
AS_ID = 1'b1;
|
AS_ID = 1'b1;
|
AS_ID2= 1'b0;
|
AS_ID2= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
AS_ID = 1'b0;
|
AS_ID = 1'b0;
|
AS_ID2= 1'b1;
|
AS_ID2= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
OTP_Z001 :
|
OTP_Z001 :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_3 && PATTERN_2)
|
if (A_PAT_3 && PATTERN_2)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
end
|
end
|
|
|
OTP :
|
OTP :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_2 && PATTERN_1)
|
if (A_PAT_2 && PATTERN_1)
|
AS_SecSi_FP = 1'b1;
|
AS_SecSi_FP = 1'b1;
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
RY_zd = 1;
|
RY_zd = 1;
|
end
|
end
|
|
|
AS :
|
AS :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (DataByte==16'hF0)
|
if (DataByte==16'hF0)
|
begin
|
begin
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
AS_ID = 1'b0;
|
AS_ID = 1'b0;
|
AS_ID2 = 1'b0;
|
AS_ID2 = 1'b0;
|
end
|
end
|
end
|
end
|
|
|
A0SEEN :
|
A0SEEN :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
begin
|
begin
|
PSTART = 1'b1;
|
PSTART = 1'b1;
|
PSTART <= #1 1'b0;
|
PSTART <= #1 1'b0;
|
WBData = DataByte;
|
WBData = DataByte;
|
WBAddr = Address;
|
WBAddr = Address;
|
SA = SecAddr;
|
SA = SecAddr;
|
Status[7] = ~DataByte[7];
|
Status[7] = ~DataByte[7];
|
end
|
end
|
end
|
end
|
|
|
C8 :
|
C8 :
|
begin
|
begin
|
end
|
end
|
|
|
C8_Z001 :
|
C8_Z001 :
|
begin
|
begin
|
end
|
end
|
|
|
C8_PREL :
|
C8_PREL :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_1 && (DataByte==16'h10))
|
if (A_PAT_1 && (DataByte==16'h10))
|
begin
|
begin
|
//Start Chip Erase
|
//Start Chip Erase
|
ESTART = 1'b1;
|
ESTART = 1'b1;
|
ESTART <= #1 1'b0;
|
ESTART <= #1 1'b0;
|
ESUSP = 1'b0;
|
ESUSP = 1'b0;
|
ERES = 1'b0;
|
ERES = 1'b0;
|
Ers_queue = ~(0);
|
Ers_queue = ~(0);
|
Status = 8'b00001000;
|
Status = 8'b00001000;
|
end
|
end
|
else if (DataByte==16'h30)
|
else if (DataByte==16'h30)
|
begin
|
begin
|
//put selected sector to sec. ers. queue
|
//put selected sector to sec. ers. queue
|
//start timeout
|
//start timeout
|
Ers_queue = 0;
|
Ers_queue = 0;
|
Ers_queue[SecAddr] = 1'b1;
|
Ers_queue[SecAddr] = 1'b1;
|
disable TCTMOUTr;
|
disable TCTMOUTr;
|
CTMOUT_in = 1'b0;
|
CTMOUT_in = 1'b0;
|
#1 CTMOUT_in <= 1'b1;
|
#1 CTMOUT_in <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
ERS :
|
ERS :
|
begin
|
begin
|
end
|
end
|
|
|
SERS :
|
SERS :
|
begin
|
begin
|
if (~write && ~CTMOUT)
|
if (~write && ~CTMOUT)
|
begin
|
begin
|
if (DataByte == 16'hB0)
|
if (DataByte == 16'hB0)
|
begin
|
begin
|
//need to start erase process prior to suspend
|
//need to start erase process prior to suspend
|
ESTART = 1'b1;
|
ESTART = 1'b1;
|
ESTART = #1 1'b0;
|
ESTART = #1 1'b0;
|
ESUSP = #1 1'b0;
|
ESUSP = #1 1'b0;
|
ESUSP = #1 1'b1;
|
ESUSP = #1 1'b1;
|
ESUSP <= #2 1'b0;
|
ESUSP <= #2 1'b0;
|
ERES = 1'b0;
|
ERES = 1'b0;
|
end
|
end
|
else if (DataByte==16'h30)
|
else if (DataByte==16'h30)
|
begin
|
begin
|
disable TCTMOUTr;
|
disable TCTMOUTr;
|
CTMOUT_in = 1'b0;
|
CTMOUT_in = 1'b0;
|
#1 CTMOUT_in <= 1'b1;
|
#1 CTMOUT_in <= 1'b1;
|
Ers_queue[SecAddr] = 1'b1;
|
Ers_queue[SecAddr] = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
SERS_EXEC :
|
SERS_EXEC :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (~EDONE && (EERR!=1'b1) && DataByte==16'hB0)
|
if (~EDONE && (EERR!=1'b1) && DataByte==16'hB0)
|
START_T1_in = 1'b1;
|
START_T1_in = 1'b1;
|
end
|
end
|
|
|
ESP :
|
ESP :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
begin
|
begin
|
if (A_PAT_2 && PATTERN_1)
|
if (A_PAT_2 && PATTERN_1)
|
AS_SecSi_FP = 1'b1;
|
AS_SecSi_FP = 1'b1;
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
if (DataByte == 16'h30)
|
if (DataByte == 16'h30)
|
begin
|
begin
|
ERES = 1'b1;
|
ERES = 1'b1;
|
ERES <= #1 1'b0;
|
ERES <= #1 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
ESP_Z001 :
|
ESP_Z001 :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_3 && PATTERN_2)
|
if (A_PAT_3 && PATTERN_2)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
end
|
end
|
|
|
ESP_PREL :
|
ESP_PREL :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
if (A_PAT_1 && (DataByte==16'h90))
|
if (A_PAT_1 && (DataByte==16'h90))
|
begin
|
begin
|
ULBYPASS = 1'b0;
|
ULBYPASS = 1'b0;
|
if (A_PAT_2)
|
if (A_PAT_2)
|
begin
|
begin
|
end
|
end
|
else
|
else
|
AS_SecSi_FP = 1'b0;
|
AS_SecSi_FP = 1'b0;
|
if (AS_addr == 1'b0)
|
if (AS_addr == 1'b0)
|
begin
|
begin
|
AS_ID = 1'b1;
|
AS_ID = 1'b1;
|
AS_ID2= 1'b0;
|
AS_ID2= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
AS_ID = 1'b0;
|
AS_ID = 1'b0;
|
AS_ID2= 1'b1;
|
AS_ID2= 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
ESP_A0SEEN :
|
ESP_A0SEEN :
|
begin
|
begin
|
if (~write)
|
if (~write)
|
begin
|
begin
|
ESP_ACT = 1'b1;
|
ESP_ACT = 1'b1;
|
PSTART = 1'b1;
|
PSTART = 1'b1;
|
PSTART <= #1 1'b0;
|
PSTART <= #1 1'b0;
|
WBData = DataByte;
|
WBData = DataByte;
|
WBAddr = Address;
|
WBAddr = Address;
|
SA = SecAddr;
|
SA = SecAddr;
|
Status[7] = ~DataByte[7];
|
Status[7] = ~DataByte[7];
|
end
|
end
|
end
|
end
|
|
|
ESP_AS :
|
ESP_AS :
|
begin
|
begin
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
initial
|
initial
|
begin
|
begin
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
//CFI array data
|
//CFI array data
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
|
|
//CFI query identification string
|
//CFI query identification string
|
for (i=16;i<92;i=i+1)
|
for (i=16;i<92;i=i+1)
|
CFI_array[i] = -1;
|
CFI_array[i] = -1;
|
|
|
CFI_array[16'h10] = 16'h51;
|
CFI_array[16'h10] = 16'h51;
|
CFI_array[16'h11] = 16'h52;
|
CFI_array[16'h11] = 16'h52;
|
CFI_array[16'h12] = 16'h59;
|
CFI_array[16'h12] = 16'h59;
|
CFI_array[16'h13] = 16'h02;
|
CFI_array[16'h13] = 16'h02;
|
CFI_array[16'h14] = 16'h00;
|
CFI_array[16'h14] = 16'h00;
|
CFI_array[16'h15] = 16'h40;
|
CFI_array[16'h15] = 16'h40;
|
CFI_array[16'h16] = 16'h00;
|
CFI_array[16'h16] = 16'h00;
|
CFI_array[16'h17] = 16'h00;
|
CFI_array[16'h17] = 16'h00;
|
CFI_array[16'h18] = 16'h00;
|
CFI_array[16'h18] = 16'h00;
|
CFI_array[16'h19] = 16'h00;
|
CFI_array[16'h19] = 16'h00;
|
CFI_array[16'h1A] = 16'h00;
|
CFI_array[16'h1A] = 16'h00;
|
|
|
//system interface string
|
//system interface string
|
CFI_array[16'h1B] = 16'h27;
|
CFI_array[16'h1B] = 16'h27;
|
CFI_array[16'h1C] = 16'h36;
|
CFI_array[16'h1C] = 16'h36;
|
CFI_array[16'h1D] = 16'h00;
|
CFI_array[16'h1D] = 16'h00;
|
CFI_array[16'h1E] = 16'h00;
|
CFI_array[16'h1E] = 16'h00;
|
CFI_array[16'h1F] = 16'h04;
|
CFI_array[16'h1F] = 16'h04;
|
CFI_array[16'h20] = 16'h00;
|
CFI_array[16'h20] = 16'h00;
|
CFI_array[16'h21] = 16'h0A;
|
CFI_array[16'h21] = 16'h0A;
|
CFI_array[16'h22] = 16'h00;
|
CFI_array[16'h22] = 16'h00;
|
CFI_array[16'h23] = 16'h05;
|
CFI_array[16'h23] = 16'h05;
|
CFI_array[16'h24] = 16'h00;
|
CFI_array[16'h24] = 16'h00;
|
CFI_array[16'h25] = 16'h04;
|
CFI_array[16'h25] = 16'h04;
|
CFI_array[16'h26] = 16'h00;
|
CFI_array[16'h26] = 16'h00;
|
//device geometry definition
|
//device geometry definition
|
CFI_array[16'h27] = 16'h16;
|
CFI_array[16'h27] = 16'h16;
|
CFI_array[16'h28] = 16'h00;
|
CFI_array[16'h28] = 16'h00;
|
CFI_array[16'h29] = 16'h00;
|
CFI_array[16'h29] = 16'h00;
|
CFI_array[16'h2A] = 16'h00;
|
CFI_array[16'h2A] = 16'h00;
|
CFI_array[16'h2B] = 16'h00;
|
CFI_array[16'h2B] = 16'h00;
|
CFI_array[16'h2C] = 16'h01;
|
CFI_array[16'h2C] = 16'h01;
|
CFI_array[16'h2D] = 16'h3F;
|
CFI_array[16'h2D] = 16'h3F;
|
CFI_array[16'h2E] = 16'h00;
|
CFI_array[16'h2E] = 16'h00;
|
CFI_array[16'h2F] = 16'h00;
|
CFI_array[16'h2F] = 16'h00;
|
CFI_array[16'h30] = 16'h01;
|
CFI_array[16'h30] = 16'h01;
|
CFI_array[16'h31] = 16'h00;
|
CFI_array[16'h31] = 16'h00;
|
CFI_array[16'h32] = 16'h00;
|
CFI_array[16'h32] = 16'h00;
|
CFI_array[16'h33] = 16'h00;
|
CFI_array[16'h33] = 16'h00;
|
CFI_array[16'h34] = 16'h00;
|
CFI_array[16'h34] = 16'h00;
|
CFI_array[16'h35] = 16'h00;
|
CFI_array[16'h35] = 16'h00;
|
CFI_array[16'h36] = 16'h00;
|
CFI_array[16'h36] = 16'h00;
|
CFI_array[16'h37] = 16'h00;
|
CFI_array[16'h37] = 16'h00;
|
CFI_array[16'h38] = 16'h00;
|
CFI_array[16'h38] = 16'h00;
|
CFI_array[16'h39] = 16'h00;
|
CFI_array[16'h39] = 16'h00;
|
CFI_array[16'h3A] = 16'h00;
|
CFI_array[16'h3A] = 16'h00;
|
CFI_array[16'h3B] = 16'h00;
|
CFI_array[16'h3B] = 16'h00;
|
CFI_array[16'h3C] = 16'h00;
|
CFI_array[16'h3C] = 16'h00;
|
|
|
//primary vendor-specific extended query
|
//primary vendor-specific extended query
|
CFI_array[16'h40] = 16'h50;
|
CFI_array[16'h40] = 16'h50;
|
CFI_array[16'h41] = 16'h52;
|
CFI_array[16'h41] = 16'h52;
|
CFI_array[16'h42] = 16'h49;
|
CFI_array[16'h42] = 16'h49;
|
CFI_array[16'h43] = 16'h31;
|
CFI_array[16'h43] = 16'h31;
|
CFI_array[16'h44] = 16'h31;
|
CFI_array[16'h44] = 16'h31;
|
CFI_array[16'h45] = 16'h01;
|
CFI_array[16'h45] = 16'h01;
|
CFI_array[16'h46] = 16'h02;
|
CFI_array[16'h46] = 16'h02;
|
CFI_array[16'h47] = 16'h01;
|
CFI_array[16'h47] = 16'h01;
|
CFI_array[16'h48] = 16'h01;
|
CFI_array[16'h48] = 16'h01;
|
CFI_array[16'h49] = 16'h04;
|
CFI_array[16'h49] = 16'h04;
|
CFI_array[16'h4A] = 16'h00;
|
CFI_array[16'h4A] = 16'h00;
|
CFI_array[16'h4B] = 16'h00;
|
CFI_array[16'h4B] = 16'h00;
|
CFI_array[16'h4C] = 16'h00;
|
CFI_array[16'h4C] = 16'h00;
|
CFI_array[16'h4D] = 16'hB5;
|
CFI_array[16'h4D] = 16'hB5;
|
CFI_array[16'h4E] = 16'hC5;
|
CFI_array[16'h4E] = 16'hC5;
|
CFI_array[16'h4F] = 16'h00;
|
CFI_array[16'h4F] = 16'h00;
|
|
|
end
|
end
|
|
|
always @(current_state or reseted)
|
always @(current_state or reseted)
|
begin
|
begin
|
if (reseted)
|
if (reseted)
|
if (current_state==RESET) RY_zd = 1'b1;
|
if (current_state==RESET) RY_zd = 1'b1;
|
if (current_state==PREL_ULBYPASS) RY_zd = 1'b1;
|
if (current_state==PREL_ULBYPASS) RY_zd = 1'b1;
|
if (current_state==A0SEEN) RY_zd = 1'b1;
|
if (current_state==A0SEEN) RY_zd = 1'b1;
|
if (current_state==ERS) RY_zd = 1'b0;
|
if (current_state==ERS) RY_zd = 1'b0;
|
if (current_state==SERS) RY_zd = 1'b0;
|
if (current_state==SERS) RY_zd = 1'b0;
|
if (current_state==ESPS) RY_zd = 1'b0;
|
if (current_state==ESPS) RY_zd = 1'b0;
|
if (current_state==SERS_EXEC) RY_zd = 1'b0;
|
if (current_state==SERS_EXEC) RY_zd = 1'b0;
|
if (current_state==ESP) RY_zd = 1'b1;
|
if (current_state==ESP) RY_zd = 1'b1;
|
if (current_state==OTP) RY_zd = 1'b1;
|
if (current_state==OTP) RY_zd = 1'b1;
|
if (current_state==ESP_A0SEEN) RY_zd = 1'b1;
|
if (current_state==ESP_A0SEEN) RY_zd = 1'b1;
|
if (current_state==PGMS) RY_zd = 1'b0;
|
if (current_state==PGMS) RY_zd = 1'b0;
|
end
|
end
|
|
|
always @(EERR or EDONE or current_state)
|
always @(EERR or EDONE or current_state)
|
begin : ERS2
|
begin : ERS2
|
integer i;
|
integer i;
|
integer j;
|
integer j;
|
if (current_state==ERS && EERR!=1'b1)
|
if (current_state==ERS && EERR!=1'b1)
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
begin
|
begin
|
if (Sec_Prot[i]!=1'b1)
|
if (Sec_Prot[i]!=1'b1)
|
for (j=0;j<=SecSize;j=j+1)
|
for (j=0;j<=SecSize;j=j+1)
|
Mem[sa(i)+j] = -1;
|
Mem[sa(i)+j] = -1;
|
end
|
end
|
if (current_state==ERS && EDONE)
|
if (current_state==ERS && EDONE)
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
begin
|
begin
|
if (Sec_Prot[i]!=1'b1)
|
if (Sec_Prot[i]!=1'b1)
|
for (j=0;j<=SecSize;j=j+1)
|
for (j=0;j<=SecSize;j=j+1)
|
Mem[sa(i)+j] = MaxData;
|
Mem[sa(i)+j] = MaxData;
|
end
|
end
|
end
|
end
|
|
|
always @(CTMOUT or current_state)
|
always @(CTMOUT or current_state)
|
begin : SERS2
|
begin : SERS2
|
if (current_state==SERS && CTMOUT)
|
if (current_state==SERS && CTMOUT)
|
begin
|
begin
|
CTMOUT_in = 1'b0;
|
CTMOUT_in = 1'b0;
|
START_T1_in = 1'b0;
|
START_T1_in = 1'b0;
|
ESTART = 1'b1;
|
ESTART = 1'b1;
|
ESTART <= #1 1'b0;
|
ESTART <= #1 1'b0;
|
ESUSP = 1'b0;
|
ESUSP = 1'b0;
|
ERES = 1'b0;
|
ERES = 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(START_T1 or current_state)
|
always @(START_T1 or current_state)
|
begin : ESPS2
|
begin : ESPS2
|
if (current_state==ESPS && START_T1)
|
if (current_state==ESPS && START_T1)
|
begin
|
begin
|
ESP_ACT = 1'b1;
|
ESP_ACT = 1'b1;
|
START_T1_in = 1'b0;
|
START_T1_in = 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(EERR or EDONE or current_state)
|
always @(EERR or EDONE or current_state)
|
begin: SERS_EXEC2
|
begin: SERS_EXEC2
|
integer i,j;
|
integer i,j;
|
if (current_state==SERS_EXEC)
|
if (current_state==SERS_EXEC)
|
begin
|
begin
|
if (EERR!=1'b1)
|
if (EERR!=1'b1)
|
begin
|
begin
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
begin
|
begin
|
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
|
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
|
for (j=0;j<=SecSize;j=j+1)
|
for (j=0;j<=SecSize;j=j+1)
|
Mem[sa(i)+j] = -1;
|
Mem[sa(i)+j] = -1;
|
|
|
if (EDONE)
|
if (EDONE)
|
for (i=0;i<=SecNum;i=i+1)
|
for (i=0;i<=SecNum;i=i+1)
|
begin
|
begin
|
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
|
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
|
for (j=0;j<=SecSize;j=j+1)
|
for (j=0;j<=SecSize;j=j+1)
|
Mem[sa(i)+j] = MaxData;
|
Mem[sa(i)+j] = MaxData;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(current_state or posedge PDONE)
|
always @(current_state or posedge PDONE)
|
begin: PGMS2
|
begin: PGMS2
|
integer i,j;
|
integer i,j;
|
if (current_state==PGMS)
|
if (current_state==PGMS)
|
begin
|
begin
|
if (PERR!=1'b1)
|
if (PERR!=1'b1)
|
begin
|
begin
|
new_int = WBData;
|
new_int = WBData;
|
if (OTP_ACT!=1'b1) //mem write
|
if (OTP_ACT!=1'b1) //mem write
|
old_int=Mem[sa(SA) + WBAddr];
|
old_int=Mem[sa(SA) + WBAddr];
|
else
|
else
|
old_int=SecSi[WBAddr];
|
old_int=SecSi[WBAddr];
|
new_bit = new_int;
|
new_bit = new_int;
|
if (old_int>-1)
|
if (old_int>-1)
|
begin
|
begin
|
old_bit = old_int;
|
old_bit = old_int;
|
for(j=0;j<=7;j=j+1)
|
for(j=0;j<=7;j=j+1)
|
if (~old_bit[j])
|
if (~old_bit[j])
|
new_bit[j]=1'b0;
|
new_bit[j]=1'b0;
|
new_int=new_bit;
|
new_int=new_bit;
|
end
|
end
|
WBData = new_int;
|
WBData = new_int;
|
if (OTP_ACT!=1'b1) //mem write
|
if (OTP_ACT!=1'b1) //mem write
|
Mem[sa(SA) + WBAddr] = -1;
|
Mem[sa(SA) + WBAddr] = -1;
|
else
|
else
|
SecSi[WBAddr] = -1;
|
SecSi[WBAddr] = -1;
|
if (PDONE && ~PSTART)
|
if (PDONE && ~PSTART)
|
begin
|
begin
|
if (OTP_ACT!=1'b1) //mem write
|
if (OTP_ACT!=1'b1) //mem write
|
Mem[sa(SA) + WBAddr] = WBData;
|
Mem[sa(SA) + WBAddr] = WBData;
|
else
|
else
|
SecSi[WBAddr] = WBData;
|
SecSi[WBAddr] = WBData;
|
WBData= -1;
|
WBData= -1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(gOE_n or gCE_n or RESETNeg or RST )
|
always @(gOE_n or gCE_n or RESETNeg or RST )
|
begin
|
begin
|
//Output Disable Control
|
//Output Disable Control
|
if (gOE_n || gCE_n || (~RESETNeg && ~RST))
|
if (gOE_n || gCE_n || (~RESETNeg && ~RST))
|
DOut_zd = 8'bZ;
|
DOut_zd = 8'bZ;
|
end
|
end
|
|
|
reg BuffInOE , BuffInCE , BuffInADDR;
|
reg BuffInOE , BuffInCE , BuffInADDR;
|
wire BuffOutOE, BuffOutCE, BuffOutADDR;
|
wire BuffOutOE, BuffOutCE, BuffOutADDR;
|
|
|
BUFFER BUFOE (BuffOutOE, BuffInOE);
|
BUFFER BUFOE (BuffOutOE, BuffInOE);
|
BUFFER BUFCE (BuffOutCE, BuffInCE);
|
BUFFER BUFCE (BuffOutCE, BuffInCE);
|
BUFFER BUFADDR (BuffOutADDR, BuffInADDR);
|
BUFFER BUFADDR (BuffOutADDR, BuffInADDR);
|
initial
|
initial
|
begin
|
begin
|
BuffInOE = 1'b1;
|
BuffInOE = 1'b1;
|
BuffInCE = 1'b1;
|
BuffInCE = 1'b1;
|
BuffInADDR = 1'b1;
|
BuffInADDR = 1'b1;
|
end
|
end
|
|
|
always @(posedge BuffOutOE)
|
always @(posedge BuffOutOE)
|
begin
|
begin
|
OEDQ_01 = $time;
|
OEDQ_01 = $time;
|
end
|
end
|
always @(posedge BuffOutCE)
|
always @(posedge BuffOutCE)
|
begin
|
begin
|
CEDQ_01 = $time;
|
CEDQ_01 = $time;
|
end
|
end
|
always @(posedge BuffOutADDR)
|
always @(posedge BuffOutADDR)
|
begin
|
begin
|
ADDRDQ_01 = $time;
|
ADDRDQ_01 = $time;
|
end
|
end
|
|
|
function integer sa;
|
function integer sa;
|
input [7:0] sect;
|
input [7:0] sect;
|
begin
|
begin
|
sa = sect * (SecSize + 1);
|
sa = sect * (SecSize + 1);
|
end
|
end
|
endfunction
|
endfunction
|
|
|
task MemRead;
|
task MemRead;
|
inout[7:0] DOut_zd;
|
inout[7:0] DOut_zd;
|
begin
|
begin
|
if (Mem[sa(SecAddr)+Address]==-1)
|
if (Mem[sa(SecAddr)+Address]==-1)
|
DOut_zd = 8'bx;
|
DOut_zd = 8'bx;
|
else
|
else
|
DOut_zd = Mem[sa(SecAddr)+Address];
|
DOut_zd = Mem[sa(SecAddr)+Address];
|
end
|
end
|
endtask
|
endtask
|
endmodule
|
endmodule
|
|
|
module BUFFER (OUT,IN);
|
module BUFFER (OUT,IN);
|
input IN;
|
input IN;
|
output OUT;
|
output OUT;
|
buf ( OUT, IN);
|
buf ( OUT, IN);
|
endmodule
|
endmodule
|
|
|