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https://opencores.org/ocsvn/wb_async_mem_bridge/wb_async_mem_bridge/trunk
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Rev 6 |
// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module tb_dut(
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module tb_dut(
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input tb_clk,
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input tb_clk,
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input tb_rst
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input tb_rst
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// async_mem_master
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// async_mem_master
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wire [31:0] mem_d;
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wire [31:0] mem_d;
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wire [31:0] mem_a;
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wire [31:0] mem_a;
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wire mem_oe_n;
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wire mem_oe_n;
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wire [3:0] mem_bls_n;
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wire [3:0] mem_bls_n;
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wire mem_we_n;
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wire mem_we_n;
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wire mem_cs_n;
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wire mem_cs_n;
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async_mem_master
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async_mem_master
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async_mem(
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async_mem(
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.mem_d(mem_d),
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.mem_d(mem_d),
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.mem_a(mem_a),
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.mem_a(mem_a),
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.mem_oe_n(mem_oe_n),
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.mem_oe_n(mem_oe_n),
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.mem_bls_n(mem_bls_n),
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.mem_bls_n(mem_bls_n),
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.mem_we_n(mem_we_n),
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.mem_we_n(mem_we_n),
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.mem_cs_n(mem_cs_n),
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.mem_cs_n(mem_cs_n),
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.tb_clk(tb_clk),
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.tb_clk(tb_clk),
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.tb_rst(tb_rst)
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.tb_rst(tb_rst)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// wb_async_mem_bridge
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// wb_async_mem_bridge
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wire [31:0] wb_data_i;
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wire [31:0] wb_data_i;
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wire [31:0] wb_data_o;
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wire [31:0] wb_data_o;
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wire [31:0] wb_addr_o;
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wire [31:0] wb_addr_o;
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wire [3:0] wb_sel_o;
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wire [3:0] wb_sel_o;
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wire wb_we_o;
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wire wb_we_o;
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wire wb_cyc_o;
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wire wb_cyc_o;
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wire wb_stb_o;
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wire wb_stb_o;
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wire wb_ack_i;
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wire wb_ack_i;
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wire wb_err_i;
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wire wb_err_i;
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wire wb_rty_i;
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wire wb_rty_i;
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wb_async_mem_bridge
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wb_async_mem_bridge
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i_wb_async_mem_bridge(
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i_wb_async_mem_bridge(
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.wb_data_i(wb_data_i),
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.wb_data_i(wb_data_i),
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.wb_data_o(wb_data_o),
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.wb_data_o(wb_data_o),
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.wb_addr_o(wb_addr_o),
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.wb_addr_o(wb_addr_o),
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.wb_sel_o(wb_sel_o),
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.wb_sel_o(wb_sel_o),
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.wb_we_o(wb_we_o),
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.wb_we_o(wb_we_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_stb_o(wb_stb_o),
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.wb_stb_o(wb_stb_o),
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.wb_ack_i(wb_ack_i),
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.wb_ack_i(wb_ack_i),
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.wb_err_i(wb_err_i),
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.wb_err_i(wb_err_i),
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.wb_rty_i(wb_rty_i),
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.wb_rty_i(wb_rty_i),
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.mem_d(mem_d),
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.mem_d(mem_d),
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.mem_a(mem_a),
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.mem_a(mem_a),
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.mem_oe_n(mem_oe_n),
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.mem_oe_n(mem_oe_n),
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.mem_bls_n(mem_bls_n),
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.mem_bls_n(mem_bls_n),
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.mem_we_n(mem_we_n),
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.mem_we_n(mem_we_n),
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.mem_cs_n(mem_cs_n),
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.mem_cs_n(mem_cs_n),
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.wb_clk_i(tb_clk),
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.wb_clk_i(tb_clk),
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.wb_rst_i(tb_rst)
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.wb_rst_i(tb_rst)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// wb_slave_model
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// wb_slave_model
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wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
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wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
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i_wb_slave_model(
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i_wb_slave_model(
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.clk_i(tb_clk),
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.clk_i(tb_clk),
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.rst_i(tb_rst),
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.rst_i(tb_rst),
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.dat_o(wb_data_i),
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.dat_o(wb_data_i),
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.dat_i(wb_data_o),
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.dat_i(wb_data_o),
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.adr_i(wb_addr_o),
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.adr_i(wb_addr_o),
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.cyc_i(wb_cyc_o),
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.cyc_i(wb_cyc_o),
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.stb_i(wb_stb_o),
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.stb_i(wb_stb_o),
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.we_i(wb_we_o),
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.we_i(wb_we_o),
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.sel_i(wb_sel_o),
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.sel_i(wb_sel_o),
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.ack_o(wb_ack_i),
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.ack_o(wb_ack_i),
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.err_o(wb_err_i),
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.err_o(wb_err_i),
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.rty_o(wb_rty_i)
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.rty_o(wb_rty_i)
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);
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);
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endmodule
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endmodule
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