// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module tb_top();
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module tb_top();
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parameter CLK_PERIOD = 10;
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parameter CLK_PERIOD = 10;
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reg tb_clk, tb_rst;
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reg tb_clk, tb_rst;
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initial
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initial
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begin
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begin
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tb_clk <= 1'b1;
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tb_clk <= 1'b1;
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tb_rst <= 1'b1;
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tb_rst <= 1'b1;
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#(CLK_PERIOD); #(CLK_PERIOD/3);
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#(CLK_PERIOD); #(CLK_PERIOD/3);
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tb_rst = 1'b0;
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tb_rst = 1'b0;
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end
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end
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always
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always
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#(CLK_PERIOD/2) tb_clk = ~tb_clk;
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#(CLK_PERIOD/2) tb_clk = ~tb_clk;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// tb_dut
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// tb_dut
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tb_dut dut( tb_clk, tb_rst );
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tb_dut dut( tb_clk, tb_rst );
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// insert test below
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// insert test below
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initial
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initial
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begin
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begin
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wait( ~tb_rst );
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wait( ~tb_rst );
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repeat(2) @(posedge tb_clk);
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repeat(2) @(posedge tb_clk);
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//
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//
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$display("\n^^^- \n");
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$display("\n^^^- \n");
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dut.async_mem.async_mem_write( 32'h83000000, 32'habbabeef, 4'b0000 );
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dut.async_mem.async_mem_write( 32'h83000000, 32'habbabeef, 4'b0000 );
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repeat(10) @(posedge tb_clk);
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repeat(10) @(posedge tb_clk);
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dut.async_mem.async_mem_cmp( 32'h83000000, 32'habbabeef, 4'b0000 );
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dut.async_mem.async_mem_cmp( 32'h83000000, 32'habbabeef, 4'b0000 );
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repeat(10) @(posedge tb_clk);
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repeat(10) @(posedge tb_clk);
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dut.async_mem.async_mem_3x_write( 32'h83000000, 32'habbabeef, 32'h55555555, 32'haaaaaaaa, 4'b0000 );
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dut.async_mem.async_mem_3x_write( 32'h83000000, 32'habbabeef, 32'h55555555, 32'haaaaaaaa, 4'b0000 );
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repeat(10) @(posedge tb_clk);
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repeat(10) @(posedge tb_clk);
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dut.async_mem.async_mem_3x_cmp( 32'h83000000, 32'habbabeef, 32'h55555555, 32'haaaaaaaa, 4'b0000 );
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dut.async_mem.async_mem_3x_cmp( 32'h83000000, 32'habbabeef, 32'h55555555, 32'haaaaaaaa, 4'b0000 );
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repeat(10) @(posedge tb_clk);
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repeat(10) @(posedge tb_clk);
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$display("\n^^^---------------------------------\n");
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$display("\n^^^---------------------------------\n");
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$display("^^^- Testbench done. %t.\n", $time);
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$display("^^^- Testbench done. %t.\n", $time);
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$stop();
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$stop();
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end
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end
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endmodule
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endmodule
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