// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
//
|
//
|
// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
|
|
|
|
module soc_ram( data, addr, we, clk, q );
|
module soc_ram( data, addr, we, clk, q );
|
|
|
parameter DATA_WIDTH = 8;
|
parameter DATA_WIDTH = 8;
|
parameter ADDR_WIDTH = 6;
|
parameter ADDR_WIDTH = 6;
|
parameter MEM_INIT = 0;
|
parameter MEM_INIT = 0;
|
|
|
input [(DATA_WIDTH-1):0] data;
|
input [(DATA_WIDTH-1):0] data;
|
input [(ADDR_WIDTH-1):0] addr;
|
input [(ADDR_WIDTH-1):0] addr;
|
input we;
|
input we;
|
input clk;
|
input clk;
|
output [(DATA_WIDTH-1):0] q;
|
output [(DATA_WIDTH-1):0] q;
|
|
|
// Declare the RAM variable
|
// Declare the RAM variable
|
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
reg [ADDR_WIDTH-1:0] addr_reg;
|
reg [ADDR_WIDTH-1:0] addr_reg;
|
|
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
// Write
|
// Write
|
if (we) ram[addr] <= data;
|
if (we) ram[addr] <= data;
|
addr_reg <= addr;
|
addr_reg <= addr;
|
end
|
end
|
|
|
// Read returns NEW data at addr if we == 1'b1. This is the
|
// Read returns NEW data at addr if we == 1'b1. This is the
|
// natural behavior of TriMatrix memory blocks in Single Port
|
// natural behavior of TriMatrix memory blocks in Single Port
|
// mode
|
// mode
|
assign q = ram[addr_reg];
|
assign q = ram[addr_reg];
|
|
|
// generate
|
// generate
|
// if( MEM_INIT != 0 )
|
// if( MEM_INIT != 0 )
|
// initial
|
// initial
|
// $readmemh( MEM_INIT, ram );
|
// $readmemh( MEM_INIT, ram );
|
// endgenerate
|
// endgenerate
|
|
|
|
|
