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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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module sync_edge_detect (
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module sync_edge_detect (
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input async_sig,
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input async_sig,
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output sync_out,
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output sync_out,
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input clk,
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input clk,
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output reg rise,
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output reg rise,
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output reg fall
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output reg fall
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);
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);
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reg [1:3] resync;
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reg [1:3] resync;
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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// detect rising and falling edges.
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// detect rising and falling edges.
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rise <= ~resync[3] & resync[2];
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rise <= ~resync[3] & resync[2];
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fall <= ~resync[2] & resync[3];
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fall <= ~resync[2] & resync[3];
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// update history shifter.
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// update history shifter.
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resync <= {async_sig , resync[1:2]};
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resync <= {async_sig , resync[1:2]};
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end
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end
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assign sync_out = resync[2];
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assign sync_out = resync[2];
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endmodule
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endmodule
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