// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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module top(
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module top(
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//////////////////////// Clock Input ////////////////////////
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//////////////////////// Clock Input ////////////////////////
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input [1:0] clock_24, // 24 MHz
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input [1:0] clock_24, // 24 MHz
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input [1:0] clock_27, // 27 MHz
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input [1:0] clock_27, // 27 MHz
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input clock_50, // 50 MHz
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input clock_50, // 50 MHz
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input ext_clock, // External Clock
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input ext_clock, // External Clock
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//////////////////////// Push Button ////////////////////////
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//////////////////////// Push Button ////////////////////////
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input [3:0] key, // Pushbutton[3:0]
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input [3:0] key, // Pushbutton[3:0]
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//////////////////////// DPDT Switch ////////////////////////
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//////////////////////// DPDT Switch ////////////////////////
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input [9:0] sw, // Toggle Switch[9:0]
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input [9:0] sw, // Toggle Switch[9:0]
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//////////////////////// 7-SEG Dispaly ////////////////////////
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//////////////////////// 7-SEG Dispaly ////////////////////////
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output [6:0] hex0, // Seven Segment Digit 0
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output [6:0] hex0, // Seven Segment Digit 0
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output [6:0] hex1, // Seven Segment Digit 1
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output [6:0] hex1, // Seven Segment Digit 1
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output [6:0] hex2, // Seven Segment Digit 2
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output [6:0] hex2, // Seven Segment Digit 2
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output [6:0] hex3, // Seven Segment Digit 3
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output [6:0] hex3, // Seven Segment Digit 3
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//////////////////////////// LED ////////////////////////////
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//////////////////////////// LED ////////////////////////////
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output [7:0] ledg, // LED Green[7:0]
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output [7:0] ledg, // LED Green[7:0]
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output [9:0] ledr, // LED Red[9:0]
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output [9:0] ledr, // LED Red[9:0]
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//////////////////////////// UART ////////////////////////////
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//////////////////////////// UART ////////////////////////////
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output uart_txd, // UART Transmitter
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output uart_txd, // UART Transmitter
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input uart_rxd, // UART Receiver
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input uart_rxd, // UART Receiver
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/////////////////////// SDRAM Interface ////////////////////////
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/////////////////////// SDRAM Interface ////////////////////////
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inout [15:0] dram_dq, // SDRAM Data bus 16 Bits
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inout [15:0] dram_dq, // SDRAM Data bus 16 Bits
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output [11:0] dram_addr, // SDRAM Address bus 12 Bits
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output [11:0] dram_addr, // SDRAM Address bus 12 Bits
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output dram_ldqm, // SDRAM Low-byte Data Mask
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output dram_ldqm, // SDRAM Low-byte Data Mask
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output dram_udqm, // SDRAM High-byte Data Mask
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output dram_udqm, // SDRAM High-byte Data Mask
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output dram_we_n, // SDRAM Write Enable
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output dram_we_n, // SDRAM Write Enable
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output dram_cas_n, // SDRAM Column Address Strobe
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output dram_cas_n, // SDRAM Column Address Strobe
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output dram_ras_n, // SDRAM Row Address Strobe
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output dram_ras_n, // SDRAM Row Address Strobe
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output dram_cs_n, // SDRAM Chip Select
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output dram_cs_n, // SDRAM Chip Select
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output dram_ba_0, // SDRAM Bank Address 0
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output dram_ba_0, // SDRAM Bank Address 0
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output dram_ba_1, // SDRAM Bank Address 0
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output dram_ba_1, // SDRAM Bank Address 0
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output dram_clk, // SDRAM Clock
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output dram_clk, // SDRAM Clock
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output dram_cke, // SDRAM Clock Enable
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output dram_cke, // SDRAM Clock Enable
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//////////////////////// Flash Interface ////////////////////////
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//////////////////////// Flash Interface ////////////////////////
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inout [7:0] fl_dq, // FLASH Data bus 8 Bits
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inout [7:0] fl_dq, // FLASH Data bus 8 Bits
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output [21:0] fl_addr, // FLASH Address bus 22 Bits
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output [21:0] fl_addr, // FLASH Address bus 22 Bits
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output fl_we_n, // FLASH Write Enable
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output fl_we_n, // FLASH Write Enable
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output fl_rst_n, // FLASH Reset
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output fl_rst_n, // FLASH Reset
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output fl_oe_n, // FLASH Output Enable
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output fl_oe_n, // FLASH Output Enable
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output fl_ce_n, // FLASH Chip Enable
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output fl_ce_n, // FLASH Chip Enable
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//////////////////////// SRAM Interface ////////////////////////
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//////////////////////// SRAM Interface ////////////////////////
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inout [15:0] sram_dq, // SRAM Data bus 16 Bits
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inout [15:0] sram_dq, // SRAM Data bus 16 Bits
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output [17:0] sram_addr, // SRAM Address bus 18 Bits
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output [17:0] sram_addr, // SRAM Address bus 18 Bits
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output sram_ub_n, // SRAM High-byte Data Mask
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output sram_ub_n, // SRAM High-byte Data Mask
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output sram_lb_n, // SRAM Low-byte Data Mask
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output sram_lb_n, // SRAM Low-byte Data Mask
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output sram_we_n, // SRAM Write Enable
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output sram_we_n, // SRAM Write Enable
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output sram_ce_n, // SRAM Chip Enable
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output sram_ce_n, // SRAM Chip Enable
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output sram_oe_n, // SRAM Output Enable
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output sram_oe_n, // SRAM Output Enable
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//////////////////// SD Card Interface ////////////////////////
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//////////////////// SD Card Interface ////////////////////////
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inout sd_dat, // SD Card Data
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inout sd_dat, // SD Card Data
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inout sd_dat3, // SD Card Data 3
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inout sd_dat3, // SD Card Data 3
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inout sd_cmd, // SD Card Command Signal
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inout sd_cmd, // SD Card Command Signal
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output sd_clk, // SD Card Clock
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output sd_clk, // SD Card Clock
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//////////////////////// I2C ////////////////////////////////
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//////////////////////// I2C ////////////////////////////////
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inout i2c_sdat, // I2C Data
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inout i2c_sdat, // I2C Data
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output i2c_sclk, // I2C Clock
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output i2c_sclk, // I2C Clock
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//////////////////////// PS2 ////////////////////////////////
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//////////////////////// PS2 ////////////////////////////////
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input ps2_dat, // PS2 Data
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input ps2_dat, // PS2 Data
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input ps2_clk, // PS2 Clock
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input ps2_clk, // PS2 Clock
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//////////////////// USB JTAG link ////////////////////////////
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//////////////////// USB JTAG link ////////////////////////////
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input tdi, // CPLD -> FPGA (data in)
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input tdi, // CPLD -> FPGA (data in)
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input tck, // CPLD -> FPGA (clk)
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input tck, // CPLD -> FPGA (clk)
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input tcs, // CPLD -> FPGA (CS)
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input tcs, // CPLD -> FPGA (CS)
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output tdo, // FPGA -> CPLD (data out)
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output tdo, // FPGA -> CPLD (data out)
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//////////////////////// VGA ////////////////////////////
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//////////////////////// VGA ////////////////////////////
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output vga_hs, // VGA H_SYNC
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output vga_hs, // VGA H_SYNC
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output vga_vs, // VGA V_SYNC
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output vga_vs, // VGA V_SYNC
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output [3:0] vga_r, // VGA Red[3:0]
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output [3:0] vga_r, // VGA Red[3:0]
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output [3:0] vga_g, // VGA Green[3:0]
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output [3:0] vga_g, // VGA Green[3:0]
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output [3:0] vga_b, // VGA Blue[3:0]
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output [3:0] vga_b, // VGA Blue[3:0]
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//////////////////// Audio CODEC ////////////////////////////
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//////////////////// Audio CODEC ////////////////////////////
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inout aud_adclrck, // Audio CODEC ADC LR Clock
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inout aud_adclrck, // Audio CODEC ADC LR Clock
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input aud_adcdat, // Audio CODEC ADC Data
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input aud_adcdat, // Audio CODEC ADC Data
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inout aud_daclrck, // Audio CODEC DAC LR Clock
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inout aud_daclrck, // Audio CODEC DAC LR Clock
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output aud_dacdat, // Audio CODEC DAC Data
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output aud_dacdat, // Audio CODEC DAC Data
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inout aud_bclk, // Audio CODEC Bit-Stream Clock
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inout aud_bclk, // Audio CODEC Bit-Stream Clock
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output aud_xck, // Audio CODEC Chip Clock
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output aud_xck, // Audio CODEC Chip Clock
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//////////////////////// GPIO ////////////////////////////////
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//////////////////////// GPIO ////////////////////////////////
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inout [35:0] gpio_0, // GPIO Connection 0
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inout [35:0] gpio_0, // GPIO Connection 0
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inout [35:0] gpio_1 // GPIO Connection 1
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inout [35:0] gpio_1 // GPIO Connection 1
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// system wires
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// system wires
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wire reset_switch;
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wire reset_switch;
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wire sysclk = clock_24[0];
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wire sysclk = clock_24[0];
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//---------------------------------------------------
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//---------------------------------------------------
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// sync reset
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// sync reset
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sync
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sync
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i_sync_reset(
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i_sync_reset(
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.async_sig(~key[0]),
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.async_sig(~key[0]),
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.sync_out(reset_switch),
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.sync_out(reset_switch),
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.clk(sysclk)
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.clk(sysclk)
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// FLED
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// FLED
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reg [24:0] counter;
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reg [24:0] counter;
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wire [7:0] fled;
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wire [7:0] fled;
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always @(posedge sysclk or posedge reset_switch)
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always @(posedge sysclk or posedge reset_switch)
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if(reset_switch)
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if(reset_switch)
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counter <= 25'b0;
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counter <= 25'b0;
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else
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else
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counter <= counter + 1;
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counter <= counter + 1;
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assign fled[0] = sw[0];
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assign fled[0] = sw[0];
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assign fled[1] = sw[1];
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assign fled[1] = sw[1];
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assign fled[2] = sw[2];
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assign fled[2] = sw[2];
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assign fled[3] = sw[3];
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assign fled[3] = sw[3];
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assign fled[4] = sw[4];
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assign fled[4] = sw[4];
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assign fled[5] = sw[5];
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assign fled[5] = sw[5];
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assign fled[6] = sw[6];
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assign fled[6] = sw[6];
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assign fled[7] = counter[24];
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assign fled[7] = counter[24];
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//---------------------------------------------------
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//---------------------------------------------------
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// test_harness
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// test_harness
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test_harness i_test_harness(
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test_harness i_test_harness(
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.gpio_0(gpio_0),
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.gpio_0(gpio_0),
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.gpio_1(gpio_1),
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.gpio_1(gpio_1),
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.sys_clk_i(sysclk),
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.sys_clk_i(sysclk),
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.sys_rst_i(reset_switch)
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.sys_rst_i(reset_switch)
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);
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);
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//---------------------------------------------------
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//---------------------------------------------------
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// outputs
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// outputs
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// Turn off all display
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// Turn off all display
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assign hex0 = 7'h7f;
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assign hex0 = 7'h7f;
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assign hex1 = 7'h7f;
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assign hex1 = 7'h7f;
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assign hex2 = 7'h7f;
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assign hex2 = 7'h7f;
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assign hex3 = 7'h7f;
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assign hex3 = 7'h7f;
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// assign ledg = 8'hff;
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// assign ledg = 8'hff;
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assign ledg = fled;
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assign ledg = fled;
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assign ledr = 10'h000;
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assign ledr = 10'h000;
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// All inout port turn to tri-state
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// All inout port turn to tri-state
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assign dram_dq = 16'hzzzz;
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assign dram_dq = 16'hzzzz;
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assign fl_dq = 8'hzz;
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assign fl_dq = 8'hzz;
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assign sram_dq = 16'hzzzz;
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assign sram_dq = 16'hzzzz;
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assign sd_dat = 1'bz;
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assign sd_dat = 1'bz;
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assign i2c_sdat = 1'bz;
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assign i2c_sdat = 1'bz;
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assign aud_adclrck = 1'bz;
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assign aud_adclrck = 1'bz;
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assign aud_daclrck = 1'bz;
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assign aud_daclrck = 1'bz;
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assign aud_bclk = 1'bz;
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assign aud_bclk = 1'bz;
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assign gpio_0 = 36'hzzzzzzzzz;
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assign gpio_0 = 36'hzzzzzzzzz;
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assign gpio_1 = 36'hzzzzzzzzz;
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assign gpio_1 = 36'hzzzzzzzzz;
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endmodule
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endmodule
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