#!/usr/bin/perl
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#!/usr/bin/perl
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#use POSIX;
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#use POSIX;
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use Tk;
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use Tk;
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use Time::Local;
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use Time::Local;
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#
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#
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# usage perl wishbone_gui.pl [-nogui] [wishbone.defines]
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# usage perl wishbone_gui.pl [-nogui] [wishbone.defines]
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#
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#
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#
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# description: users manual
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# description: users manual
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#
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my $infile = "wishbone.defines";
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my $infile = "wishbone.defines";
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my $outfile = wb;
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my $outfile = wb;
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my $a;
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my $a;
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my $i=0;
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my $i=0;
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my $j=0;
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my $j=0;
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# default settings
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# default settings
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my $syscon=syscon;
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my $syscon=syscon;
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my $intercon=intercon;
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my $intercon=intercon;
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my $target="generic";
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my $target="generic";
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my $hdl=vhdl;
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my $hdl=vhdl;
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my $ext=".vhd";
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my $ext=".vhd";
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my $signal_groups=0;
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my $signal_groups=0;
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my $comment="--";
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my $comment="--";
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my $dat_size=32;
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my $dat_size=32;
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my $adr_size=32;
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my $adr_size=32;
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my $tgd_bits=0;
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my $tgd_bits=0;
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my $tga_bits=2;
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my $tga_bits=2;
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my $tgc_bits=3;
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my $tgc_bits=3;
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my $rename_tgc="cti";
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my $rename_tgc="cti";
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my $rename_tga="bte";
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my $rename_tga="bte";
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my $rename_tgd="tgd";
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my $rename_tgd="tgd";
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my $classic="000";
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my $classic="000";
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my $endofburst="111";
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my $endofburst="111";
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my $interconnect="sharedbus";
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my $interconnect="sharedbus";
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my $mux_type="andor";
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my $mux_type="andor";
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my $optimize="speed";
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my $optimize="speed";
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my $priority="0";
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my $priority="0";
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# keep track of implementation size
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# keep track of implementation size
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my $masters=0;
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my $masters=0;
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my $slaves=0;
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my $slaves=0;
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my $rty_o=0;
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my $rty_o=0;
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my $rty_i=0;
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my $rty_i=0;
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my $err_o=0;
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my $err_o=0;
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my $err_i=0;
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my $err_i=0;
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my $tgc_o=0;
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my $tgc_o=0;
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my $tgc_i=0;
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my $tgc_i=0;
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my $tga_o=0;
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my $tga_o=0;
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my $tga_i=0;
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my $tga_i=0;
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# GUI FSM
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# GUI FSM
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my $state='WinGlobal';
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my $state='WinGlobal';
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my $next=0;
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my $next=0;
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my $back=0;
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my $back=0;
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my $amp=0;
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my $amp=0;
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my $asp=0;
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my $asp=0;
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my $del=0;
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my $del=0;
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my $i;
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my $i;
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# open input file
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# open input file
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#if (open(FILE,"<$file")) {
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#if (open(FILE,"<$file")) {
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# read in settings from infile
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# read in settings from infile
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sub master_init {
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sub master_init {
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$masters += 1;
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$masters += 1;
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$master[$masters]{"wbm"}=$_[0];
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$master[$masters]{"wbm"}=$_[0];
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$master[$masters]{"dat_size"}=$dat_size;
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$master[$masters]{"dat_size"}=$dat_size;
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$master[$masters]{"adr_size"}=$adr_size;
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$master[$masters]{"adr_size"}=$adr_size;
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$master[$masters]{"type"}="rw";
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$master[$masters]{"type"}="rw";
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$master[$masters]{"adr_o_hi"}=31;
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$master[$masters]{"adr_o_hi"}=31;
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$master[$masters]{"adr_o_lo"}=0;
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$master[$masters]{"adr_o_lo"}=0;
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$master[$masters]{"lock_o"}=0;
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$master[$masters]{"lock_o"}=0;
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$master[$masters]{"err_i"}=1;
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$master[$masters]{"err_i"}=1;
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$master[$masters]{"rty_i"}=1;
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$master[$masters]{"rty_i"}=1;
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$master[$masters]{"tga_o"}=0;
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$master[$masters]{"tga_o"}=0;
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$master[$masters]{"tgd_o"}=0;
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$master[$masters]{"tgd_o"}=0;
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$master[$masters]{"tgc_o"}=0;
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$master[$masters]{"tgc_o"}=0;
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$master[$masters]{"priority"}=1;
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$master[$masters]{"priority"}=1;
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};
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};
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sub slave_init {
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sub slave_init {
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$slaves += 1;
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$slaves += 1;
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$slave[$slaves]{"wbs"}=$_[0];
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$slave[$slaves]{"wbs"}=$_[0];
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$slave[$slaves]{"dat_size"}=$dat_size;
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$slave[$slaves]{"dat_size"}=$dat_size;
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$slave[$slaves]{"type"}="rw";
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$slave[$slaves]{"type"}="rw";
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$slave[$slaves]{"sel_i"}=1;
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$slave[$slaves]{"sel_i"}=1;
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$slave[$slaves]{"adr_i_hi"}=31;
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$slave[$slaves]{"adr_i_hi"}=31;
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$slave[$slaves]{"adr_i_lo"}=2;
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$slave[$slaves]{"adr_i_lo"}=2;
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$slave[$slaves]{"lock_i"}=0;
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$slave[$slaves]{"lock_i"}=0;
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$slave[$slaves]{"tgd_i"}=0;
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$slave[$slaves]{"tgd_i"}=0;
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$slave[$slaves]{"tga_i"}=0;
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$slave[$slaves]{"tga_i"}=0;
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$slave[$slaves]{"tgc_i"}=0;
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$slave[$slaves]{"tgc_i"}=0;
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$slave[$slaves]{"err_o"}=0;
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$slave[$slaves]{"err_o"}=0;
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$slave[$slaves]{"rty_o"}=0;
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$slave[$slaves]{"rty_o"}=0;
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$slave[$slaves]{"baseadr"}="00000000";
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$slave[$slaves]{"baseadr"}="00000000";
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$slave[$slaves]{"size"}="00100000";
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$slave[$slaves]{"size"}="00100000";
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$slave[$slaves]{"baseadr1"}="00000000";
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$slave[$slaves]{"baseadr1"}="00000000";
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$slave[$slaves]{"size1"}="ffffffff";
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$slave[$slaves]{"size1"}="ffffffff";
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$slave[$slaves]{"baseadr2"}="00000000";
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$slave[$slaves]{"baseadr2"}="00000000";
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$slave[$slaves]{"size2"}="ffffffff";
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$slave[$slaves]{"size2"}="ffffffff";
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$slave[$slaves]{"baseadr3"}="00000000";
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$slave[$slaves]{"baseadr3"}="00000000";
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$slave[$slaves]{"size3"}="ffffffff";
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$slave[$slaves]{"size3"}="ffffffff";
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};
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};
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sub read_defines {
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sub read_defines {
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$priority=0;
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$priority=0;
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$masters=0;
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$masters=0;
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$slaves=0;
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$slaves=0;
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open(FILE,"<$_[0]") or die "could not read from $file";
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open(FILE,"<$_[0]") or die "could not read from $file";
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while($a = <FILE>)
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while($a = <FILE>)
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{
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{
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if ($a =~ /^(syscon|intercon|filename)( *)(=)( *)([a-zA-Z0-9_\/\.]+)(;?)$/) {
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if ($a =~ /^(syscon|intercon|filename)( *)(=)( *)([a-zA-Z0-9_\/\.]+)(;?)$/) {
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if($1 eq "syscon") { $syscon = $5; }
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if($1 eq "syscon") { $syscon = $5; }
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if($1 eq "intercon") { $intercon = $5; }
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if($1 eq "intercon") { $intercon = $5; }
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if($1 eq "filename") { $outfile = $5; }
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if($1 eq "filename") { $outfile = $5; }
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}
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}
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if ($a =~ /^(target)( *)(=)( *)(generic|xilinx|altera)(;?)$/) {
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if ($a =~ /^(target)( *)(=)( *)(generic|xilinx|altera)(;?)$/) {
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$target = $5; };
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$target = $5; };
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if ($a =~ /^(hdl)( *)(=)( *)(vhdl|verilog|perlilog);?$/) {
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if ($a =~ /^(hdl)( *)(=)( *)(vhdl|verilog|perlilog);?$/) {
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$hdl = $5;
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$hdl = $5;
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if ($5 eq "vhdl") {
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if ($5 eq "vhdl") {
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$comment="--";
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$comment="--";
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$ext=".vhd";
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$ext=".vhd";
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} else {
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} else {
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$comment="//";
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$comment="//";
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$ext=".v";
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$ext=".v";
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};
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};
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};
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};
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if ($a =~ /^(interconnect)( *)(=)( *)(crossbarswitch|sharedbus)(;?)$/) {
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if ($a =~ /^(interconnect)( *)(=)( *)(crossbarswitch|sharedbus)(;?)$/) {
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$interconnect = $5; };
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$interconnect = $5; };
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if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($*)/) {
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if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($*)/) {
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$signal_groups = $5; };
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$signal_groups = $5; };
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if ($a =~ /^(mux_type)( *)(=)( *)(mux|andor|tristate)(;?)$/) {
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if ($a =~ /^(mux_type)( *)(=)( *)(mux|andor|tristate)(;?)$/) {
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$mux_type = $5; };
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$mux_type = $5; };
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if ($a =~ /^(optimize)( *)(=)( *)(speed|area);?$/) {
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if ($a =~ /^(optimize)( *)(=)( *)(speed|area);?$/) {
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$optimize = $5; };
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$optimize = $5; };
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if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits)( *)(=)( *)([0-9]+)(;?)($*)/) {
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if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits)( *)(=)( *)([0-9]+)(;?)($*)/) {
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if ($1 eq "dat_size"){$dat_size = $5};
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if ($1 eq "dat_size"){$dat_size = $5};
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if ($1 eq "adr_size"){$adr_size = $5};
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if ($1 eq "adr_size"){$adr_size = $5};
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if ($1 eq "tgd_bits"){$tgd_bits = $5};
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if ($1 eq "tgd_bits"){$tgd_bits = $5};
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if ($1 eq "tga_bits"){$tga_bits = $5};
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if ($1 eq "tga_bits"){$tga_bits = $5};
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if ($1 eq "tgc_bits"){$tgc_bits = $5};
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if ($1 eq "tgc_bits"){$tgc_bits = $5};
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};
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};
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if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($*)/) {
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if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($*)/) {
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if ($3 eq "tga"){$rename_tga=$7};
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if ($3 eq "tga"){$rename_tga=$7};
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if ($3 eq "tgc"){$rename_tgc=$7};
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if ($3 eq "tgc"){$rename_tgc=$7};
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if ($3 eq "tgd"){$rename_tgd=$7};
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if ($3 eq "tgd"){$rename_tgd=$7};
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};
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};
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# master port setup
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# master port setup
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if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($*)/) {
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if ($a =~ /^(master)( *)([A-Za-z0-9_-]+)($*)/) {
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if($1 eq "master") {
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if($1 eq "master") {
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master_init($3);
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master_init($3);
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};
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};
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$a = <FILE>;
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$a = <FILE>;
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until ($a =~ /^(end master)($*)/) {
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until ($a =~ /^(end master)($*)/) {
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if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($*)/) {
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if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($*)/) {
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$master[$masters]{"$2"}=$7;
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$master[$masters]{"$2"}=$7;
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if (($2 eq "rty_i") && ($7 eq 1)) {
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if (($2 eq "rty_i") && ($7 eq 1)) {
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$rty_i++; };
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$rty_i++; };
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if (($2 eq "err_i") && ($7 eq 1)) {
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if (($2 eq "err_i") && ($7 eq 1)) {
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$err_i++; };
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$err_i++; };
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if (($2 eq "tgc_o") && ($7 eq 1)) {
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if (($2 eq "tgc_o") && ($7 eq 1)) {
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$tgc_o++; };
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$tgc_o++; };
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if (($2 eq "tga_o") && ($7 eq 1)) {
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if (($2 eq "tga_o") && ($7 eq 1)) {
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$tga_o++; };
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$tga_o++; };
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# priority for shared bus system
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# priority for shared bus system
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if ($2 eq "priority") {
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if ($2 eq "priority") {
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$priority += $7; };
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$priority += $7; };
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}; #end if
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}; #end if
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if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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$master[$masters]{"$2"}=$6; };
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$master[$masters]{"$2"}=$6; };
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# priority for crossbarswitch
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# priority for crossbarswitch
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if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($*)/) {
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if ($a =~ /^( *)(priority)(_)([0-9a-zA-Z_]*)( *)(=)( *)([0-9]*)(;?)($*)/) {
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$master[$masters]{("priority_"."$4")}=$8; };
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$master[$masters]{("priority_"."$4")}=$8; };
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$a = <FILE>;
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$a = <FILE>;
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};
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};
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};
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};
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# slave port setup
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# slave port setup
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if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($*)/) {
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if ($a =~ /^(slave)( *)([A-Za-z0-9_-]+)($*)/) {
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if ($1 eq "slave") {
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if ($1 eq "slave") {
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slave_init($3);
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slave_init($3);
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};
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};
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$a = <FILE>;
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$a = <FILE>;
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until ($a =~ /^(end slave)($*)/) {
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until ($a =~ /^(end slave)($*)/) {
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if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
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if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
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$slave[$slaves]{"$2"}=$7;
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$slave[$slaves]{"$2"}=$7;
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if (($2 eq "rty_o") && ($7 eq 1)) {
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if (($2 eq "rty_o") && ($7 eq 1)) {
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$rty_o++; };
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$rty_o++; };
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if (($2 eq "err_o") && ($7 eq 1)) {
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if (($2 eq "err_o") && ($7 eq 1)) {
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$err_o++; };
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$err_o++; };
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if (($2 eq "tgc_i") && ($7 eq 1)) {
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if (($2 eq "tgc_i") && ($7 eq 1)) {
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$tgc_i++; };
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$tgc_i++; };
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if (($2 eq "tga_i") && ($7 eq 1)) {
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if (($2 eq "tga_i") && ($7 eq 1)) {
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$tga_i++; };
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$tga_i++; };
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}; #end if
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}; #end if
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if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
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$slave[$slaves]{"$2"}=$6; };
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$slave[$slaves]{"$2"}=$6; };
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$a = <FILE>;
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$a = <FILE>;
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};
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};
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};
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};
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}; #end while
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}; #end while
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close($_[0]);
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close($_[0]);
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}; #end sub
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}; #end sub
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################################################################################
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################################################################################
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# GUI
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# GUI
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my $mw;
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my $mw;
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sub WinGlobalExit {
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sub WinGlobalExit {
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$mw->destroy();
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$mw->destroy();
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};
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};
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# global assignments
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# global assignments
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sub WinGlobal {
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sub WinGlobal {
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$mw = MainWindow->new;
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$mw = MainWindow->new;
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$mw->title ("Wishbone generator");
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$mw->title ("Wishbone generator");
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$frame=$mw->Frame(-label=>"Global definitions");
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$frame=$mw->Frame(-label=>"Global definitions");
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# define file
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# define file
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Define file:")->pack(-side=>'left');
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$frame->Label(-text => "Define file:")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$infile)->pack(-side=>'right');
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$frame->Entry(-textvariable => \$infile)->pack(-side=>'right');
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# HDL file
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# HDL file
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$frame=$mw->Frame();
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "HDL file :")->pack(-side=>'left');
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$frame->Label(-text => "HDL file :")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$outfile)->pack(-side=>'right');
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$frame->Entry(-textvariable => \$outfile)->pack(-side=>'right');
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# intercon
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# intercon
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$frame=$mw->Frame();
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "intercon :")->pack(-side=>'left');
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$frame->Label(-text => "intercon :")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$intercon)->pack(-side=>'right');
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$frame->Entry(-textvariable => \$intercon)->pack(-side=>'right');
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# syscon
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# syscon
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$frame=$mw->Frame();
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "syscon :")->pack(-side=>'left');
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$frame->Label(-text => "syscon :")->pack(-side=>'left');
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$frame->Entry(-textvariable => \$syscon)->pack(-side=>'right');
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$frame->Entry(-textvariable => \$syscon)->pack(-side=>'right');
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# target
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# target
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$frame=$mw->Frame();
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$frame=$mw->Frame();
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
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$frame->Label(-text => "Target :")->pack(-side=>'left');
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$frame->Label(-text => "Target :")->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$target, -text => 'Generic', -value => 'generic')->pack(-side=>'left');
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$a = $frame->Radiobutton ( -variable => \$target, -text => 'Generic', -value => 'generic')->pack(-side=>'left');
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$b = $frame->Radiobutton ( -variable => \$target, -text => 'XILINX', -value => 'xilinx')->pack(-side=>'left');
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$b = $frame->Radiobutton ( -variable => \$target, -text => 'XILINX', -value => 'xilinx')->pack(-side=>'left');
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$c = $frame->Radiobutton ( -variable => \$target, -text => 'ALTERA', -value => 'altera')->pack(-side=>'left');
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$c = $frame->Radiobutton ( -variable => \$target, -text => 'ALTERA', -value => 'altera')->pack(-side=>'left');
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# interconnect
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# interconnect
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$frame=$mw->Frame();
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$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Interconnection :")->pack(-side=>'left');
|
$frame->Label(-text => "Interconnection :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$interconnect, -text => 'Shared bus', -value => 'sharedbus')->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$interconnect, -text => 'Shared bus', -value => 'sharedbus')->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$interconnect, -text => 'Crossbar switch', -value => 'crossbarswitch' )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$interconnect, -text => 'Crossbar switch', -value => 'crossbarswitch' )->pack( -side=>'right');
|
# mux
|
# mux
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Mux type :")->pack(-side=>'left');
|
$frame->Label(-text => "Mux type :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$mux_type, -text => 'mux', -value => 'mux')->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$mux_type, -text => 'mux', -value => 'mux')->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$mux_type, -text => 'andor', -value => 'andor')->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$mux_type, -text => 'andor', -value => 'andor')->pack( -side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$mux_type, -text => 'tristate', -value => 'tristate' )->pack( -side=>'right');
|
$c = $frame->Radiobutton ( -variable => \$mux_type, -text => 'tristate', -value => 'tristate' )->pack( -side=>'right');
|
# hdl
|
# hdl
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "HDL type :")->pack(-side=>'left');
|
$frame->Label(-text => "HDL type :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$hdl, -text => 'VHDL', -value => 'vhdl')->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$hdl, -text => 'VHDL', -value => 'vhdl')->pack(-side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$hdl, -text => 'Verilog', -value => 'verilog')->pack(-side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$hdl, -text => 'Verilog', -value => 'verilog')->pack(-side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$hdl, -text => 'Perlilog', -value => 'perlilog')->pack(-side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$hdl, -text => 'Perlilog', -value => 'perlilog')->pack(-side=>'left');
|
# signalgroups
|
# signalgroups
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Signal groups :")->pack(-side=>'left');
|
$frame->Label(-text => "Signal groups :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# dat size
|
# dat size
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$dat_size)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$dat_size)->pack(-side=>'right');
|
# adr size
|
# adr size
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Adr bus size :")->pack(-side=>'left');
|
$frame->Label(-text => "Adr bus size :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$adr_size)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$adr_size)->pack(-side=>'right');
|
# tga
|
# tga
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tga bits :")->pack(-side=>'left');
|
$frame->Label(-text => "tga bits :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$tga_bits)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$tga_bits)->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tga rename :")->pack(-side=>'left');
|
$frame->Label(-text => "tga rename :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$rename_tga)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$rename_tga)->pack(-side=>'right');
|
# tgc
|
# tgc
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgc bits :")->pack(-side=>'left');
|
$frame->Label(-text => "tgc bits :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$tgc_bits)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$tgc_bits)->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgc rename :")->pack(-side=>'left');
|
$frame->Label(-text => "tgc rename :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$rename_tgc)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$rename_tgc)->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "classic :")->pack(-side=>'left');
|
$frame->Label(-text => "classic :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$classic)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$classic)->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "end of burst :")->pack(-side=>'left');
|
$frame->Label(-text => "end of burst :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$endofburst)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$endofburst)->pack(-side=>'right');
|
# tgd
|
# tgd
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgd bits :")->pack(-side=>'left');
|
$frame->Label(-text => "tgd bits :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$tgd_bits)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$tgd_bits)->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgd rename :")->pack(-side=>'left');
|
$frame->Label(-text => "tgd rename :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$rename_tgd)->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$rename_tgd)->pack(-side=>'right');
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->Button(-text => "add master port", -command =>sub {WinGlobalExit(); $amp=1;})->pack (-side => 'left');
|
$frame->Button(-text => "add master port", -command =>sub {WinGlobalExit(); $amp=1;})->pack (-side => 'left');
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $asp=1;})->pack (-side => 'left');
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $asp=1;})->pack (-side => 'left');
|
if (($masters > 0) && ($slaves > 0)) {
|
if (($masters > 0) && ($slaves > 0)) {
|
$frame->Button(-text => "set priority", -command =>sub {WinGlobalExit();})->pack (-side => 'left');
|
$frame->Button(-text => "set priority", -command =>sub {WinGlobalExit();})->pack (-side => 'left');
|
};
|
};
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack (-side => 'right');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack (-side => 'right');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
# add master port
|
# add master port
|
sub WinAddMaster {
|
sub WinAddMaster {
|
master_init("wbm". ($masters+1));
|
master_init("wbm". ($masters+1));
|
$mw = MainWindow->new;
|
$mw = MainWindow->new;
|
$mw->title ("Wishbone generator");
|
$mw->title ("Wishbone generator");
|
$frame=$mw->Frame(-label=>"Add wishbone master port");
|
$frame=$mw->Frame(-label=>"Add wishbone master port");
|
# port name
|
# port name
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Master port name:")->pack(-side=>'left');
|
$frame->Label(-text => "Master port name:")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$masters]{"wbm"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$master[$masters]{"wbm"})->pack(-side=>'right');
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->Button(-text => "add master port", -command =>sub {WinGlobalExit(); $amp=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "add master port", -command =>sub {WinGlobalExit(); $amp=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
sub WinMaster {
|
sub WinMaster {
|
$mw = MainWindow->new;
|
$mw = MainWindow->new;
|
$mw->title ("Wishbone generator");
|
$mw->title ("Wishbone generator");
|
$frame=$mw->Frame(-label=>"Master port");
|
$frame=$mw->Frame(-label=>"Master port");
|
# Master port
|
# Master port
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Master port :")->pack(-side=>'left');
|
$frame->Label(-text => "Master port :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'right');
|
# dat_size
|
# dat_size
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"dat_size"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$master[$i]{"dat_size"})->pack(-side=>'right');
|
# adr size
|
# adr size
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Adr bus size :")->pack(-side=>'left');
|
$frame->Label(-text => "Adr bus size :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"adr_size"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$master[$i]{"adr_size"})->pack(-side=>'right');
|
# type
|
# type
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Master type :")->pack(-side=>'left');
|
$frame->Label(-text => "Master type :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Read/Write', -value => 'rw')->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Read/Write', -value => 'rw')->pack(-side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Read only', -value => 'ro')->pack(-side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Read only', -value => 'ro')->pack(-side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Write only', -value => 'wo')->pack(-side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$master[$i]{"type"}, -text => 'Write only', -value => 'wo')->pack(-side=>'left');
|
# err_i
|
# err_i
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "err_i :")->pack(-side=>'left');
|
$frame->Label(-text => "err_i :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"err_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"err_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"err_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"err_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# rty_i
|
# rty_i
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "rty_i :")->pack(-side=>'left');
|
$frame->Label(-text => "rty_i :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"rty_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"rty_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"rty_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"rty_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# lock_o
|
# lock_o
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "lock_o :")->pack(-side=>'left');
|
$frame->Label(-text => "lock_o :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"lock_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"lock_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"lock_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"lock_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# tga_o
|
# tga_o
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tga_o :")->pack(-side=>'left');
|
$frame->Label(-text => "tga_o :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tga_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tga_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tga_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tga_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# tgc_o
|
# tgc_o
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgc_o :")->pack(-side=>'left');
|
$frame->Label(-text => "tgc_o :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tgc_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tgc_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tgc_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tgc_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# tgd_o
|
# tgd_o
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgd_o :")->pack(-side=>'left');
|
$frame->Label(-text => "tgd_o :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tgd_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$master[$i]{"tgd_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tgd_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$master[$i]{"tgd_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
if ($i == $masters) {
|
if ($i == $masters) {
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $am=1;})->pack (-side => 'left');
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $am=1;})->pack (-side => 'left');
|
};
|
};
|
$frame->Button(-text => "delete", -command =>sub {WinGlobalExit(); $del=1;})->pack (-side => 'left');
|
$frame->Button(-text => "delete", -command =>sub {WinGlobalExit(); $del=1;})->pack (-side => 'left');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack (-side => 'left');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack (-side => 'left');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack (-side => 'left');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack (-side => 'left');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
# add slave port
|
# add slave port
|
sub WinAddSlave {
|
sub WinAddSlave {
|
slave_init("wbs" . ($slaves+1));
|
slave_init("wbs" . ($slaves+1));
|
$mw = MainWindow->new;
|
$mw = MainWindow->new;
|
$mw->title ("Wishbone generator");
|
$mw->title ("Wishbone generator");
|
$frame=$mw->Frame(-label=>"Add wishbone slave port");
|
$frame=$mw->Frame(-label=>"Add wishbone slave port");
|
# port name
|
# port name
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Slave port name:")->pack(-side=>'left');
|
$frame->Label(-text => "Slave port name:")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$slaves]{"wbs"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$slaves]{"wbs"})->pack(-side=>'right');
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $asp=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "add slave port", -command =>sub {WinGlobalExit(); $asp=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
# slave port
|
# slave port
|
sub WinSlave {
|
sub WinSlave {
|
$mw = MainWindow->new;
|
$mw = MainWindow->new;
|
$mw->title ("Wishbone generator");
|
$mw->title ("Wishbone generator");
|
$frame=$mw->Frame(-label=>"Slave port");
|
$frame=$mw->Frame(-label=>"Slave port");
|
# Slave port
|
# Slave port
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Slave port :")->pack(-side=>'left');
|
$frame->Label(-text => "Slave port :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"wbs"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"wbs"})->pack(-side=>'right');
|
# dat_size
|
# dat_size
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"dat_size"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"dat_size"})->pack(-side=>'right');
|
# adr
|
# adr
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "adr hi :")->pack(-side=>'left');
|
$frame->Label(-text => "adr hi :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"adr_i_hi"})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"adr_i_hi"})->pack(-side=>'left');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "adr lo :")->pack(-side=>'left');
|
$frame->Label(-text => "adr lo :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"adr_i_lo"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"adr_i_lo"})->pack(-side=>'right');
|
# type
|
# type
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Slave type :")->pack(-side=>'left');
|
$frame->Label(-text => "Slave type :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Read/Write', -value => 'rw')->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Read/Write', -value => 'rw')->pack(-side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Read only', -value => 'ro')->pack(-side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Read only', -value => 'ro')->pack(-side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Write only', -value => 'wo')->pack(-side=>'left');
|
$c = $frame->Radiobutton ( -variable => \$slave[$i]{"type"}, -text => 'Write only', -value => 'wo')->pack(-side=>'left');
|
# lock_i
|
# lock_i
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "lock_i :")->pack(-side=>'left');
|
$frame->Label(-text => "lock_i :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# tga_i
|
# tga_i
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tga_i :")->pack(-side=>'left');
|
$frame->Label(-text => "tga_i :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tga_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tga_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tga_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tga_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# tgc_i
|
# tgc_i
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgc_i :")->pack(-side=>'left');
|
$frame->Label(-text => "tgc_i :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tgc_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tgc_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tgc_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tgc_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# tgd_i
|
# tgd_i
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "tgd_i :")->pack(-side=>'left');
|
$frame->Label(-text => "tgd_i :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tgd_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"tgd_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tgd_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"tgd_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# err_o
|
# err_o
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "err_o :")->pack(-side=>'left');
|
$frame->Label(-text => "err_o :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"err_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"err_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"err_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"err_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# rty_o
|
# rty_o
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "rty_o :")->pack(-side=>'left');
|
$frame->Label(-text => "rty_o :")->pack(-side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"rty_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"rty_o"}, -text => 'No', -value => 0)->pack( -side=>'left');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"rty_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"rty_o"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
|
# ss
|
# ss
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Base_adr :")->pack(-side=>'left');
|
$frame->Label(-text => "Base_adr :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr"})->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Size :")->pack(-side=>'left');
|
$frame->Label(-text => "Size :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"size"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"size"})->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Base_adr1 :")->pack(-side=>'left');
|
$frame->Label(-text => "Base_adr1 :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr1"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr1"})->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Size1 :")->pack(-side=>'left');
|
$frame->Label(-text => "Size1 :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"size1"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"size1"})->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Base_adr2 :")->pack(-side=>'left');
|
$frame->Label(-text => "Base_adr2 :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr2"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"baseadr2"})->pack(-side=>'right');
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => "Size2 :")->pack(-side=>'left');
|
$frame->Label(-text => "Size2 :")->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$i]{"size2"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$slave[$i]{"size2"})->pack(-side=>'right');
|
|
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "delete", -command =>sub {WinGlobalExit(); $del=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "delete", -command =>sub {WinGlobalExit(); $del=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
$frame->Button(-text => "next", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
# Prio shared bus
|
# Prio shared bus
|
sub WinPrioshb {
|
sub WinPrioshb {
|
$mw = MainWindow->new;
|
$mw = MainWindow->new;
|
$mw->title ("Wishbone generator");
|
$mw->title ("Wishbone generator");
|
$frame=$mw->Frame(-label=>"Priority for shared bus system")->pack();
|
$frame=$mw->Frame(-label=>"Priority for shared bus system")->pack();
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
|
$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
|
$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"priority"})->pack(-side=>'right');
|
$frame->Entry(-textvariable => \$master[$i]{"priority"})->pack(-side=>'right');
|
};
|
};
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "generate", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
$frame->Button(-text => "generate", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
# Prio cross bar switch
|
# Prio cross bar switch
|
sub WinPriocbs {
|
sub WinPriocbs {
|
my $tmp="";
|
my $tmp="";
|
$mw = MainWindow->new;
|
$mw = MainWindow->new;
|
$mw->title ("Wishbone generator");
|
$mw->title ("Wishbone generator");
|
$frame=$mw->Frame(-label=>"Priority for crossbar switch bus system")->pack();
|
$frame=$mw->Frame(-label=>"Priority for crossbar switch bus system")->pack();
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
|
$frame->Entry(-textvariable => \$tmp)->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$tmp)->pack(-side=>'left');
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
$frame->Entry(-textvariable => \$slave[$j]{"wbs"})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$slave[$j]{"wbs"})->pack(-side=>'left');
|
};
|
};
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
$frame=$mw->Frame();
|
$frame=$mw->Frame();
|
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
|
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
|
#$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
|
#$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'left');
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
#$frame->Label(-text => $master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
|
#$frame->Label(-text => $master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
|
$frame->Entry(-textvariable => \$master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
|
};
|
};
|
};
|
};
|
# exit
|
# exit
|
$frame=$mw->Frame(-label=>"\n");
|
$frame=$mw->Frame(-label=>"\n");
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->pack(-side => 'right', -fill => 'y', -expand => 'y');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "back", -command =>sub {WinGlobalExit(); $back=1;})->pack ( -side => 'left');
|
$frame->Button(-text => "generate", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
$frame->Button(-text => "generate", -command =>sub {WinGlobalExit(); $next=1;})->pack ( -side => 'right');
|
MainLoop;
|
MainLoop;
|
};
|
};
|
|
|
# delete wishbone master
|
# delete wishbone master
|
sub wbm_del {
|
sub wbm_del {
|
my $i;
|
my $i;
|
if ($_[0] != $masters) {
|
if ($_[0] != $masters) {
|
for ($i=$_[0]; $i lt $masters; $i++) {
|
for ($i=$_[0]; $i lt $masters; $i++) {
|
$master[$i]=$master[$i+1];
|
$master[$i]=$master[$i+1];
|
};
|
};
|
};
|
};
|
$masters--;
|
$masters--;
|
};
|
};
|
|
|
# delete wishbone slave
|
# delete wishbone slave
|
sub wbs_del {
|
sub wbs_del {
|
my $i;
|
my $i;
|
if ($_[0] != $slaves) {
|
if ($_[0] != $slaves) {
|
for ($i=$_[0]; $i lt $slaves; $i++) {
|
for ($i=$_[0]; $i lt $slaves; $i++) {
|
$slave[$i]=$slave[$i+1];
|
$slave[$i]=$slave[$i+1];
|
};
|
};
|
};
|
};
|
$slaves--;
|
$slaves--;
|
};
|
};
|
|
|
# GUI FSM
|
# GUI FSM
|
sub gui_fsm {
|
sub gui_fsm {
|
$i=1;
|
$i=1;
|
until ($state eq "bye") {
|
until ($state eq "bye") {
|
$amp=0; $asp=0; $back=0; $next=0; $del=0;
|
$amp=0; $asp=0; $back=0; $next=0; $del=0;
|
if ($state eq 'WinGlobal') {
|
if ($state eq 'WinGlobal') {
|
WinGlobal;
|
WinGlobal;
|
if ($amp == 1) {
|
if ($amp == 1) {
|
$state='WinAddMaster';
|
$state='WinAddMaster';
|
} elsif ($asp == 1) {
|
} elsif ($asp == 1) {
|
$state='WinAddSlave';
|
$state='WinAddSlave';
|
} elsif ($next == 1) {
|
} elsif ($next == 1) {
|
$i=1;
|
$i=1;
|
if ($masters == 0) {
|
if ($masters == 0) {
|
$state='WinAddMaster';
|
$state='WinAddMaster';
|
} else {
|
} else {
|
$state='WinMaster';
|
$state='WinMaster';
|
};
|
};
|
} else {
|
} else {
|
$state='WinPrio';
|
$state='WinPrio';
|
};
|
};
|
} elsif ($state eq 'WinAddMaster') {
|
} elsif ($state eq 'WinAddMaster') {
|
WinAddMaster;
|
WinAddMaster;
|
if ($next == 1) {
|
if ($next == 1) {
|
$i=1;
|
$i=1;
|
$state='WinMaster';
|
$state='WinMaster';
|
};
|
};
|
} elsif ($state eq 'WinMaster') {
|
} elsif ($state eq 'WinMaster') {
|
WinMaster;
|
WinMaster;
|
if ($del == 1) {
|
if ($del == 1) {
|
wbm_del($i);
|
wbm_del($i);
|
$state='WinGlobal';
|
$state='WinGlobal';
|
$i=1;
|
$i=1;
|
} elsif ($asp == 1) {
|
} elsif ($asp == 1) {
|
$state='WinAddSlave';
|
$state='WinAddSlave';
|
} elsif ($next == 1) {
|
} elsif ($next == 1) {
|
if ($i == $masters) {
|
if ($i == $masters) {
|
$i=1;
|
$i=1;
|
if ($slaves == 0) {
|
if ($slaves == 0) {
|
$state='WinAddSlave';
|
$state='WinAddSlave';
|
} else {
|
} else {
|
$state='WinSlave';
|
$state='WinSlave';
|
};
|
};
|
} else {
|
} else {
|
$i++
|
$i++
|
};
|
};
|
} else {
|
} else {
|
if ($i == 1) {
|
if ($i == 1) {
|
$state='WinGlobal';
|
$state='WinGlobal';
|
} else {
|
} else {
|
$i--;
|
$i--;
|
}
|
}
|
};
|
};
|
} elsif ($state eq 'WinAddSlave') {
|
} elsif ($state eq 'WinAddSlave') {
|
WinAddSlave;
|
WinAddSlave;
|
if ($next == 1) {
|
if ($next == 1) {
|
$i=1;
|
$i=1;
|
$state='WinSlave';
|
$state='WinSlave';
|
};
|
};
|
} elsif ($state eq 'WinSlave') {
|
} elsif ($state eq 'WinSlave') {
|
WinSlave;
|
WinSlave;
|
if ($del == 1) {
|
if ($del == 1) {
|
wbs_del($i);
|
wbs_del($i);
|
$i=1;
|
$i=1;
|
$state='WinGlobal';
|
$state='WinGlobal';
|
} elsif ($next == 1) {
|
} elsif ($next == 1) {
|
if ($i eq $slaves) {
|
if ($i eq $slaves) {
|
$state='WinPrio';
|
$state='WinPrio';
|
} else {
|
} else {
|
$i++
|
$i++
|
};
|
};
|
} else {
|
} else {
|
if ($i == 1) {
|
if ($i == 1) {
|
$state='WinGlobal';
|
$state='WinGlobal';
|
} else {
|
} else {
|
$i--;
|
$i--;
|
}
|
}
|
};
|
};
|
} elsif ($state eq 'WinPrio') {
|
} elsif ($state eq 'WinPrio') {
|
if ($interconnect eq "sharedbus") {
|
if ($interconnect eq "sharedbus") {
|
WinPrioshb;
|
WinPrioshb;
|
} else {
|
} else {
|
WinPriocbs;
|
WinPriocbs;
|
};
|
};
|
if ($next == 1) {
|
if ($next == 1) {
|
$state='bye';
|
$state='bye';
|
} else {
|
} else {
|
$state='WinGlobal';
|
$state='WinGlobal';
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
|
|
sub generate_defines {
|
sub generate_defines {
|
open(OUTFILE,"> $_[0]") or die "could not open $infile for writing";
|
open(OUTFILE,"> $_[0]") or die "could not open $infile for writing";
|
printf OUTFILE "# Generated by PERL program wishbone.pl.\n";
|
printf OUTFILE "# Generated by PERL program wishbone.pl.\n";
|
printf OUTFILE "# File used as input for wishbone arbiter generation\n";
|
printf OUTFILE "# File used as input for wishbone arbiter generation\n";
|
$tmp=localtime(time);
|
$tmp=localtime(time);
|
printf OUTFILE "# Generated %s\n\n",$tmp;
|
printf OUTFILE "# Generated %s\n\n",$tmp;
|
printf OUTFILE "filename=%s\n",$outfile;
|
printf OUTFILE "filename=%s\n",$outfile;
|
printf OUTFILE "intercon=%s\n",$intercon;
|
printf OUTFILE "intercon=%s\n",$intercon;
|
printf OUTFILE "syscon=%s\n",$syscon;
|
printf OUTFILE "syscon=%s\n",$syscon;
|
printf OUTFILE "target=%s\n",$target;
|
printf OUTFILE "target=%s\n",$target;
|
printf OUTFILE "hdl=%s\n",$hdl;
|
printf OUTFILE "hdl=%s\n",$hdl;
|
printf OUTFILE "signal_groups=%s\n",$signal_groups;
|
printf OUTFILE "signal_groups=%s\n",$signal_groups;
|
printf OUTFILE "tga_bits=%s\n",$tga_bits;
|
printf OUTFILE "tga_bits=%s\n",$tga_bits;
|
printf OUTFILE "tgc_bits=%s\n",$tgc_bits;
|
printf OUTFILE "tgc_bits=%s\n",$tgc_bits;
|
printf OUTFILE "tgd_bits=%s\n",$tgd_bits;
|
printf OUTFILE "tgd_bits=%s\n",$tgd_bits;
|
printf OUTFILE "rename_tga=%s\n",$rename_tga;
|
printf OUTFILE "rename_tga=%s\n",$rename_tga;
|
printf OUTFILE "rename_tgc=%s\n",$rename_tgc;
|
printf OUTFILE "rename_tgc=%s\n",$rename_tgc;
|
printf OUTFILE "rename_tgd=%s\n",$rename_tgd;
|
printf OUTFILE "rename_tgd=%s\n",$rename_tgd;
|
printf OUTFILE "classic=%s\n",$classic;
|
printf OUTFILE "classic=%s\n",$classic;
|
printf OUTFILE "endofburst=%s\n",$endofburst;
|
printf OUTFILE "endofburst=%s\n",$endofburst;
|
printf OUTFILE "dat_size=%s\n",$dat_size;
|
printf OUTFILE "dat_size=%s\n",$dat_size;
|
printf OUTFILE "adr_size=%s\n",$adr_size;
|
printf OUTFILE "adr_size=%s\n",$adr_size;
|
printf OUTFILE "mux_type=%s\n",$mux_type;
|
printf OUTFILE "mux_type=%s\n",$mux_type;
|
printf OUTFILE "interconnect=%s\n",$interconnect;
|
printf OUTFILE "interconnect=%s\n",$interconnect;
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE "\nmaster %s\n",$master[$i]{"wbm"};
|
printf OUTFILE "\nmaster %s\n",$master[$i]{"wbm"};
|
printf OUTFILE " type=%s\n",$master[$i]{"type"};
|
printf OUTFILE " type=%s\n",$master[$i]{"type"};
|
printf OUTFILE " lock_o=%s\n",$master[$i]{"lock_o"};
|
printf OUTFILE " lock_o=%s\n",$master[$i]{"lock_o"};
|
printf OUTFILE " tga_o=%s\n",$master[$i]{"tga_o"};
|
printf OUTFILE " tga_o=%s\n",$master[$i]{"tga_o"};
|
printf OUTFILE " tgc_o=%s\n",$master[$i]{"tgc_o"};
|
printf OUTFILE " tgc_o=%s\n",$master[$i]{"tgc_o"};
|
printf OUTFILE " tgd_o=%s\n",$master[$i]{"tgd_o"};
|
printf OUTFILE " tgd_o=%s\n",$master[$i]{"tgd_o"};
|
printf OUTFILE " err_i=%s\n",$master[$i]{"err_i"};
|
printf OUTFILE " err_i=%s\n",$master[$i]{"err_i"};
|
printf OUTFILE " rty_i=%s\n",$master[$i]{"rty_i"};
|
printf OUTFILE " rty_i=%s\n",$master[$i]{"rty_i"};
|
if ($interconnect eq "sharedbus") {
|
if ($interconnect eq "sharedbus") {
|
printf OUTFILE " priority=%s\n",$master[$i]{"priority"};
|
printf OUTFILE " priority=%s\n",$master[$i]{"priority"};
|
} else {
|
} else {
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
printf OUTFILE " priority_%s=%s\n",$slave[$j]{"wbs"},$master[$i]{"priority_".($slave[$j]{"wbs"})};
|
printf OUTFILE " priority_%s=%s\n",$slave[$j]{"wbs"},$master[$i]{"priority_".($slave[$j]{"wbs"})};
|
};
|
};
|
};
|
};
|
printf OUTFILE "end master %s\n",$master[$i]{"wbm"};
|
printf OUTFILE "end master %s\n",$master[$i]{"wbm"};
|
};
|
};
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "\nslave %s\n",$slave[$i]{"wbs"};
|
printf OUTFILE "\nslave %s\n",$slave[$i]{"wbs"};
|
printf OUTFILE " type=%s\n",$slave[$i]{"type"};
|
printf OUTFILE " type=%s\n",$slave[$i]{"type"};
|
printf OUTFILE " adr_i_hi=%s\n",$slave[$i]{"adr_i_hi"};
|
printf OUTFILE " adr_i_hi=%s\n",$slave[$i]{"adr_i_hi"};
|
printf OUTFILE " adr_i_lo=%s\n",$slave[$i]{"adr_i_lo"};
|
printf OUTFILE " adr_i_lo=%s\n",$slave[$i]{"adr_i_lo"};
|
printf OUTFILE " tga_i=%s\n",$slave[$i]{"tga_i"};
|
printf OUTFILE " tga_i=%s\n",$slave[$i]{"tga_i"};
|
printf OUTFILE " tgc_i=%s\n",$slave[$i]{"tgc_i"};
|
printf OUTFILE " tgc_i=%s\n",$slave[$i]{"tgc_i"};
|
printf OUTFILE " tgd_i=%s\n",$slave[$i]{"tgd_i"};
|
printf OUTFILE " tgd_i=%s\n",$slave[$i]{"tgd_i"};
|
printf OUTFILE " lock_i=%s\n",$slave[$i]{"lock_i"};
|
printf OUTFILE " lock_i=%s\n",$slave[$i]{"lock_i"};
|
printf OUTFILE " err_o=%s\n",$slave[$i]{"err_o"};
|
printf OUTFILE " err_o=%s\n",$slave[$i]{"err_o"};
|
printf OUTFILE " rty_o=%s\n",$slave[$i]{"rty_o"};
|
printf OUTFILE " rty_o=%s\n",$slave[$i]{"rty_o"};
|
printf OUTFILE " baseadr=0x%s\n",$slave[$i]{"baseadr"};
|
printf OUTFILE " baseadr=0x%s\n",$slave[$i]{"baseadr"};
|
printf OUTFILE " size=0x%s\n",$slave[$i]{"size"};
|
printf OUTFILE " size=0x%s\n",$slave[$i]{"size"};
|
printf OUTFILE " baseadr1=0x%s\n",$slave[$i]{"baseadr1"};
|
printf OUTFILE " baseadr1=0x%s\n",$slave[$i]{"baseadr1"};
|
printf OUTFILE " size1=0x%s\n",$slave[$i]{"size1"};
|
printf OUTFILE " size1=0x%s\n",$slave[$i]{"size1"};
|
printf OUTFILE " baseadr2=0x%s\n",$slave[$i]{"baseadr2"};
|
printf OUTFILE " baseadr2=0x%s\n",$slave[$i]{"baseadr2"};
|
printf OUTFILE " size2=0x%s\n",$slave[$i]{"size2"};
|
printf OUTFILE " size2=0x%s\n",$slave[$i]{"size2"};
|
printf OUTFILE "end slave %s\n",$slave[$i]{"wbs"};
|
printf OUTFILE "end slave %s\n",$slave[$i]{"wbs"};
|
};
|
};
|
close(OUTFILE);
|
close(OUTFILE);
|
};
|
};
|
|
|
# print header
|
# print header
|
sub gen_header {
|
sub gen_header {
|
printf OUTFILE "%s Generated by PERL program wishbone.pl. Do not edit this file.\n%s\n",$comment,$comment;
|
printf OUTFILE "%s Generated by PERL program wishbone.pl. Do not edit this file.\n%s\n",$comment,$comment;
|
printf OUTFILE "%s For defines see %s\n%s\n",$comment,$infile,$comment;
|
printf OUTFILE "%s For defines see %s\n%s\n",$comment,$infile,$comment;
|
$tmp=localtime(time);
|
$tmp=localtime(time);
|
printf OUTFILE "%s Generated %s\n%s\n",$comment,$tmp,$comment;
|
printf OUTFILE "%s Generated %s\n%s\n",$comment,$tmp,$comment;
|
printf OUTFILE "%s Wishbone masters:\n",$comment;
|
printf OUTFILE "%s Wishbone masters:\n",$comment;
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE "%s %s\n",$comment,$master[$i]{"wbm"}; };
|
printf OUTFILE "%s %s\n",$comment,$master[$i]{"wbm"}; };
|
printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
|
printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "%s %s\n",$comment,$slave[$i]{"wbs"};
|
printf OUTFILE "%s %s\n",$comment,$slave[$i]{"wbs"};
|
if ($slave[$i]{"size"} ne ffffffff) {
|
if ($slave[$i]{"size"} ne ffffffff) {
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
|
if ($slave[$i]{"size1"} ne ffffffff) {
|
if ($slave[$i]{"size1"} ne ffffffff) {
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr1"},$slave[$i]{"size1"}};
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr1"},$slave[$i]{"size1"}};
|
if ($slave[$i]{"size2"} ne ffffffff) {
|
if ($slave[$i]{"size2"} ne ffffffff) {
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr2"},$slave[$i]{"size2"}};
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr2"},$slave[$i]{"size2"}};
|
if ($slave[$i]{"size3"} ne ffffffff) {
|
if ($slave[$i]{"size3"} ne ffffffff) {
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
|
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
|
};
|
};
|
};
|
};
|
|
|
sub gen_vhdl_package {
|
sub gen_vhdl_package {
|
printf OUTFILE "-----------------------------------------------------------------------------------------\n";
|
printf OUTFILE "-----------------------------------------------------------------------------------------\n";
|
printf OUTFILE "library IEEE;\nuse IEEE.std_logic_1164.all;\n\n";
|
printf OUTFILE "library IEEE;\nuse IEEE.std_logic_1164.all;\n\n";
|
printf OUTFILE "package %s_package is\n\n",$intercon;
|
printf OUTFILE "package %s_package is\n\n",$intercon;
|
|
|
# records ?
|
# records ?
|
if ($signal_groups eq 1) {
|
if ($signal_groups eq 1) {
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
# input record
|
# input record
|
printf OUTFILE "type %s_wbm_i_type is record\n",$master[$i]{"wbm"};
|
printf OUTFILE "type %s_wbm_i_type is record\n",$master[$i]{"wbm"};
|
if ($master[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;};
|
if ($master[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;};
|
if ($master[$i]{"err_i"} eq 1) { printf OUTFILE " err_i : std_logic;\n";};
|
if ($master[$i]{"err_i"} eq 1) { printf OUTFILE " err_i : std_logic;\n";};
|
if ($master[$i]{"rty_i"} eq 1) { printf OUTFILE " rty_i : std_logic;\n";};
|
if ($master[$i]{"rty_i"} eq 1) { printf OUTFILE " rty_i : std_logic;\n";};
|
printf OUTFILE " ack_i : std_logic;\n";
|
printf OUTFILE " ack_i : std_logic;\n";
|
printf OUTFILE "end record;\n";
|
printf OUTFILE "end record;\n";
|
# output record
|
# output record
|
printf OUTFILE "type %s_wbm_o_type is record\n",$master[$i]{"wbm"};
|
printf OUTFILE "type %s_wbm_o_type is record\n",$master[$i]{"wbm"};
|
if ($master[$i]{"type"} =~ /(wo|rw)/) {
|
if ($master[$i]{"type"} =~ /(wo|rw)/) {
|
printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;
|
printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;
|
printf OUTFILE " we_o : std_logic;\n"; };
|
printf OUTFILE " we_o : std_logic;\n"; };
|
if ($dat_size eq 8) {
|
if ($dat_size eq 8) {
|
printf OUTFILE " sel_o : std_logic;\n";
|
printf OUTFILE " sel_o : std_logic;\n";
|
} else {
|
} else {
|
printf OUTFILE " sel_o : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
|
printf OUTFILE " sel_o : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
|
printf OUTFILE " adr_o : std_logic_vector(%s downto 0);\n",$adr_size-1;
|
printf OUTFILE " adr_o : std_logic_vector(%s downto 0);\n",$adr_size-1;
|
if ($master[$i]{"lock_o"} eq 1) { printf OUTFILE " lock_o : std_logic;\n";};
|
if ($master[$i]{"lock_o"} eq 1) { printf OUTFILE " lock_o : std_logic;\n";};
|
if ($master[$i]{"tga_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
|
if ($master[$i]{"tga_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
|
if ($master[$i]{"tgc_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
|
if ($master[$i]{"tgc_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
|
printf OUTFILE " cyc_o : std_logic;\n";
|
printf OUTFILE " cyc_o : std_logic;\n";
|
printf OUTFILE " stb_o : std_logic;\n";
|
printf OUTFILE " stb_o : std_logic;\n";
|
printf OUTFILE "end record;\n\n";
|
printf OUTFILE "end record;\n\n";
|
}; #end for
|
}; #end for
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
# input record
|
# input record
|
printf OUTFILE "type %s_wbs_i_type is record\n",$slave[$i]{"wbs"};
|
printf OUTFILE "type %s_wbs_i_type is record\n",$slave[$i]{"wbs"};
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1;
|
printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1;
|
printf OUTFILE " we_i : std_logic;\n"; };
|
printf OUTFILE " we_i : std_logic;\n"; };
|
if ($dat_size eq 8) {
|
if ($dat_size eq 8) {
|
printf OUTFILE " sel_i : std_logic;\n";
|
printf OUTFILE " sel_i : std_logic;\n";
|
} else {
|
} else {
|
printf OUTFILE " sel_i : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
|
printf OUTFILE " sel_i : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
|
if ($slave[$i]{"adr_i_hi"} gt 0) { printf OUTFILE " adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
|
if ($slave[$i]{"adr_i_hi"} gt 0) { printf OUTFILE " adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
|
if ($slave[$i]{"tga_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
|
if ($slave[$i]{"tga_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
|
if ($slave[$i]{"tgc_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
|
if ($slave[$i]{"tgc_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
|
printf OUTFILE " cyc_i : std_logic;\n";
|
printf OUTFILE " cyc_i : std_logic;\n";
|
printf OUTFILE " stb_i : std_logic;\n";
|
printf OUTFILE " stb_i : std_logic;\n";
|
printf OUTFILE "end record;\n";
|
printf OUTFILE "end record;\n";
|
# output record
|
# output record
|
printf OUTFILE "type %s_wbs_o_type is record\n",$slave[$i]{"wbs"};
|
printf OUTFILE "type %s_wbs_o_type is record\n",$slave[$i]{"wbs"};
|
if ($slave[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1 };
|
if ($slave[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1 };
|
if ($slave[$i]{"rty_o"} eq 1) { printf OUTFILE " rty_o : std_logic;\n" };
|
if ($slave[$i]{"rty_o"} eq 1) { printf OUTFILE " rty_o : std_logic;\n" };
|
if ($slave[$i]{"err_o"} eq 1) { printf OUTFILE " err_o : std_logic;\n" };
|
if ($slave[$i]{"err_o"} eq 1) { printf OUTFILE " err_o : std_logic;\n" };
|
printf OUTFILE " ack_o : std_logic;\n";
|
printf OUTFILE " ack_o : std_logic;\n";
|
printf OUTFILE "end record;\n";
|
printf OUTFILE "end record;\n";
|
}; #end for
|
}; #end for
|
}; #end if signal groups
|
}; #end if signal groups
|
|
|
# overload of "and"
|
# overload of "and"
|
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector;\n";
|
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector;\n";
|
printf OUTFILE "end %s_package;\n",$intercon;
|
printf OUTFILE "end %s_package;\n",$intercon;
|
printf OUTFILE "package body %s_package is\n",$intercon;
|
printf OUTFILE "package body %s_package is\n",$intercon;
|
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector is\n";
|
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector is\n";
|
printf OUTFILE " variable result : std_logic_vector(l'range);\n";
|
printf OUTFILE " variable result : std_logic_vector(l'range);\n";
|
printf OUTFILE "begin -- \"and\"\n for i in l'range loop\n result(i) := l(i) and r;\nend loop; -- i\nreturn result;\nend \"and\";\n";
|
printf OUTFILE "begin -- \"and\"\n for i in l'range loop\n result(i) := l(i) and r;\nend loop; -- i\nreturn result;\nend \"and\";\n";
|
printf OUTFILE "end %s_package;\n",$intercon;
|
printf OUTFILE "end %s_package;\n",$intercon;
|
};
|
};
|
|
|
sub gen_trafic_ctrl {
|
sub gen_trafic_ctrl {
|
if ($hdl eq "vhdl") {
|
if ($hdl eq "vhdl") {
|
if ($target eq "xilinx") {
|
if ($target eq "xilinx") {
|
print OUTFILE <<EOP;
|
print OUTFILE <<EOP;
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
entity trafic_supervision is
|
entity trafic_supervision is
|
|
|
generic (
|
generic (
|
priority : integer := 1;
|
priority : integer := 1;
|
tot_priority : integer := 2);
|
tot_priority : integer := 2);
|
|
|
port (
|
port (
|
bg : in std_logic; -- bus grant
|
bg : in std_logic; -- bus grant
|
ce : in std_logic; -- clock enable
|
ce : in std_logic; -- clock enable
|
trafic_limit : out std_logic;
|
trafic_limit : out std_logic;
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic);
|
reset : in std_logic);
|
|
|
end trafic_supervision;
|
end trafic_supervision;
|
|
|
architecture rtl of trafic_supervision is
|
architecture rtl of trafic_supervision is
|
|
|
signal shreg : std_logic_vector(tot_priority-1 downto 0);
|
signal shreg : std_logic_vector(tot_priority-1 downto 0);
|
signal cntr : integer range 0 to tot_priority;
|
signal cntr : integer range 0 to tot_priority;
|
|
|
begin -- rtl
|
begin -- rtl
|
|
|
-- purpose: holds information of usage of latest cycles
|
-- purpose: holds information of usage of latest cycles
|
-- type : sequential
|
-- type : sequential
|
-- inputs : clk, reset, ce, bg
|
-- inputs : clk, reset, ce, bg
|
-- outputs: shreg('left)
|
-- outputs: shreg('left)
|
sh_reg: process (clk)
|
sh_reg: process (clk)
|
begin -- process shreg
|
begin -- process shreg
|
if clk'event and clk = '1' then -- rising clock edge
|
if clk'event and clk = '1' then -- rising clock edge
|
if ce='1' then
|
if ce='1' then
|
shreg <= shreg(tot_priority-2 downto 0) & bg;
|
shreg <= shreg(tot_priority-2 downto 0) & bg;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sh_reg;
|
end process sh_reg;
|
|
|
-- purpose: keeps track of used cycles
|
-- purpose: keeps track of used cycles
|
-- type : sequential
|
-- type : sequential
|
-- inputs : clk, reset, shreg('left), bg, ce
|
-- inputs : clk, reset, shreg('left), bg, ce
|
-- outputs: trafic_limit
|
-- outputs: trafic_limit
|
counter: process (clk, reset)
|
counter: process (clk, reset)
|
begin -- process counter
|
begin -- process counter
|
if reset = '1' then -- asynchronous reset (active hi)
|
if reset = '1' then -- asynchronous reset (active hi)
|
cntr <= 0;
|
cntr <= 0;
|
trafic_limit <= '0';
|
trafic_limit <= '0';
|
elsif clk'event and clk = '1' then -- rising clock edge
|
elsif clk'event and clk = '1' then -- rising clock edge
|
if ce='1' then
|
if ce='1' then
|
if bg='1' and shreg(tot_priority-1)/='1' then
|
if bg='1' and shreg(tot_priority-1)/='1' then
|
cntr <= cntr + 1;
|
cntr <= cntr + 1;
|
if cntr=priority-1 then
|
if cntr=priority-1 then
|
trafic_limit <= '1';
|
trafic_limit <= '1';
|
end if;
|
end if;
|
elsif bg='0' and shreg(tot_priority-1)='1' then
|
elsif bg='0' and shreg(tot_priority-1)='1' then
|
cntr <= cntr - 1;
|
cntr <= cntr - 1;
|
if cntr=priority then
|
if cntr=priority then
|
trafic_limit <= '0';
|
trafic_limit <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process counter;
|
end process counter;
|
|
|
end rtl;
|
end rtl;
|
EOP
|
EOP
|
} else {
|
} else {
|
print OUTFILE<<EOP;
|
print OUTFILE<<EOP;
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
entity trafic_supervision is
|
entity trafic_supervision is
|
|
|
generic (
|
generic (
|
priority : integer := 1;
|
priority : integer := 1;
|
tot_priority : integer := 2);
|
tot_priority : integer := 2);
|
|
|
port (
|
port (
|
bg : in std_logic; -- bus grant
|
bg : in std_logic; -- bus grant
|
ce : in std_logic; -- clock enable
|
ce : in std_logic; -- clock enable
|
trafic_limit : out std_logic;
|
trafic_limit : out std_logic;
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic);
|
reset : in std_logic);
|
|
|
end trafic_supervision;
|
end trafic_supervision;
|
|
|
architecture rtl of trafic_supervision is
|
architecture rtl of trafic_supervision is
|
|
|
signal shreg : std_logic_vector(tot_priority-1 downto 0);
|
signal shreg : std_logic_vector(tot_priority-1 downto 0);
|
signal cntr : integer range 0 to tot_priority;
|
signal cntr : integer range 0 to tot_priority;
|
|
|
begin -- rtl
|
begin -- rtl
|
|
|
-- purpose: holds information of usage of latest cycles
|
-- purpose: holds information of usage of latest cycles
|
-- type : sequential
|
-- type : sequential
|
-- inputs : clk, reset, ce, bg
|
-- inputs : clk, reset, ce, bg
|
-- outputs: shreg('left)
|
-- outputs: shreg('left)
|
sh_reg: process (clk,reset)
|
sh_reg: process (clk,reset)
|
begin -- process shreg
|
begin -- process shreg
|
if reset = '1' then -- asynchronous reset (active hi)
|
if reset = '1' then -- asynchronous reset (active hi)
|
shreg <= (others=>'0');
|
shreg <= (others=>'0');
|
elsif clk'event and clk = '1' then -- rising clock edge
|
elsif clk'event and clk = '1' then -- rising clock edge
|
if ce='1' then
|
if ce='1' then
|
shreg <= shreg(tot_priority-2 downto 0) & bg;
|
shreg <= shreg(tot_priority-2 downto 0) & bg;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sh_reg;
|
end process sh_reg;
|
|
|
-- purpose: keeps track of used cycles
|
-- purpose: keeps track of used cycles
|
-- type : sequential
|
-- type : sequential
|
-- inputs : clk, reset, shreg('left), bg, ce
|
-- inputs : clk, reset, shreg('left), bg, ce
|
-- outputs: trafic_limit
|
-- outputs: trafic_limit
|
counter: process (clk, reset)
|
counter: process (clk, reset)
|
begin -- process counter
|
begin -- process counter
|
if reset = '1' then -- asynchronous reset (active hi)
|
if reset = '1' then -- asynchronous reset (active hi)
|
cntr <= 0;
|
cntr <= 0;
|
trafic_limit <= '0';
|
trafic_limit <= '0';
|
elsif clk'event and clk = '1' then -- rising clock edge
|
elsif clk'event and clk = '1' then -- rising clock edge
|
if ce='1' then
|
if ce='1' then
|
if bg='1' and shreg(tot_priority-1)='0' then
|
if bg='1' and shreg(tot_priority-1)='0' then
|
cntr <= cntr + 1;
|
cntr <= cntr + 1;
|
if cntr=priority-1 then
|
if cntr=priority-1 then
|
trafic_limit <= '1';
|
trafic_limit <= '1';
|
end if;
|
end if;
|
elsif bg='0' and shreg(tot_priority-1)='1' then
|
elsif bg='0' and shreg(tot_priority-1)='1' then
|
cntr <= cntr - 1;
|
cntr <= cntr - 1;
|
if cntr=priority then
|
if cntr=priority then
|
trafic_limit <= '0';
|
trafic_limit <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process counter;
|
end process counter;
|
|
|
end rtl;
|
end rtl;
|
EOP
|
EOP
|
};
|
};
|
} else {
|
} else {
|
|
|
};
|
};
|
};
|
};
|
|
|
sub gen_entity {
|
sub gen_entity {
|
# library usage
|
# library usage
|
printf OUTFILE "\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n";
|
printf OUTFILE "\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n";
|
printf OUTFILE "use work.%s_package.all;\n",$intercon;
|
printf OUTFILE "use work.%s_package.all;\n",$intercon;
|
|
|
# entity intercon
|
# entity intercon
|
printf OUTFILE "\nentity %s is\n port (\n",$intercon;
|
printf OUTFILE "\nentity %s is\n port (\n",$intercon;
|
# records
|
# records
|
if ($signal_groups eq 1) {
|
if ($signal_groups eq 1) {
|
# master port(s)
|
# master port(s)
|
printf OUTFILE " -- wishbone master port(s)\n";
|
printf OUTFILE " -- wishbone master port(s)\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
|
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_wbm_i : out %s_wbm_i_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " %s_wbm_i : out %s_wbm_i_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " %s_wbm_o : in %s_wbm_o_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " %s_wbm_o : in %s_wbm_o_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
}; #end for
|
}; #end for
|
# slave port(s)
|
# slave port(s)
|
printf OUTFILE " -- wishbone slave port(s)\n";
|
printf OUTFILE " -- wishbone slave port(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
|
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
|
printf OUTFILE " %s_wbs_i : out %s_wbs_i_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE " %s_wbs_i : out %s_wbs_i_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE " %s_wbs_o : in %s_wbs_o_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE " %s_wbs_o : in %s_wbs_o_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
};
|
};
|
# separate signals
|
# separate signals
|
} else {
|
} else {
|
printf OUTFILE " -- wishbone master port(s)\n";
|
printf OUTFILE " -- wishbone master port(s)\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
|
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
|
if ($master[$i]{"type"} ne "wo") {
|
if ($master[$i]{"type"} ne "wo") {
|
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1; };
|
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1; };
|
printf OUTFILE " %s_ack_i : out std_logic;\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_ack_i : out std_logic;\n",$master[$i]{"wbm"};
|
if ($master[$i]{"err_i"} eq 1) {
|
if ($master[$i]{"err_i"} eq 1) {
|
printf OUTFILE " %s_err_i : out std_logic;\n",$master[$i]{"wbm"}; };
|
printf OUTFILE " %s_err_i : out std_logic;\n",$master[$i]{"wbm"}; };
|
if ($master[$i]{"rty_i"} eq 1) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
printf OUTFILE " %s_rty_i : out std_logic;\n",$master[$i]{"wbm"}; };
|
printf OUTFILE " %s_rty_i : out std_logic;\n",$master[$i]{"wbm"}; };
|
if ($master[$i]{"type"} ne "ro") {
|
if ($master[$i]{"type"} ne "ro") {
|
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1;
|
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1;
|
printf OUTFILE " %s_we_o : in std_logic;\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_we_o : in std_logic;\n",$master[$i]{"wbm"};
|
};
|
};
|
if ($dat_size ge 16) {
|
if ($dat_size ge 16) {
|
printf OUTFILE " %s_sel_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size/8-1; };
|
printf OUTFILE " %s_sel_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size/8-1; };
|
printf OUTFILE " %s_adr_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$adr_size-1;
|
printf OUTFILE " %s_adr_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$adr_size-1;
|
if ($master[$i]{"tgc_o"} eq 1) {
|
if ($master[$i]{"tgc_o"} eq 1) {
|
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tgc,$tgc_bits-1; };
|
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tgc,$tgc_bits-1; };
|
if ($master[$i]{"tga_o"} eq 1) {
|
if ($master[$i]{"tga_o"} eq 1) {
|
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tga,$tga_bits-1; };
|
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tga,$tga_bits-1; };
|
printf OUTFILE " %s_cyc_o : in std_logic;\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_cyc_o : in std_logic;\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_stb_o : in std_logic;\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_stb_o : in std_logic;\n",$master[$i]{"wbm"};
|
};
|
};
|
printf OUTFILE " -- wishbone slave port(s)\n";
|
printf OUTFILE " -- wishbone slave port(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
|
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
|
if ($slave[$i]{"type"} ne "wo") {
|
if ($slave[$i]{"type"} ne "wo") {
|
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1; };
|
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1; };
|
printf OUTFILE " %s_ack_o : in std_logic;\n",$slave[$i]{"wbs"};
|
printf OUTFILE " %s_ack_o : in std_logic;\n",$slave[$i]{"wbs"};
|
if ($slave[$i]{"err_o"} eq 1) {
|
if ($slave[$i]{"err_o"} eq 1) {
|
printf OUTFILE " %s_err_o : in std_logic;\n",$slave[$i]{"wbs"}; };
|
printf OUTFILE " %s_err_o : in std_logic;\n",$slave[$i]{"wbs"}; };
|
if ($slave[$i]{"rty_o"} eq 1) {
|
if ($slave[$i]{"rty_o"} eq 1) {
|
printf OUTFILE " %s_rty_o : in std_logic;\n",$slave[$i]{"wbs"}; };
|
printf OUTFILE " %s_rty_o : in std_logic;\n",$slave[$i]{"wbs"}; };
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1;
|
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1;
|
printf OUTFILE " %s_we_i : out std_logic;\n",$slave[$i]{"wbs"};
|
printf OUTFILE " %s_we_i : out std_logic;\n",$slave[$i]{"wbs"};
|
};
|
};
|
if ($dat_size ge 16) {
|
if ($dat_size ge 16) {
|
printf OUTFILE " %s_sel_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size/8-1; };
|
printf OUTFILE " %s_sel_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size/8-1; };
|
printf OUTFILE " %s_adr_i : out std_logic_vector(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
|
printf OUTFILE " %s_adr_i : out std_logic_vector(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tgc,$tgc_bits-1; };
|
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tgc,$tgc_bits-1; };
|
if ($slave[$i]{"tga_i"} eq 1) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tga,$tga_bits-1; };
|
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tga,$tga_bits-1; };
|
printf OUTFILE " %s_cyc_i : out std_logic;\n",$slave[$i]{"wbs"};
|
printf OUTFILE " %s_cyc_i : out std_logic;\n",$slave[$i]{"wbs"};
|
printf OUTFILE " %s_stb_i : out std_logic;\n",$slave[$i]{"wbs"};
|
printf OUTFILE " %s_stb_i : out std_logic;\n",$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
# clock and reset
|
# clock and reset
|
printf OUTFILE " -- clock and reset\n";
|
printf OUTFILE " -- clock and reset\n";
|
printf OUTFILE " clk : in std_logic;\n";
|
printf OUTFILE " clk : in std_logic;\n";
|
printf OUTFILE " reset : in std_logic);\n";
|
printf OUTFILE " reset : in std_logic);\n";
|
printf OUTFILE "end %s;\n",$intercon;
|
printf OUTFILE "end %s;\n",$intercon;
|
};
|
};
|
|
|
|
|
# generate signals for remapping (for records)
|
# generate signals for remapping (for records)
|
sub gen_sig_remap {
|
sub gen_sig_remap {
|
sub gen_sig_dec {
|
sub gen_sig_dec {
|
if ($_[1] gt 0) {
|
if ($_[1] gt 0) {
|
printf OUTFILE " signal %s : std_logic_vector(%s downto %s);\n",$_[0],$_[1]-1,$_[2];
|
printf OUTFILE " signal %s : std_logic_vector(%s downto %s);\n",$_[0],$_[1]-1,$_[2];
|
} else {
|
} else {
|
printf OUTFILE " signal %s : std_logic;\n",$_[0];
|
printf OUTFILE " signal %s : std_logic;\n",$_[0];
|
};
|
};
|
};
|
};
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"type"} ne "wo") {
|
if ($master[$i]{"type"} ne "wo") {
|
gen_sig_dec($master[$i]{"wbm"}.'_dat_i',$dat_size,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_dat_i',$dat_size,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_ack_i');
|
gen_sig_dec($master[$i]{"wbm"}.'_ack_i');
|
if ($master[$i]{"err_i"} eq 1) {
|
if ($master[$i]{"err_i"} eq 1) {
|
gen_sig_dec($master[$i]{"wbm"}.'_err_i'); };
|
gen_sig_dec($master[$i]{"wbm"}.'_err_i'); };
|
if ($master[$i]{"rty_i"} eq 1) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
gen_sig_dec($master[$i]{"wbm"}.'_rty_i') };
|
gen_sig_dec($master[$i]{"wbm"}.'_rty_i') };
|
if ($master[$i]{"type"} ne "ro") {
|
if ($master[$i]{"type"} ne "ro") {
|
gen_sig_dec($master[$i]{"wbm"}.'_dat_o',$dat_size,0);
|
gen_sig_dec($master[$i]{"wbm"}.'_dat_o',$dat_size,0);
|
gen_sig_dec($master[$i]{"wbm"}.'_we_o ');
|
gen_sig_dec($master[$i]{"wbm"}.'_we_o ');
|
};
|
};
|
if ($dat_size > 8) {
|
if ($dat_size > 8) {
|
gen_sig_dec($master[$i]{"wbm"}.'_sel_o',$dat_size/8,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_sel_o',$dat_size/8,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_adr_o',$adr_size,0);
|
gen_sig_dec($master[$i]{"wbm"}.'_adr_o',$adr_size,0);
|
if ($master[$i]{"tga_o"} eq 1) {
|
if ($master[$i]{"tga_o"} eq 1) {
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tga.'_o',$tga_bits,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tga.'_o',$tga_bits,0); };
|
if ($master[$i]{"tgc_o"} eq 1) {
|
if ($master[$i]{"tgc_o"} eq 1) {
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgc.'_o',$tgc_bits,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgc.'_o',$tgc_bits,0); };
|
if ($master[$i]{"tgd_o"} eq 1) {
|
if ($master[$i]{"tgd_o"} eq 1) {
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgd.'_o',$tgd_bits,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgd.'_o',$tgd_bits,0); };
|
gen_sig_dec($master[$i]{"wbm"}.'_cyc_o');
|
gen_sig_dec($master[$i]{"wbm"}.'_cyc_o');
|
gen_sig_dec($master[$i]{"wbm"}.'_stb_o');
|
gen_sig_dec($master[$i]{"wbm"}.'_stb_o');
|
};
|
};
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"type"} ne "wo") {
|
if ($slave[$i]{"type"} ne "wo") {
|
gen_sig_dec($slave[$i]{"wbs"}.'_dat_o',$dat_size,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_dat_o',$dat_size,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_ack_o');
|
gen_sig_dec($slave[$i]{"wbs"}.'_ack_o');
|
if ($slave[$i]{"err_o"} eq 1) {
|
if ($slave[$i]{"err_o"} eq 1) {
|
gen_sig_dec($slave[$i]{"wbs"}.'_err_o'); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_err_o'); };
|
if ($slave[$i]{"rty_o"} eq 1) {
|
if ($slave[$i]{"rty_o"} eq 1) {
|
gen_sig_dec($slave[$i]{"wbs"}.'_rty_o'); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_rty_o'); };
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
gen_sig_dec($slave[$i]{"wbs"}.'_dat_i',$dat_size,0);
|
gen_sig_dec($slave[$i]{"wbs"}.'_dat_i',$dat_size,0);
|
gen_sig_dec($slave[$i]{"wbs"}.'_we_i ');
|
gen_sig_dec($slave[$i]{"wbs"}.'_we_i ');
|
};
|
};
|
if ($dat_size > 8) {
|
if ($dat_size > 8) {
|
gen_sig_dec($slave[$i]{"wbs"}.'_sel_i',$dat_size/8,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_sel_i',$dat_size/8,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_adr_i',$slave[$i]{"adr_i_hi"}+1,$slave[$i]{"adr_i_lo"});
|
gen_sig_dec($slave[$i]{"wbs"}.'_adr_i',$slave[$i]{"adr_i_hi"}+1,$slave[$i]{"adr_i_lo"});
|
if ($slave[$i]{"tga_i"} eq 1) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tga.'_i',$tga_bits,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tga.'_i',$tga_bits,0); };
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgc.'_i',$tgc_bits,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgc.'_i',$tgc_bits,0); };
|
if ($slave[$i]{"tgd_i"} eq 1) {
|
if ($slave[$i]{"tgd_i"} eq 1) {
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgd.'_i',$tgd_bits,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgd.'_i',$tgd_bits,0); };
|
gen_sig_dec($slave[$i]{"wbs"}.'_cyc_i');
|
gen_sig_dec($slave[$i]{"wbs"}.'_cyc_i');
|
gen_sig_dec($slave[$i]{"wbs"}.'_stb_i');
|
gen_sig_dec($slave[$i]{"wbs"}.'_stb_i');
|
};
|
};
|
};
|
};
|
|
|
sub gen_global_signals {
|
sub gen_global_signals {
|
# single master
|
# single master
|
if ($masters eq 1) {
|
if ($masters eq 1) {
|
# slave select for generation of stb_i to slaves
|
# slave select for generation of stb_i to slaves
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
|
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
|
# shared bus
|
# shared bus
|
} elsif ($interconnect eq "sharedbus") {
|
} elsif ($interconnect eq "sharedbus") {
|
# bus grant
|
# bus grant
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE " signal %s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"}; };
|
printf OUTFILE " signal %s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"}; };
|
# slave select for generation of stb_i to slaves
|
# slave select for generation of stb_i to slaves
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
|
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
|
# crossbarswitch
|
# crossbarswitch
|
} else {
|
} else {
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " signal %s_%s_ss : std_logic; -- slave select\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " signal %s_%s_ss : std_logic; -- slave select\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " signal %s_%s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " signal %s_%s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
|
|
sub gen_arbiter {
|
sub gen_arbiter {
|
# out: wbm_bg (bus grant)
|
# out: wbm_bg (bus grant)
|
if ($masters eq 1) {
|
if ($masters eq 1) {
|
# ack_i
|
# ack_i
|
# cyc_i
|
# cyc_i
|
# printf OUTFILE "%s_bg <= %s_cyc_o;\n",$master[1]{"wbm"},$master[1]{"wbm"};
|
# printf OUTFILE "%s_bg <= %s_cyc_o;\n",$master[1]{"wbm"},$master[1]{"wbm"};
|
# sharedbus
|
# sharedbus
|
} elsif ($interconnect eq "sharedbus") {
|
} elsif ($interconnect eq "sharedbus") {
|
printf OUTFILE "arbiter_sharedbus: block\n";
|
printf OUTFILE "arbiter_sharedbus: block\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE " signal %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE " signal %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE " signal %s_trafic_ctrl_limit : std_logic;\n",$master[$i]{"wbm"}; };
|
printf OUTFILE " signal %s_trafic_ctrl_limit : std_logic;\n",$master[$i]{"wbm"}; };
|
printf OUTFILE " signal ack, ce, idle :std_logic;\n";
|
printf OUTFILE " signal ack, ce, idle :std_logic;\n";
|
printf OUTFILE "begin -- arbiter\n";
|
printf OUTFILE "begin -- arbiter\n";
|
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
|
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
|
for ($i=2; $i le $slaves; $i++) {
|
for ($i=2; $i le $slaves; $i++) {
|
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
|
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
# instantiate trafic_supervision(s)
|
# instantiate trafic_supervision(s)
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
|
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
|
printf OUTFILE "generic map(\n";
|
printf OUTFILE "generic map(\n";
|
printf OUTFILE " priority => %s,\n",$master[$i]{"priority"};
|
printf OUTFILE " priority => %s,\n",$master[$i]{"priority"};
|
printf OUTFILE " tot_priority => %s)\n",$priority;
|
printf OUTFILE " tot_priority => %s)\n",$priority;
|
printf OUTFILE "port map(\n";
|
printf OUTFILE "port map(\n";
|
printf OUTFILE " bg => %s_bg,\n",$master[$i]{"wbm"};
|
printf OUTFILE " bg => %s_bg,\n",$master[$i]{"wbm"};
|
printf OUTFILE " ce => ce,\n";
|
printf OUTFILE " ce => ce,\n";
|
printf OUTFILE " trafic_limit => %s_trafic_ctrl_limit,\n",$master[$i]{"wbm"};
|
printf OUTFILE " trafic_limit => %s_trafic_ctrl_limit,\n",$master[$i]{"wbm"};
|
printf OUTFILE " clk => clk,\n";
|
printf OUTFILE " clk => clk,\n";
|
printf OUTFILE " reset => reset);\n"; };
|
printf OUTFILE " reset => reset);\n"; };
|
# _bg_q
|
# _bg_q
|
# bg eq 1 => set
|
# bg eq 1 => set
|
# end of cycle => reset
|
# end of cycle => reset
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
|
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
|
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE "elsif clk'event and clk='1' then\n";
|
printf OUTFILE "elsif clk'event and clk='1' then\n";
|
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
|
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "elsif ack='1'";
|
printf OUTFILE "elsif ack='1'";
|
if ($master[$i]{"tgc_o"} eq 1) {
|
if ($master[$i]{"tgc_o"} eq 1) {
|
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
|
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
|
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
|
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
|
}; # end for
|
}; # end for
|
# _bg
|
# _bg
|
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[1]{"wbm"};
|
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[1]{"wbm"};
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"}; };
|
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"}; };
|
printf OUTFILE " else '0';\n";
|
printf OUTFILE " else '0';\n";
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' else '0';\n",$master[1]{"wbm"},$master[1]{"wbm"},$master[1]{"wbm"};
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' else '0';\n",$master[1]{"wbm"},$master[1]{"wbm"},$master[1]{"wbm"};
|
$depend = $master[1]{"wbm"}."_bg_1='0'";
|
$depend = $master[1]{"wbm"}."_bg_1='0'";
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' and (%s) else '0';\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$depend;
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' and (%s) else '0';\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$depend;
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
|
};
|
};
|
|
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[1]{"wbm"},$depend,$master[1]{"wbm"};
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[1]{"wbm"},$depend,$master[1]{"wbm"};
|
$depend = $depend." and ".$master[1]{"wbm"}."_bg_2='0'";
|
$depend = $depend." and ".$master[1]{"wbm"}."_bg_2='0'";
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"};
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"};
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
|
};
|
};
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
# ce
|
# ce
|
printf OUTFILE "ce <= %s_cyc_o",$master[1]{"wbm"};
|
printf OUTFILE "ce <= %s_cyc_o",$master[1]{"wbm"};
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE " or %s_cyc_o",$master[$i]{"wbm"}; };
|
printf OUTFILE " or %s_cyc_o",$master[$i]{"wbm"}; };
|
printf OUTFILE " when idle='1' else '0';\n\n";
|
printf OUTFILE " when idle='1' else '0';\n\n";
|
# thats it
|
# thats it
|
printf OUTFILE "end block arbiter_sharedbus;\n\n";
|
printf OUTFILE "end block arbiter_sharedbus;\n\n";
|
# interconnect crossbarswitch
|
# interconnect crossbarswitch
|
} else {
|
} else {
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
# single master ?
|
# single master ?
|
$tmp=0;
|
$tmp=0;
|
for ($l=1; $l le $masters; $l++) {
|
for ($l=1; $l le $masters; $l++) {
|
if ($master[$l]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$l]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
$only_master = $l;
|
$only_master = $l;
|
$tmp++;
|
$tmp++;
|
};
|
};
|
};
|
};
|
if ($tmp == 1) {
|
if ($tmp == 1) {
|
printf OUTFILE "%s_%s_bg <= %s_%s_ss and %s_cyc_o;\n",$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"};
|
printf OUTFILE "%s_%s_bg <= %s_%s_ss and %s_cyc_o;\n",$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"};
|
} else {
|
} else {
|
printf OUTFILE "arbiter_%s : block\n",$slave[$j]{"wbs"};
|
printf OUTFILE "arbiter_%s : block\n",$slave[$j]{"wbs"};
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " signal %s_bg, %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " signal %s_bg, %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " signal %s_trafic_limit : std_logic;\n",$master[$i]{"wbm"};
|
printf OUTFILE " signal %s_trafic_limit : std_logic;\n",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE " signal ce, idle, ack : std_logic;\n";
|
printf OUTFILE " signal ce, idle, ack : std_logic;\n";
|
printf OUTFILE "begin\n";
|
printf OUTFILE "begin\n";
|
printf OUTFILE "ack <= %s_ack_o;\n",$slave[$j]{"wbs"};
|
printf OUTFILE "ack <= %s_ack_o;\n",$slave[$j]{"wbs"};
|
# instantiate trafic_supervision(s)
|
# instantiate trafic_supervision(s)
|
# calc tot priority per slave
|
# calc tot priority per slave
|
$priority = 0;
|
$priority = 0;
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
$priority += $master[$i]{("priority_".($slave[$j]{"wbs"}))}; };
|
$priority += $master[$i]{("priority_".($slave[$j]{"wbs"}))}; };
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
|
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
|
printf OUTFILE "generic map(\n";
|
printf OUTFILE "generic map(\n";
|
printf OUTFILE " priority => %s,\n",$master[$i]{("priority_".($slave[$j]{"wbs"}))};
|
printf OUTFILE " priority => %s,\n",$master[$i]{("priority_".($slave[$j]{"wbs"}))};
|
printf OUTFILE " tot_priority => %s)\n",$priority;
|
printf OUTFILE " tot_priority => %s)\n",$priority;
|
printf OUTFILE "port map(\n";
|
printf OUTFILE "port map(\n";
|
printf OUTFILE " bg => %s_%s_bg,\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " bg => %s_%s_bg,\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " ce => ce,\n";
|
printf OUTFILE " ce => ce,\n";
|
printf OUTFILE " trafic_limit => %s_trafic_limit,\n",$master[$i]{"wbm"};
|
printf OUTFILE " trafic_limit => %s_trafic_limit,\n",$master[$i]{"wbm"};
|
printf OUTFILE " clk => clk,\n";
|
printf OUTFILE " clk => clk,\n";
|
printf OUTFILE " reset => reset);\n";
|
printf OUTFILE " reset => reset);\n";
|
};
|
};
|
};
|
};
|
# _bg_q
|
# _bg_q
|
# bg eq 1 => set
|
# bg eq 1 => set
|
# end of cycle => reset
|
# end of cycle => reset
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
|
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
|
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE "elsif clk'event and clk='1' then\n";
|
printf OUTFILE "elsif clk'event and clk='1' then\n";
|
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
|
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
|
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "elsif ack='1'";
|
printf OUTFILE "elsif ack='1'";
|
if ($master[$i]{"tgc_o"} eq 1) {
|
if ($master[$i]{"tgc_o"} eq 1) {
|
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
|
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
|
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
|
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
|
};
|
};
|
}; # end for
|
}; # end for
|
# _bg
|
# _bg
|
$depend = "";
|
$depend = "";
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[$tmp]{"wbm"};
|
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[$tmp]{"wbm"};
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"};
|
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE " else '0';\n";
|
printf OUTFILE " else '0';\n";
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"},$master[$tmp]{"wbm"};
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"},$master[$tmp]{"wbm"};
|
$depend = $master[$tmp]{"wbm"}."_bg_1='0'",;
|
$depend = $master[$tmp]{"wbm"}."_bg_1='0'",;
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};;
|
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};;
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
|
};
|
};
|
};
|
};
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$tmp]{"wbm"},$depend,$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$tmp]{"wbm"},$depend,$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
|
$depend = $depend." and ".$master[$tmp]{"wbm"}."_bg_2='0'";
|
$depend = $depend." and ".$master[$tmp]{"wbm"}."_bg_2='0'";
|
$tmp1 = $tmp;
|
$tmp1 = $tmp;
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
|
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
|
};
|
};
|
};
|
};
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
# ce
|
# ce
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "ce <= (%s_cyc_o and %s_%s_ss)",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE "ce <= (%s_cyc_o and %s_%s_ss)",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
for ($i=$tmp+1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_cyc_o and %s_%s_ss)",$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " or (%s_cyc_o and %s_%s_ss)",$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE " when idle='1' else '0';\n";
|
printf OUTFILE " when idle='1' else '0';\n";
|
# global bg
|
# global bg
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "%s_%s_bg <= %s_bg;\n",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_%s_bg <= %s_bg;\n",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE "end block arbiter_%s;\n",$slave[$j]{"wbs"};
|
printf OUTFILE "end block arbiter_%s;\n",$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
}; #end if
|
}; #end if
|
};
|
};
|
|
|
sub gen_adr_decoder{
|
sub gen_adr_decoder{
|
printf OUTFILE "decoder:block\n";
|
printf OUTFILE "decoder:block\n";
|
if ($interconnect eq "sharedbus") {
|
if ($interconnect eq "sharedbus") {
|
printf OUTFILE " signal adr : std_logic_vector(%s downto 0);\n",$adr_size-1;
|
printf OUTFILE " signal adr : std_logic_vector(%s downto 0);\n",$adr_size-1;
|
printf OUTFILE "begin\n";
|
printf OUTFILE "begin\n";
|
# adr
|
# adr
|
printf OUTFILE "adr <= (%s_adr_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
printf OUTFILE "adr <= (%s_adr_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
if ($masters gt 1){
|
if ($masters gt 1){
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE " or (%s_adr_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE " or (%s_adr_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
# slave select
|
# slave select
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "%s_ss <= '1' when adr(%s downto %s)=\"",$slave[$i]{"wbs"}, $adr_size-1,log(hex($slave[$i]{"size"}))/log(2);
|
printf OUTFILE "%s_ss <= '1' when adr(%s downto %s)=\"",$slave[$i]{"wbs"}, $adr_size-1,log(hex($slave[$i]{"size"}))/log(2);
|
$slave[$i]{"baseadr"}=hex($slave[$i]{"baseadr"});
|
$slave[$i]{"baseadr"}=hex($slave[$i]{"baseadr"});
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
|
if (($slave[$i]{"baseadr"}) >= (2**$j)) {
|
if (($slave[$i]{"baseadr"}) >= (2**$j)) {
|
$slave[$i]{"baseadr"} -= 2**$j;
|
$slave[$i]{"baseadr"} -= 2**$j;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
};
|
};
|
};
|
};
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
# 1
|
# 1
|
if ($slave[$i]{"size1"} ne "ffffffff") {
|
if ($slave[$i]{"size1"} ne "ffffffff") {
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size1"}))/log(2);
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size1"}))/log(2);
|
$slave[$i]{"baseadr1"}=hex($slave[$i]{"baseadr1"});
|
$slave[$i]{"baseadr1"}=hex($slave[$i]{"baseadr1"});
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
|
if (($slave[$i]{"baseadr1"}) >= (2**$j)) {
|
if (($slave[$i]{"baseadr1"}) >= (2**$j)) {
|
$slave[$i]{"baseadr1"} -= 2**$j;
|
$slave[$i]{"baseadr1"} -= 2**$j;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
}; # end if
|
}; # end if
|
}; # end for
|
}; # end for
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
};
|
};
|
# 2
|
# 2
|
if ($slave[$i]{"size2"} ne "ffffffff") {
|
if ($slave[$i]{"size2"} ne "ffffffff") {
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size2"}))/log(2);
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size2"}))/log(2);
|
$slave[$i]{"baseadr2"}=hex($slave[$i]{"baseadr2"});
|
$slave[$i]{"baseadr2"}=hex($slave[$i]{"baseadr2"});
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
|
if (($slave[$i]{"baseadr2"}) >= (2**$j)) {
|
if (($slave[$i]{"baseadr2"}) >= (2**$j)) {
|
$slave[$i]{"baseadr2"} -= 2**$j;
|
$slave[$i]{"baseadr2"} -= 2**$j;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
};
|
};
|
};
|
};
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
};
|
};
|
# 3
|
# 3
|
if ($slave[$i]{"size3"} ne "ffffffff") {
|
if ($slave[$i]{"size3"} ne "ffffffff") {
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size3"}))/log(2);
|
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size3"}))/log(2);
|
$slave[$i]{"baseadr3"}=hex($slave[$i]{"baseadr3"});
|
$slave[$i]{"baseadr3"}=hex($slave[$i]{"baseadr3"});
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
|
for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
|
if (($slave[$i]{"baseadr3"}) >= (2**$j)) {
|
if (($slave[$i]{"baseadr3"}) >= (2**$j)) {
|
$slave[$i]{"baseadr3"} -= 2**$j;
|
$slave[$i]{"baseadr3"} -= 2**$j;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
};
|
};
|
};
|
};
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
};
|
};
|
printf OUTFILE " else\n'0';\n";
|
printf OUTFILE " else\n'0';\n";
|
# adr to slaves
|
# adr to slaves
|
};
|
};
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "%s_adr_i <= adr(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"}; };
|
printf OUTFILE "%s_adr_i <= adr(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"}; };
|
# crossbar switch
|
# crossbar switch
|
} else {
|
} else {
|
printf OUTFILE "begin\n";
|
printf OUTFILE "begin\n";
|
# master_slave_ss
|
# master_slave_ss
|
# $j=0;
|
# $j=0;
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
$slave[$j]{"baseadr"}=hex($slave[$j]{"baseadr"});
|
$slave[$j]{"baseadr"}=hex($slave[$j]{"baseadr"});
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE "%s_%s_ss <= '1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size"}))/log(2);
|
printf OUTFILE "%s_%s_ss <= '1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size"}))/log(2);
|
$tmp=hex($slave[$j]{"baseadr"});
|
$tmp=hex($slave[$j]{"baseadr"});
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
|
if ($tmp >= (2**$k)) {
|
if ($tmp >= (2**$k)) {
|
$tmp -= 2**$k;
|
$tmp -= 2**$k;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
};
|
};
|
};
|
};
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
# 2?
|
# 2?
|
if ($slave[$j]{"size1"} ne "ffffffff") {
|
if ($slave[$j]{"size1"} ne "ffffffff") {
|
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size1"}))/log(2);
|
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size1"}))/log(2);
|
$tmp=hex($slave[$j]{"baseadr1"});
|
$tmp=hex($slave[$j]{"baseadr1"});
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
|
if ($tmp >= (2**$k)) {
|
if ($tmp >= (2**$k)) {
|
$tmp -= 2**$k;
|
$tmp -= 2**$k;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
};
|
};
|
};
|
};
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
};
|
};
|
# 3?
|
# 3?
|
if ($slave[$j]{"size2"} ne "ffffffff") {
|
if ($slave[$j]{"size2"} ne "ffffffff") {
|
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size2"}))/log(2);
|
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size2"}))/log(2);
|
$tmp=hex($slave[$j]{"baseadr2"});
|
$tmp=hex($slave[$j]{"baseadr2"});
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
|
for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
|
if ($tmp >= (2**$k)) {
|
if ($tmp >= (2**$k)) {
|
$tmp -= 2**$k;
|
$tmp -= 2**$k;
|
printf OUTFILE "1";
|
printf OUTFILE "1";
|
} else {
|
} else {
|
printf OUTFILE "0";
|
printf OUTFILE "0";
|
};
|
};
|
};
|
};
|
printf OUTFILE "\"";
|
printf OUTFILE "\"";
|
};
|
};
|
printf OUTFILE " else \n'0';\n";
|
printf OUTFILE " else \n'0';\n";
|
}; #if
|
}; #if
|
};
|
};
|
};
|
};
|
# _adr_o
|
# _adr_o
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
# mux ?
|
# mux ?
|
$tmp=0;
|
$tmp=0;
|
for ($l=1; $l le $masters; $l++) {
|
for ($l=1; $l le $masters; $l++) {
|
if ($master[$l]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$l]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
$tmp++;
|
$tmp++;
|
};
|
};
|
};
|
};
|
if ($tmp eq 1) {
|
if ($tmp eq 1) {
|
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
|
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
|
printf OUTFILE "%s_adr_i <= %s_adr_o(%s downto %s);\n",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
|
printf OUTFILE "%s_adr_i <= %s_adr_o(%s downto %s);\n",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
|
} else {
|
} else {
|
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
|
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
|
printf OUTFILE "%s_adr_i <= (%s_adr_o(%s downto %s) and %s_%s_bg)",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$k]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_adr_i <= (%s_adr_o(%s downto %s) and %s_%s_bg)",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$k]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$k+1; $j le $masters; $j++) {
|
for ($j=$k+1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_adr_o(%s downto %s) and %s_%s_bg)",$master[$j]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_adr_o(%s downto %s) and %s_%s_bg)",$master[$j]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
};
|
};
|
printf OUTFILE "end block decoder;\n\n";
|
printf OUTFILE "end block decoder;\n\n";
|
};
|
};
|
|
|
sub gen_muxshb{
|
sub gen_muxshb{
|
printf OUTFILE "mux: block\n";
|
printf OUTFILE "mux: block\n";
|
printf OUTFILE " signal cyc, stb, we, ack : std_logic;\n";
|
printf OUTFILE " signal cyc, stb, we, ack : std_logic;\n";
|
if (($rty_i gt 0) && ($rty_o gt 1)) {
|
if (($rty_i gt 0) && ($rty_o gt 1)) {
|
printf OUTFILE " signal rty : std_logic;\n"; };
|
printf OUTFILE " signal rty : std_logic;\n"; };
|
if (($err_i gt 0) && ($err_o gt 1)) {
|
if (($err_i gt 0) && ($err_o gt 1)) {
|
printf OUTFILE " signal err : std_logic;\n"; };
|
printf OUTFILE " signal err : std_logic;\n"; };
|
if ($dat_size eq 8) {
|
if ($dat_size eq 8) {
|
printf OUTFILE " signal sel : std_logic;\n";
|
printf OUTFILE " signal sel : std_logic;\n";
|
} else {
|
} else {
|
printf OUTFILE " signal sel : std_logic_vector(%s downto 0);\n",$dat_size/8-1;
|
printf OUTFILE " signal sel : std_logic_vector(%s downto 0);\n",$dat_size/8-1;
|
};
|
};
|
printf OUTFILE " signal dat_m2s, dat_s2m : std_logic_vector(%s downto 0);\n",$dat_size-1;
|
printf OUTFILE " signal dat_m2s, dat_s2m : std_logic_vector(%s downto 0);\n",$dat_size-1;
|
if (($tgc_o gt 0) && ($tgc_i gt 0)) {
|
if (($tgc_o gt 0) && ($tgc_i gt 0)) {
|
printf OUTFILE " signal tgc : std_logic_vector(%s downto 0);\n",$tgc_bits-1; };
|
printf OUTFILE " signal tgc : std_logic_vector(%s downto 0);\n",$tgc_bits-1; };
|
if (($tga_o gt 0) && ($tga_i gt 0)) {
|
if (($tga_o gt 0) && ($tga_i gt 0)) {
|
printf OUTFILE " signal tga : std_logic_vector(%s downto 0);\n",$tga_bits-1; };
|
printf OUTFILE " signal tga : std_logic_vector(%s downto 0);\n",$tga_bits-1; };
|
printf OUTFILE "begin\n";
|
printf OUTFILE "begin\n";
|
# cyc
|
# cyc
|
printf OUTFILE "cyc <= (%s_cyc_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
printf OUTFILE "cyc <= (%s_cyc_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
if ($masters gt 1) {
|
if ($masters gt 1) {
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE " or (%s_cyc_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE " or (%s_cyc_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "%s_cyc_i <= %s_ss and cyc;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_cyc_i <= %s_ss and cyc;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
# stb
|
# stb
|
printf OUTFILE "stb <= (%s_stb_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
printf OUTFILE "stb <= (%s_stb_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
if ($masters gt 1) {
|
if ($masters gt 1) {
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE " or (%s_stb_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE " or (%s_stb_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "%s_stb_i <= stb;\n",$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_stb_i <= stb;\n",$slave[$i]{"wbs"}; };
|
# we
|
# we
|
$i=1; until ($master[$i]{"type"} ne "ro") {$i++};
|
$i=1; until ($master[$i]{"type"} ne "ro") {$i++};
|
printf OUTFILE "we <= (%s_we_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "we <= (%s_we_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
if ($i lt $masters) {
|
if ($i lt $masters) {
|
for ($j=$i+1; $j le $masters; $j++) {
|
for ($j=$i+1; $j le $masters; $j++) {
|
if ($master[$j]{"type"} ne "ro") {
|
if ($master[$j]{"type"} ne "ro") {
|
printf OUTFILE " or (%s_we_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
|
printf OUTFILE " or (%s_we_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
|
};
|
};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
printf OUTFILE "%s_we_i <= we;\n",$slave[$i]{"wbs"};
|
printf OUTFILE "%s_we_i <= we;\n",$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
# ack
|
# ack
|
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
|
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
|
for ($i=2; $i le $slaves; $i++) {
|
for ($i=2; $i le $slaves; $i++) {
|
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
|
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
printf OUTFILE "%s_ack_i <= ack and %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE "%s_ack_i <= ack and %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
# rty
|
# rty
|
if (($rty_o eq 0) && ($rty_i gt 0)) {
|
if (($rty_o eq 0) && ($rty_i gt 0)) {
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
} elsif (($rty_o eq 1) && ($rty_i gt 0)) {
|
} elsif (($rty_o eq 1) && ($rty_i gt 0)) {
|
$i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
|
$i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if ($master[$j]{"rty_i"} eq 1) {
|
if ($master[$j]{"rty_i"} eq 1) {
|
printf OUTFILE "%s_rty_i <= %s_rty_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_rty_i <= %s_rty_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
} elsif (($rty_o gt 1) && ($rty_i gt 0)) {
|
} elsif (($rty_o gt 1) && ($rty_i gt 0)) {
|
$i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
|
$i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
|
printf OUTFILE "rty <= %s_rty_o",$slave[$i]{"wbs"};
|
printf OUTFILE "rty <= %s_rty_o",$slave[$i]{"wbs"};
|
for ($j=$i+1; $j le $slaves; $j++) {
|
for ($j=$i+1; $j le $slaves; $j++) {
|
if ($slave[$j]{"rty_o"} eq 1) {
|
if ($slave[$j]{"rty_o"} eq 1) {
|
printf OUTFILE " or %s_rty_o",$slave[$j]{"wbs"};
|
printf OUTFILE " or %s_rty_o",$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
printf OUTFILE "%s_rty_i <= rty;\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_rty_i <= rty;\n",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
};
|
};
|
# err
|
# err
|
if (($err_o eq 0) && ($err_i gt 0)) {
|
if (($err_o eq 0) && ($err_i gt 0)) {
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"err_i"} eq 1) {
|
if ($master[$i]{"err_i"} eq 1) {
|
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
} elsif (($err_o eq 1) && ($err_i gt 0)) {
|
} elsif (($err_o eq 1) && ($err_i gt 0)) {
|
$i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
|
$i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if ($master[$j]{"err_i"} eq 1) {
|
if ($master[$j]{"err_i"} eq 1) {
|
printf OUTFILE "%s_err_i <= %s_err_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_err_i <= %s_err_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
} elsif (($err_o gt 1) && ($err_i gt 0)) {
|
} elsif (($err_o gt 1) && ($err_i gt 0)) {
|
$i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
|
$i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
|
printf OUTFILE "err <= %s_err_o",$slave[$i]{"wbs"};
|
printf OUTFILE "err <= %s_err_o",$slave[$i]{"wbs"};
|
for ($j=$i+1; $j le $slaves; $j++) {
|
for ($j=$i+1; $j le $slaves; $j++) {
|
if ($slave[$j]{"err_o"} eq 1) {
|
if ($slave[$j]{"err_o"} eq 1) {
|
printf OUTFILE " or %s_err_o",$slave[$j]{"wbs"};
|
printf OUTFILE " or %s_err_o",$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"err_i"} eq 1) {
|
if ($master[$i]{"err_i"} eq 1) {
|
printf OUTFILE "%s_err_i <= err;\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_err_i <= err;\n",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
};
|
};
|
# sel
|
# sel
|
printf OUTFILE "sel <= (%s_sel_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
printf OUTFILE "sel <= (%s_sel_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
|
if ($masters gt 1) {
|
if ($masters gt 1) {
|
for ($i=2; $i le $masters; $i++) {
|
for ($i=2; $i le $masters; $i++) {
|
printf OUTFILE " or (%s_sel_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE " or (%s_sel_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
printf OUTFILE "%s_sel_i <= sel;\n",$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_sel_i <= sel;\n",$slave[$i]{"wbs"}; };
|
# data m2s
|
# data m2s
|
$i=1; until ($master[$i]{"type"} ne "ro") {$i++};
|
$i=1; until ($master[$i]{"type"} ne "ro") {$i++};
|
printf OUTFILE "dat_m2s <= (%s_dat_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "dat_m2s <= (%s_dat_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
if ($i lt $masters) {
|
if ($i lt $masters) {
|
for ($j=$i+1; $j le $masters; $j++) {
|
for ($j=$i+1; $j le $masters; $j++) {
|
printf OUTFILE " or (%s_dat_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
|
printf OUTFILE " or (%s_dat_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
printf OUTFILE "%s_dat_i <= dat_m2s;\n",$slave[$i]{"wbs"};
|
printf OUTFILE "%s_dat_i <= dat_m2s;\n",$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
# data s2m
|
# data s2m
|
$i=1; until ($slave[$i]{"type"} ne "wo") {$i++};
|
$i=1; until ($slave[$i]{"type"} ne "wo") {$i++};
|
printf OUTFILE "dat_s2m <= (%s_dat_o and %s_ss)",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "dat_s2m <= (%s_dat_o and %s_ss)",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
if ($i lt $slaves) {
|
if ($i lt $slaves) {
|
for ($j=$i+1; $j le $slaves; $j++) {
|
for ($j=$i+1; $j le $slaves; $j++) {
|
printf OUTFILE " or (%s_dat_o and %s_ss)",$slave[$j]{"wbs"},$slave[$j]{"wbs"};
|
printf OUTFILE " or (%s_dat_o and %s_ss)",$slave[$j]{"wbs"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"type"} ne "wo") {
|
if ($master[$i]{"type"} ne "wo") {
|
printf OUTFILE "%s_dat_i <= dat_s2m;\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_dat_i <= dat_s2m;\n",$master[$i]{"wbm"};
|
};
|
};
|
};
|
};
|
# tgc
|
# tgc
|
if (($tgc_o eq 0) && ($tgc_i gt 0)) {
|
if (($tgc_o eq 0) && ($tgc_i gt 0)) {
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
printf OUTFILE "%s_%s_i <= %s;\n",$slave[$i]{"wbs"},$rename_tgc,$classic;
|
printf OUTFILE "%s_%s_i <= %s;\n",$slave[$i]{"wbs"},$rename_tgc,$classic;
|
};
|
};
|
};
|
};
|
} elsif (($tgc_o gt 0) && ($tgc_i gt 0)) {
|
} elsif (($tgc_o gt 0) && ($tgc_i gt 0)) {
|
$i=1; until ($master[$i]{"tgc_o"} eq 1) {$i++};
|
$i=1; until ($master[$i]{"tgc_o"} eq 1) {$i++};
|
printf OUTFILE "tgc <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"};
|
printf OUTFILE "tgc <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"};
|
for ($j=$i+1; $j le $masters; $j++) {
|
for ($j=$i+1; $j le $masters; $j++) {
|
if ($master[$j]{"tgc_o"} eq 1) {
|
if ($master[$j]{"tgc_o"} eq 1) {
|
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"};
|
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
printf OUTFILE "%s_%s_i <= tgc;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"};
|
printf OUTFILE "%s_%s_i <= tgc;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
};
|
};
|
# tga
|
# tga
|
if (($tga_o eq 0) && ($tga_i gt 0)) {
|
if (($tga_o eq 0) && ($tga_i gt 0)) {
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
printf OUTFILE "%s_%s_i <= (others=>'0');\n",$slave[$i]{"wbs"},$rename_tga;
|
printf OUTFILE "%s_%s_i <= (others=>'0');\n",$slave[$i]{"wbs"},$rename_tga;
|
};
|
};
|
};
|
};
|
} elsif (($tga_o gt 0) && ($tga_i gt 0)) {
|
} elsif (($tga_o gt 0) && ($tga_i gt 0)) {
|
$i=1; until ($master[$i]{"tga_o"} eq 1) {$i++};
|
$i=1; until ($master[$i]{"tga_o"} eq 1) {$i++};
|
printf OUTFILE "tga <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"};
|
printf OUTFILE "tga <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"};
|
for ($j=$i+1; $j le $masters; $j++) {
|
for ($j=$i+1; $j le $masters; $j++) {
|
if ($master[$j]{"tga_o"} eq 1) {
|
if ($master[$j]{"tga_o"} eq 1) {
|
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"};
|
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
printf OUTFILE "%s_%s_i <= tga;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"};
|
printf OUTFILE "%s_%s_i <= tga;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
};
|
};
|
# end block
|
# end block
|
printf OUTFILE "end block mux;\n\n";
|
printf OUTFILE "end block mux;\n\n";
|
};
|
};
|
|
|
sub gen_muxcbs{
|
sub gen_muxcbs{
|
# cyc
|
# cyc
|
printf OUTFILE "-- cyc_i(s)\n";
|
printf OUTFILE "-- cyc_i(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_cyc_i <= (%s_cyc_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_cyc_i <= (%s_cyc_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_cyc_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_cyc_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
# stb
|
# stb
|
printf OUTFILE "-- stb_i(s)\n";
|
printf OUTFILE "-- stb_i(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_stb_i <= (%s_stb_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_stb_i <= (%s_stb_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_stb_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_stb_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
# we
|
# we
|
printf OUTFILE "-- we_i(s)\n";
|
printf OUTFILE "-- we_i(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
|
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
|
printf OUTFILE "%s_we_i <= (%s_we_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_we_i <= (%s_we_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
printf OUTFILE " or (%s_we_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_we_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
# ack
|
# ack
|
printf OUTFILE "-- ack_i(s)\n";
|
printf OUTFILE "-- ack_i(s)\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_ack_i <= (%s_ack_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
printf OUTFILE "%s_ack_i <= (%s_ack_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_ack_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " or (%s_ack_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
# rty
|
# rty
|
printf OUTFILE "-- rty_i(s)\n";
|
printf OUTFILE "-- rty_i(s)\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
$rty_o=0;
|
$rty_o=0;
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if (($slave[$j]{"rty_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
|
if (($slave[$j]{"rty_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
|
$rty_o+=1;
|
$rty_o+=1;
|
};
|
};
|
};
|
};
|
if ($rty_o eq 0) {
|
if ($rty_o eq 0) {
|
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
|
} else {
|
} else {
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_rty_i <= (%s_rty_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
printf OUTFILE "%s_rty_i <= (%s_rty_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_rty_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " or (%s_rty_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
};
|
};
|
# err
|
# err
|
printf OUTFILE "-- err_i(s)\n";
|
printf OUTFILE "-- err_i(s)\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"err_i"} eq 1) {
|
if ($master[$i]{"err_i"} eq 1) {
|
$err_o=0;
|
$err_o=0;
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if (($slave[$j]{"err_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
|
if (($slave[$j]{"err_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
|
$err_o+=1;
|
$err_o+=1;
|
};
|
};
|
};
|
};
|
if ($err_o eq 0) {
|
if ($err_o eq 0) {
|
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
|
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
|
} else {
|
} else {
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_err_i <= (%s_err_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
printf OUTFILE "%s_err_i <= (%s_err_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_err_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " or (%s_err_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
};
|
};
|
# sel
|
# sel
|
printf OUTFILE "-- sel_i(s)\n";
|
printf OUTFILE "-- sel_i(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($dat_size >= 16) {
|
if ($dat_size >= 16) {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_sel_i <= (%s_sel_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_sel_i <= (%s_sel_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
printf OUTFILE " or (%s_sel_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_sel_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
# dat
|
# dat
|
printf OUTFILE "-- slave dat_i(s)\n";
|
printf OUTFILE "-- slave dat_i(s)\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
$tmp=0;
|
$tmp=0;
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
$tmp+=1;
|
$tmp+=1;
|
};
|
};
|
};
|
};
|
if ($tmp eq 1) {
|
if ($tmp eq 1) {
|
$j=1; until (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {$j++};
|
$j=1; until (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {$j++};
|
printf OUTFILE "%s_dat_i <= %s_dat_o;\n",$slave[$i]{"wbs"},$master[$j]{"wbm"};
|
printf OUTFILE "%s_dat_i <= %s_dat_o;\n",$slave[$i]{"wbs"},$master[$j]{"wbm"};
|
} elsif ($tmp >= 1) {
|
} elsif ($tmp >= 1) {
|
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
|
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
|
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
|
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
};
|
};
|
printf OUTFILE "-- master dat_i(s)\n";
|
printf OUTFILE "-- master dat_i(s)\n";
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"type"} ne "wo") {
|
if ($master[$i]{"type"} ne "wo") {
|
$tmp=0;
|
$tmp=0;
|
for ($j=1; $j le $slaves; $j++) {
|
for ($j=1; $j le $slaves; $j++) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
|
$tmp+=1;
|
$tmp+=1;
|
};
|
};
|
};
|
};
|
if ($tmp eq 1) {
|
if ($tmp eq 1) {
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_dat_i <= %s_dat_o",$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
printf OUTFILE "%s_dat_i <= %s_dat_o",$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
} else {
|
} else {
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
|
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
for ($j=$tmp+1; $j le $slaves; $j++) {
|
if (($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) && ($master[$i]{"type"} ne "wo")) {
|
if (($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) && ($master[$i]{"type"} ne "wo")) {
|
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
|
};
|
};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
# tgc
|
# tgc
|
printf OUTFILE "-- tgc_i\n";
|
printf OUTFILE "-- tgc_i\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
$tmp=0;
|
$tmp=0;
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
$tmp+=1;
|
$tmp+=1;
|
};
|
};
|
};
|
};
|
if ($tmp eq 1) {
|
if ($tmp eq 1) {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc;
|
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc;
|
} else {
|
} else {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{"tga_o"} eq 1) {
|
if ($master[$j]{"tga_o"} eq 1) {
|
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
} else {
|
} else {
|
if ($classic ne "000") {
|
if ($classic ne "000") {
|
printf OUTFILE " or \"%s\"",$classic;
|
printf OUTFILE " or \"%s\"",$classic;
|
};
|
};
|
};
|
};
|
|
|
};
|
};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
# tga
|
# tga
|
printf OUTFILE "-- tga_i\n";
|
printf OUTFILE "-- tga_i\n";
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
$tmp=0;
|
$tmp=0;
|
for ($j=1; $j le $masters; $j++) {
|
for ($j=1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
$tmp+=1;
|
$tmp+=1;
|
};
|
};
|
};
|
};
|
if ($tmp eq 1) {
|
if ($tmp eq 1) {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga;
|
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga;
|
} else {
|
} else {
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
|
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
for ($j=$tmp+1; $j le $masters; $j++) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
|
if ($master[$j]{"tga_o"} eq 1) {
|
if ($master[$j]{"tga_o"} eq 1) {
|
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
};
|
printf OUTFILE ";\n";
|
printf OUTFILE ";\n";
|
};
|
};
|
};
|
};
|
};
|
};
|
|
|
sub gen_remap{
|
sub gen_remap{
|
for ($i=1; $i le $masters; $i++) {
|
for ($i=1; $i le $masters; $i++) {
|
if ($master[$i]{"type"} ne "wo") {
|
if ($master[$i]{"type"} ne "wo") {
|
printf OUTFILE "%s_wbm_i.dat_i <= %s_dat_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE "%s_wbm_i.dat_i <= %s_dat_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE "%s_wbm_i.ack_i <= %s_ack_i ;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_wbm_i.ack_i <= %s_ack_i ;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
if ($master[$i]{"err_i"} eq 1) {
|
if ($master[$i]{"err_i"} eq 1) {
|
printf OUTFILE "%s_wbm_i.err_i <= %s_err_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE "%s_wbm_i.err_i <= %s_err_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
if ($master[$i]{"rty_i"} eq 1) {
|
if ($master[$i]{"rty_i"} eq 1) {
|
printf OUTFILE "%s_wbm_i.rty_i <= %s_rty_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
printf OUTFILE "%s_wbm_i.rty_i <= %s_rty_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
|
if ($master[$i]{"type"} ne "ro") {
|
if ($master[$i]{"type"} ne "ro") {
|
printf OUTFILE "%s_dat_o <= %s_wbm_o.dat_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_dat_o <= %s_wbm_o.dat_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_we_o <= %s_wbm_o.we_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_we_o <= %s_wbm_o.we_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
};
|
};
|
printf OUTFILE "%s_sel_o <= %s_wbm_o.sel_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_sel_o <= %s_wbm_o.sel_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_adr_o <= %s_wbm_o.adr_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_adr_o <= %s_wbm_o.adr_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
if ($master[$i]{"tgc_o"} eq 1) {
|
if ($master[$i]{"tgc_o"} eq 1) {
|
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"},$rename_tgc; };
|
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"},$rename_tgc; };
|
if ($master[$i]{"tga_o"} eq 1) {
|
if ($master[$i]{"tga_o"} eq 1) {
|
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"},$rename_tga; };
|
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"},$rename_tga; };
|
printf OUTFILE "%s_cyc_o <= %s_wbm_o.cyc_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_cyc_o <= %s_wbm_o.cyc_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_stb_o <= %s_wbm_o.stb_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
printf OUTFILE "%s_stb_o <= %s_wbm_o.stb_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
|
};
|
};
|
for ($i=1; $i le $slaves; $i++) {
|
for ($i=1; $i le $slaves; $i++) {
|
if ($slave[$i]{"type"} ne "wo") {
|
if ($slave[$i]{"type"} ne "wo") {
|
printf OUTFILE "%s_dat_o <= %s_wbs_o.dat_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_dat_o <= %s_wbs_o.dat_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_ack_o <= %s_wbs_o.ack_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_ack_o <= %s_wbs_o.ack_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
if ($slave[$i]{"err_o"} eq 1) {
|
if ($slave[$i]{"err_o"} eq 1) {
|
printf OUTFILE "%s_err_o <= %s_wbs_o.err_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_err_o <= %s_wbs_o.err_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
if ($slave[$i]{"rty_o"} eq 1) {
|
if ($slave[$i]{"rty_o"} eq 1) {
|
printf OUTFILE "%s_rty_o <= %s_wbs_o.rty_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
printf OUTFILE "%s_rty_o <= %s_wbs_o.rty_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
|
if ($slave[$i]{"type"} ne "ro") {
|
if ($slave[$i]{"type"} ne "ro") {
|
printf OUTFILE "%s_wbs_i.dat_i <= %s_dat_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.dat_i <= %s_dat_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.we_i <= %s_we_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.we_i <= %s_we_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
};
|
};
|
printf OUTFILE "%s_wbs_i.sel_i <= %s_sel_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.sel_i <= %s_sel_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.adr_i <= %s_adr_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.adr_i <= %s_adr_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
if ($slave[$i]{"tgc_i"} eq 1) {
|
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"},$rename_tgc; };
|
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"},$rename_tgc; };
|
if ($slave[$i]{"tga_i"} eq 1) {
|
if ($slave[$i]{"tga_i"} eq 1) {
|
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"},$rename_tga; };
|
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"},$rename_tga; };
|
printf OUTFILE "%s_wbs_i.cyc_i <= %s_cyc_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.cyc_i <= %s_cyc_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.stb_i <= %s_stb_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
printf OUTFILE "%s_wbs_i.stb_i <= %s_stb_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
|
};
|
};
|
};
|
};
|
|
|
# GUI
|
# GUI
|
$tmp=shift;
|
$tmp=shift;
|
if ($tmp eq "-nogui") {
|
if ($tmp eq "-nogui") {
|
$infile = shift;
|
$infile = shift;
|
read_defines($infile);
|
read_defines($infile);
|
} else {
|
} else {
|
if ($tmp ne <undef>) {
|
if ($tmp ne <undef>) {
|
$infile=$tmp;
|
$infile=$tmp;
|
read_defines($infile);
|
read_defines($infile);
|
};
|
};
|
gui_fsm;
|
gui_fsm;
|
generate_defines($infile);
|
generate_defines($infile);
|
read_defines($infile);
|
read_defines($infile);
|
};
|
};
|
|
|
# main
|
# main
|
open(OUTFILE,">$outfile$ext") or die "could not write to $outfile$ext";
|
open(OUTFILE,">$outfile$ext") or die "could not write to $outfile$ext";
|
gen_header;
|
gen_header;
|
if ($hdl eq 'vhdl') {
|
if ($hdl eq 'vhdl') {
|
gen_vhdl_package;
|
gen_vhdl_package;
|
gen_trafic_ctrl;
|
gen_trafic_ctrl;
|
gen_entity;
|
gen_entity;
|
printf OUTFILE "architecture rtl of %s is\n",$intercon;
|
printf OUTFILE "architecture rtl of %s is\n",$intercon;
|
if ($signal_groups == 1) { gen_sig_remap; };
|
if ($signal_groups == 1) { gen_sig_remap; };
|
gen_global_signals;
|
gen_global_signals;
|
printf OUTFILE "begin -- rtl\n";
|
printf OUTFILE "begin -- rtl\n";
|
gen_arbiter;
|
gen_arbiter;
|
gen_adr_decoder;
|
gen_adr_decoder;
|
if ($interconnect eq 'sharedbus') {
|
if ($interconnect eq 'sharedbus') {
|
gen_muxshb;
|
gen_muxshb;
|
} else {
|
} else {
|
gen_muxcbs;
|
gen_muxcbs;
|
};
|
};
|
if ($signal_groups == 1) { gen_remap; };
|
if ($signal_groups == 1) { gen_remap; };
|
printf OUTFILE "end rtl;";
|
printf OUTFILE "end rtl;";
|
} else {
|
} else {
|
|
|
};
|
};
|
close(OUTFILE);
|
close(OUTFILE);
|
|
|