/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE Slave Model ////
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//// WISHBONE Slave Model ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_slv_model.v,v 1.2 2002-02-01 01:55:44 rudi Exp $
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// $Id: wb_slv_model.v,v 1.2 2002-02-01 01:55:44 rudi Exp $
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//
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//
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// $Date: 2002-02-01 01:55:44 $
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// $Date: 2002-02-01 01:55:44 $
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// $Revision: 1.2 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 08:57:02 rudi
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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// 2) Added restart signal (REST)
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//
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//
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// Revision 1.1.1.1 2001/03/19 13:11:29 rudi
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// Revision 1.1.1.1 2001/03/19 13:11:29 rudi
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// Initial Release
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// Initial Release
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//
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//
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//
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//
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//
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//
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`include "wb_model_defines.v"
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`include "wb_model_defines.v"
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module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
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module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
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input clk, rst;
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input clk, rst;
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input [31:0] adr, din;
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input [31:0] adr, din;
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output [31:0] dout;
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output [31:0] dout;
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input cyc, stb;
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input cyc, stb;
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input [3:0] sel;
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input [3:0] sel;
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input we;
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input we;
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output ack, err, rty;
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output ack, err, rty;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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parameter mem_size = 13;
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parameter mem_size = 13;
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parameter sz = (1<<mem_size)-1;
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parameter sz = (1<<mem_size)-1;
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reg [31:0] mem[sz:0];
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reg [31:0] mem[sz:0];
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wire mem_re, mem_we;
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wire mem_re, mem_we;
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wire [31:0] tmp;
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wire [31:0] tmp;
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reg [31:0] dout, tmp2;
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reg [31:0] dout, tmp2;
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reg err, rty;
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reg err, rty;
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reg [31:0] del_ack;
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reg [31:0] del_ack;
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reg [5:0] delay;
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reg [5:0] delay;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Logic
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// Memory Logic
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//
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//
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initial
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initial
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begin
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begin
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delay = 0;
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delay = 0;
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err = 0;
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err = 0;
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rty = 0;
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rty = 0;
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#2;
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#2;
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$display("\nINFO: WISHBONE MEMORY MODEL INSTANTIATED (%m)");
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$display("\nINFO: WISHBONE MEMORY MODEL INSTANTIATED (%m)");
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$display(" Memory Size %0d address lines %0d words\n",
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$display(" Memory Size %0d address lines %0d words\n",
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mem_size, sz+1);
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mem_size, sz+1);
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end
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end
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assign mem_re = cyc & stb & !we;
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assign mem_re = cyc & stb & !we;
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assign mem_we = cyc & stb & we;
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assign mem_we = cyc & stb & we;
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assign tmp = mem[adr[mem_size+1:2]];
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assign tmp = mem[adr[mem_size+1:2]];
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always @(sel or tmp or mem_re or ack)
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always @(sel or tmp or mem_re or ack)
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if(mem_re & ack)
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if(mem_re & ack)
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begin
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begin
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dout[31:24] <= #1 sel[3] ? tmp[31:24] : 8'hxx;
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dout[31:24] <= #1 sel[3] ? tmp[31:24] : 8'hxx;
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dout[23:16] <= #1 sel[2] ? tmp[23:16] : 8'hxx;
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dout[23:16] <= #1 sel[2] ? tmp[23:16] : 8'hxx;
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dout[15:08] <= #1 sel[1] ? tmp[15:08] : 8'hxx;
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dout[15:08] <= #1 sel[1] ? tmp[15:08] : 8'hxx;
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dout[07:00] <= #1 sel[0] ? tmp[07:00] : 8'hxx;
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dout[07:00] <= #1 sel[0] ? tmp[07:00] : 8'hxx;
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end
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end
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else dout <= #1 32'hzzzz_zzzz;
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else dout <= #1 32'hzzzz_zzzz;
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always @(sel or tmp or din)
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always @(sel or tmp or din)
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begin
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begin
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tmp2[31:24] = !sel[3] ? tmp[31:24] : din[31:24];
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tmp2[31:24] = !sel[3] ? tmp[31:24] : din[31:24];
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tmp2[23:16] = !sel[2] ? tmp[23:16] : din[23:16];
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tmp2[23:16] = !sel[2] ? tmp[23:16] : din[23:16];
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tmp2[15:08] = !sel[1] ? tmp[15:08] : din[15:08];
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tmp2[15:08] = !sel[1] ? tmp[15:08] : din[15:08];
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tmp2[07:00] = !sel[0] ? tmp[07:00] : din[07:00];
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tmp2[07:00] = !sel[0] ? tmp[07:00] : din[07:00];
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;
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if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;
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always @(posedge clk)
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always @(posedge clk)
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del_ack = ack ? 0 : {del_ack[30:0], (mem_re | mem_we)};
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del_ack = ack ? 0 : {del_ack[30:0], (mem_re | mem_we)};
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assign #3 ack = cyc & ((delay==0) ? (mem_re | mem_we) : del_ack[delay-1]);
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assign #3 ack = cyc & ((delay==0) ? (mem_re | mem_we) : del_ack[delay-1]);
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task fill_mem;
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task fill_mem;
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input mode;
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input mode;
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integer n, mode;
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integer n, mode;
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begin
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begin
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for(n=0;n<(sz+1);n=n+1)
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for(n=0;n<(sz+1);n=n+1)
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begin
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begin
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case(mode)
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case(mode)
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0: mem[n] = { ~n[15:0], n[15:0] };
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0: mem[n] = { ~n[15:0], n[15:0] };
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1: mem[n] = $random;
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1: mem[n] = $random;
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endcase
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endcase
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end
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end
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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