/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE DMA DMA Engine Core ////
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//// WISHBONE DMA DMA Engine Core ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
|
//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_dma_de.v,v 1.3 2002-02-01 01:54:45 rudi Exp $
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// $Id: wb_dma_de.v,v 1.3 2002-02-01 01:54:45 rudi Exp $
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//
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//
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// $Date: 2002-02-01 01:54:45 $
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// $Date: 2002-02-01 01:54:45 $
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// $Revision: 1.3 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/15 05:40:30 rudi
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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//
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// - Changed IO names to be more clear.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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// - Added Section 3.10, describing DMA restart.
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//
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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// 2) Added restart signal (REST)
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//
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//
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// Revision 1.3 2001/06/13 02:26:48 rudi
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// Revision 1.3 2001/06/13 02:26:48 rudi
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//
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//
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//
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//
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// Small changes after running lint.
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// Small changes after running lint.
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//
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//
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// Revision 1.2 2001/06/05 10:22:36 rudi
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// Revision 1.2 2001/06/05 10:22:36 rudi
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//
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//
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//
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//
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// - Added Support of up to 31 channels
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// - Added Support of up to 31 channels
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// - Added support for 2,4 and 8 priority levels
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// - Added support for 2,4 and 8 priority levels
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// - Now can have up to 31 channels
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// - Now can have up to 31 channels
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// - Added many configuration items
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// - Added many configuration items
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// - Changed reset to async
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// - Changed reset to async
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//
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//
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// Revision 1.1.1.1 2001/03/19 13:10:44 rudi
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// Revision 1.1.1.1 2001/03/19 13:10:44 rudi
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// Initial Release
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// Initial Release
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//
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//
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//
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//
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//
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//
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|
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`include "wb_dma_defines.v"
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`include "wb_dma_defines.v"
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|
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module wb_dma_de(clk, rst,
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module wb_dma_de(clk, rst,
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|
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// WISHBONE MASTER INTERFACE 0
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// WISHBONE MASTER INTERFACE 0
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mast0_go, mast0_we, mast0_adr, mast0_din,
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mast0_go, mast0_we, mast0_adr, mast0_din,
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mast0_dout, mast0_err, mast0_drdy, mast0_wait,
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mast0_dout, mast0_err, mast0_drdy, mast0_wait,
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|
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// WISHBONE MASTER INTERFACE 1
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// WISHBONE MASTER INTERFACE 1
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mast1_go, mast1_we, mast1_adr, mast1_din,
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mast1_go, mast1_we, mast1_adr, mast1_din,
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mast1_dout, mast1_err, mast1_drdy, mast1_wait,
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mast1_dout, mast1_err, mast1_drdy, mast1_wait,
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|
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// DMA Engine Init & Setup
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// DMA Engine Init & Setup
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de_start, nd, csr, pointer, pointer_s, txsz,
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de_start, nd, csr, pointer, pointer_s, txsz,
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adr0, adr1, am0, am1,
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adr0, adr1, am0, am1,
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|
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// DMA Engine Register File Update Outputs
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// DMA Engine Register File Update Outputs
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de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set,
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de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set,
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de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr,
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de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr,
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|
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// DMA Engine Control Outputs
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// DMA Engine Control Outputs
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next_ch, de_ack,
|
next_ch, de_ack,
|
|
|
// DMA Engine Status
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// DMA Engine Status
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pause_req, paused,
|
pause_req, paused,
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dma_abort, dma_busy, dma_err, dma_done, dma_done_all
|
dma_abort, dma_busy, dma_err, dma_done, dma_done_all
|
);
|
);
|
|
|
input clk, rst;
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input clk, rst;
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|
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// --------------------------------------
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// --------------------------------------
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// WISHBONE MASTER INTERFACE 0
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// WISHBONE MASTER INTERFACE 0
|
|
|
output mast0_go; // Perform a Master Cycle
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output mast0_go; // Perform a Master Cycle
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output mast0_we; // Read/Write
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output mast0_we; // Read/Write
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output [31:0] mast0_adr; // Address for the transfer
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output [31:0] mast0_adr; // Address for the transfer
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input [31:0] mast0_din; // Internal Input Data
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input [31:0] mast0_din; // Internal Input Data
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output [31:0] mast0_dout; // Internal Output Data
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output [31:0] mast0_dout; // Internal Output Data
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input mast0_err; // Indicates an error has occurred
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input mast0_err; // Indicates an error has occurred
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input mast0_drdy; // Indicated that either data is available
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input mast0_drdy; // Indicated that either data is available
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// during a read, or that the master can accept
|
// during a read, or that the master can accept
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// the next data during a write
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// the next data during a write
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output mast0_wait; // Tells the master to insert wait cycles
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output mast0_wait; // Tells the master to insert wait cycles
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// because data can not be accepted/provided
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// because data can not be accepted/provided
|
|
|
// --------------------------------------
|
// --------------------------------------
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// WISHBONE MASTER INTERFACE 1
|
// WISHBONE MASTER INTERFACE 1
|
|
|
output mast1_go; // Perform a Master Cycle
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output mast1_go; // Perform a Master Cycle
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output mast1_we; // Read/Write
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output mast1_we; // Read/Write
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output [31:0] mast1_adr; // Address for the transfer
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output [31:0] mast1_adr; // Address for the transfer
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input [31:0] mast1_din; // Internal Input Data
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input [31:0] mast1_din; // Internal Input Data
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output [31:0] mast1_dout; // Internal Output Data
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output [31:0] mast1_dout; // Internal Output Data
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input mast1_err; // Indicates an error has occurred
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input mast1_err; // Indicates an error has occurred
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input mast1_drdy; // Indicated that either data is available
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input mast1_drdy; // Indicated that either data is available
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// during a read, or that the master can accept
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// during a read, or that the master can accept
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// the next data during a write
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// the next data during a write
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output mast1_wait; // Tells the master to insert wait cycles
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output mast1_wait; // Tells the master to insert wait cycles
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// because data can not be accepted/provided
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// because data can not be accepted/provided
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|
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// --------------------------------------
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// --------------------------------------
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// DMA Engine Signals
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// DMA Engine Signals
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|
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// DMA Engine Init & Setup
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// DMA Engine Init & Setup
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input de_start; // Start DMA Engine Indicator
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input de_start; // Start DMA Engine Indicator
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input nd; // Next Descriptor Indicator
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input nd; // Next Descriptor Indicator
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input [31:0] csr; // Selected Channel CSR
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input [31:0] csr; // Selected Channel CSR
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input [31:0] pointer; // Linked List Descriptor pointer
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input [31:0] pointer; // Linked List Descriptor pointer
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input [31:0] pointer_s; // Previous Pointer
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input [31:0] pointer_s; // Previous Pointer
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input [31:0] txsz; // Selected Channel Transfer Size
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input [31:0] txsz; // Selected Channel Transfer Size
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input [31:0] adr0, adr1; // Selected Channel Addresses
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input [31:0] adr0, adr1; // Selected Channel Addresses
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input [31:0] am0, am1; // Selected Channel Address Masks
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input [31:0] am0, am1; // Selected Channel Address Masks
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|
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// DMA Engine Register File Update Outputs
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// DMA Engine Register File Update Outputs
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output de_csr_we; // Write enable for csr register
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output de_csr_we; // Write enable for csr register
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output de_txsz_we; // Write enable for txsz register
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output de_txsz_we; // Write enable for txsz register
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output de_adr0_we; // Write enable for adr0 register
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output de_adr0_we; // Write enable for adr0 register
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output de_adr1_we; // Write enable for adr1 register
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output de_adr1_we; // Write enable for adr1 register
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output ptr_set; // Set Pointer as Valid
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output ptr_set; // Set Pointer as Valid
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output [31:0] de_csr; // Write Data for CSR when loading External Desc.
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output [31:0] de_csr; // Write Data for CSR when loading External Desc.
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output [11:0] de_txsz; // Write back data for txsz register
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output [11:0] de_txsz; // Write back data for txsz register
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output [31:0] de_adr0; // Write back data for adr0 register
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output [31:0] de_adr0; // Write back data for adr0 register
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output [31:0] de_adr1; // Write back data for adr1 register
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output [31:0] de_adr1; // Write back data for adr1 register
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output de_fetch_descr; // Indicates that we are fetching a descriptor
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output de_fetch_descr; // Indicates that we are fetching a descriptor
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|
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// DMA Engine Control Outputs
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// DMA Engine Control Outputs
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output next_ch; // Indicates the DMA Engine is done
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output next_ch; // Indicates the DMA Engine is done
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output de_ack;
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output de_ack;
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|
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// DMA Abort from RF (software forced abort)
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// DMA Abort from RF (software forced abort)
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input dma_abort;
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input dma_abort;
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|
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// DMA Engine Status
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// DMA Engine Status
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input pause_req;
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input pause_req;
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output paused;
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output paused;
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output dma_busy, dma_err, dma_done, dma_done_all;
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output dma_busy, dma_err, dma_done, dma_done_all;
|
|
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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|
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parameter [10:0] // synopsys enum state
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parameter [10:0] // synopsys enum state
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IDLE = 11'b000_0000_0001,
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IDLE = 11'b000_0000_0001,
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READ = 11'b000_0000_0010,
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READ = 11'b000_0000_0010,
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WRITE = 11'b000_0000_0100,
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WRITE = 11'b000_0000_0100,
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UPDATE = 11'b000_0000_1000,
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UPDATE = 11'b000_0000_1000,
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LD_DESC1 = 11'b000_0001_0000,
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LD_DESC1 = 11'b000_0001_0000,
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LD_DESC2 = 11'b000_0010_0000,
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LD_DESC2 = 11'b000_0010_0000,
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LD_DESC3 = 11'b000_0100_0000,
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LD_DESC3 = 11'b000_0100_0000,
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LD_DESC4 = 11'b000_1000_0000,
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LD_DESC4 = 11'b000_1000_0000,
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LD_DESC5 = 11'b001_0000_0000,
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LD_DESC5 = 11'b001_0000_0000,
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WB = 11'b010_0000_0000,
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WB = 11'b010_0000_0000,
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PAUSE = 11'b100_0000_0000;
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PAUSE = 11'b100_0000_0000;
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|
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reg [10:0] /* synopsys enum state */ state, next_state;
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reg [10:0] /* synopsys enum state */ state, next_state;
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// synopsys state_vector state
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// synopsys state_vector state
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|
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reg [31:0] mast0_adr, mast1_adr;
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reg [31:0] mast0_adr, mast1_adr;
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|
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reg [29:0] adr0_cnt, adr1_cnt;
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reg [29:0] adr0_cnt, adr1_cnt;
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wire [29:0] adr0_cnt_next, adr1_cnt_next;
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wire [29:0] adr0_cnt_next, adr1_cnt_next;
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wire [29:0] adr0_cnt_next1, adr1_cnt_next1;
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wire [29:0] adr0_cnt_next1, adr1_cnt_next1;
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reg adr0_inc, adr1_inc;
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reg adr0_inc, adr1_inc;
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|
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reg [8:0] chunk_cnt;
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reg [8:0] chunk_cnt;
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reg chunk_dec;
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reg chunk_dec;
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|
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reg [11:0] tsz_cnt;
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reg [11:0] tsz_cnt;
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reg tsz_dec;
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reg tsz_dec;
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|
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reg de_txsz_we;
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reg de_txsz_we;
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reg de_csr_we;
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reg de_csr_we;
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reg de_adr0_we;
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reg de_adr0_we;
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reg de_adr1_we;
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reg de_adr1_we;
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reg ld_desc_sel;
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reg ld_desc_sel;
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|
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wire chunk_cnt_is_0_d;
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wire chunk_cnt_is_0_d;
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reg chunk_cnt_is_0_r;
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reg chunk_cnt_is_0_r;
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wire tsz_cnt_is_0_d;
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wire tsz_cnt_is_0_d;
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reg tsz_cnt_is_0_r;
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reg tsz_cnt_is_0_r;
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|
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reg read, write;
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reg read, write;
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reg read_r, write_r;
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reg read_r, write_r;
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wire rd_ack, wr_ack;
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wire rd_ack, wr_ack;
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reg rd_ack_r;
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reg rd_ack_r;
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|
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reg chunk_0;
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reg chunk_0;
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wire done;
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wire done;
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reg dma_done_d;
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reg dma_done_d;
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reg dma_done_r;
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reg dma_done_r;
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reg dma_abort_r;
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reg dma_abort_r;
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reg next_ch;
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reg next_ch;
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wire read_hold, write_hold;
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wire read_hold, write_hold;
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reg write_hold_r;
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reg write_hold_r;
|
|
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reg [1:0] ptr_adr_low;
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reg [1:0] ptr_adr_low;
|
reg m0_go;
|
reg m0_go;
|
reg m0_we;
|
reg m0_we;
|
reg ptr_set;
|
reg ptr_set;
|
|
|
// Aliases
|
// Aliases
|
wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable
|
wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable
|
wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable
|
wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable
|
wire ptr_valid = pointer[0];
|
wire ptr_valid = pointer[0];
|
wire use_ed = csr[`WDMA_USE_ED];
|
wire use_ed = csr[`WDMA_USE_ED];
|
|
|
reg mast0_drdy_r;
|
reg mast0_drdy_r;
|
reg paused;
|
reg paused;
|
|
|
reg de_fetch_descr; // Indicates that we are fetching a descriptor
|
reg de_fetch_descr; // Indicates that we are fetching a descriptor
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Misc Logic
|
// Misc Logic
|
//
|
//
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
dma_done_r <= #1 dma_done;
|
dma_done_r <= #1 dma_done;
|
|
|
// Address Counter 0 (Source Address)
|
// Address Counter 0 (Source Address)
|
always @(posedge clk)
|
always @(posedge clk)
|
if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2];
|
if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2];
|
else
|
else
|
if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next;
|
if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next;
|
|
|
// 30 Bit Incrementor (registered)
|
// 30 Bit Incrementor (registered)
|
wb_dma_inc30r u0( .clk( clk ),
|
wb_dma_inc30r u0( .clk( clk ),
|
.in( adr0_cnt ),
|
.in( adr0_cnt ),
|
.out( adr0_cnt_next1 ) );
|
.out( adr0_cnt_next1 ) );
|
|
|
assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0];
|
assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0];
|
assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2];
|
assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2];
|
assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3];
|
assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3];
|
assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4];
|
assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4];
|
assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5];
|
assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5];
|
assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6];
|
assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6];
|
assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7];
|
assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7];
|
assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8];
|
assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8];
|
assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9];
|
assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9];
|
assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10];
|
assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10];
|
assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11];
|
assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11];
|
assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12];
|
assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12];
|
assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13];
|
assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13];
|
assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14];
|
assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14];
|
assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15];
|
assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15];
|
assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16];
|
assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16];
|
assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17];
|
assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17];
|
assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18];
|
assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18];
|
assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19];
|
assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19];
|
assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20];
|
assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20];
|
assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21];
|
assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21];
|
assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22];
|
assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22];
|
assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23];
|
assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23];
|
assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24];
|
assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24];
|
assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25];
|
assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25];
|
assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26];
|
assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26];
|
assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27];
|
assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27];
|
assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28];
|
assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28];
|
assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29];
|
assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29];
|
|
|
|
|
// Address Counter 1 (Destination Address)
|
// Address Counter 1 (Destination Address)
|
always @(posedge clk)
|
always @(posedge clk)
|
if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2];
|
if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2];
|
else
|
else
|
if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next;
|
if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next;
|
|
|
// 30 Bit Incrementor (registered)
|
// 30 Bit Incrementor (registered)
|
wb_dma_inc30r u1( .clk( clk ),
|
wb_dma_inc30r u1( .clk( clk ),
|
.in( adr1_cnt ),
|
.in( adr1_cnt ),
|
.out( adr1_cnt_next1 ) );
|
.out( adr1_cnt_next1 ) );
|
|
|
assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0];
|
assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0];
|
assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2];
|
assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2];
|
assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3];
|
assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3];
|
assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4];
|
assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4];
|
assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5];
|
assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5];
|
assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6];
|
assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6];
|
assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7];
|
assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7];
|
assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8];
|
assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8];
|
assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9];
|
assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9];
|
assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10];
|
assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10];
|
assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11];
|
assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11];
|
assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12];
|
assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12];
|
assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13];
|
assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13];
|
assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14];
|
assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14];
|
assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15];
|
assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15];
|
assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16];
|
assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16];
|
assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17];
|
assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17];
|
assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18];
|
assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18];
|
assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19];
|
assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19];
|
assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20];
|
assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20];
|
assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21];
|
assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21];
|
assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22];
|
assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22];
|
assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23];
|
assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23];
|
assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24];
|
assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24];
|
assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25];
|
assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25];
|
assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26];
|
assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26];
|
assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27];
|
assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27];
|
assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28];
|
assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28];
|
assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29];
|
assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29];
|
|
|
// Chunk Counter
|
// Chunk Counter
|
always @(posedge clk)
|
always @(posedge clk)
|
if(de_start) chunk_cnt <= #1 txsz[24:16];
|
if(de_start) chunk_cnt <= #1 txsz[24:16];
|
else
|
else
|
if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1;
|
if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1;
|
|
|
assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0);
|
assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d;
|
chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d;
|
|
|
// Total Size Counter
|
// Total Size Counter
|
always @(posedge clk)
|
always @(posedge clk)
|
if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0];
|
if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0];
|
else
|
else
|
if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1;
|
if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1;
|
|
|
assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15];
|
assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15];
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d;
|
tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d;
|
|
|
// Counter Control Logic
|
// Counter Control Logic
|
always @(posedge clk)
|
always @(posedge clk)
|
chunk_dec <= #1 read & !read_r;
|
chunk_dec <= #1 read & !read_r;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
tsz_dec <= #1 read & !read_r;
|
tsz_dec <= #1 read & !read_r;
|
|
|
//always @(posedge clk)
|
//always @(posedge clk)
|
always @(rd_ack or read_r)
|
always @(rd_ack or read_r)
|
adr0_inc = rd_ack & read_r;
|
adr0_inc = rd_ack & read_r;
|
|
|
//always @(posedge clk)
|
//always @(posedge clk)
|
always @(wr_ack or write_r)
|
always @(wr_ack or write_r)
|
adr1_inc = wr_ack & write_r;
|
adr1_inc = wr_ack & write_r;
|
|
|
// Done logic
|
// Done logic
|
always @(posedge clk)
|
always @(posedge clk)
|
chunk_0 <= #1 (txsz[24:16] == 9'h0);
|
chunk_0 <= #1 (txsz[24:16] == 9'h0);
|
|
|
assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d);
|
assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d);
|
assign dma_done = dma_done_d & done;
|
assign dma_done = dma_done_d & done;
|
assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d));
|
assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d));
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
next_ch <= #1 dma_done;
|
next_ch <= #1 dma_done;
|
|
|
// Register Update Outputs
|
// Register Update Outputs
|
assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt;
|
assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt;
|
assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00};
|
assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00};
|
assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00};
|
assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00};
|
assign de_csr = mast0_din;
|
assign de_csr = mast0_din;
|
|
|
// Abort logic
|
// Abort logic
|
always @(posedge clk)
|
always @(posedge clk)
|
dma_abort_r <= #1 dma_abort | mast0_err | mast1_err;
|
dma_abort_r <= #1 dma_abort | mast0_err | mast1_err;
|
|
|
assign dma_err = dma_abort_r;
|
assign dma_err = dma_abort_r;
|
|
|
assign dma_busy = (state != IDLE);
|
assign dma_busy = (state != IDLE);
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// WISHBONE Interface Logic
|
// WISHBONE Interface Logic
|
//
|
//
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
read_r <= #1 read;
|
read_r <= #1 read;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
write_r <= #1 write;
|
write_r <= #1 write;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
rd_ack_r <= #1 read_r;
|
rd_ack_r <= #1 read_r;
|
|
|
// Data Path
|
// Data Path
|
assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din;
|
assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din;
|
assign mast1_dout = csr[2] ? mast1_din : mast0_din;
|
assign mast1_dout = csr[2] ? mast1_din : mast0_din;
|
|
|
// Address Path
|
// Address Path
|
always @(posedge clk)
|
always @(posedge clk)
|
mast0_adr <= #1 m0_go ?
|
mast0_adr <= #1 m0_go ?
|
(m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) :
|
(m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) :
|
read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
|
read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
|
mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
|
|
|
// CTRL
|
// CTRL
|
assign write_hold = (read | write) & write_hold_r;
|
assign write_hold = (read | write) & write_hold_r;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
write_hold_r <= #1 read | write;
|
write_hold_r <= #1 read | write;
|
|
|
assign read_hold = done ? read : (read | write);
|
assign read_hold = done ? read : (read | write);
|
|
|
assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go;
|
assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go;
|
assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold);
|
assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold);
|
|
|
assign mast0_we = m0_go ? m0_we : (!csr[1] & write);
|
assign mast0_we = m0_go ? m0_we : (!csr[1] & write);
|
assign mast1_we = csr[1] & write;
|
assign mast1_we = csr[1] & write;
|
|
|
assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy);
|
assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy);
|
assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy);
|
assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy);
|
|
|
assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go;
|
assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go;
|
assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write));
|
assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write));
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
mast0_drdy_r <= #1 mast0_drdy;
|
mast0_drdy_r <= #1 mast0_drdy;
|
|
|
assign de_ack = dma_done;
|
assign de_ack = dma_done;
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// State Machine
|
// State Machine
|
//
|
//
|
|
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) state <= #1 IDLE;
|
if(!rst) state <= #1 IDLE;
|
else state <= #1 next_state;
|
else state <= #1 next_state;
|
|
|
always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or
|
always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or
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done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd)
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done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd)
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begin
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begin
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next_state = state; // Default keep state
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next_state = state; // Default keep state
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read = 1'b0;
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read = 1'b0;
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write = 1'b0;
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write = 1'b0;
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dma_done_d = 1'b0;
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dma_done_d = 1'b0;
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de_csr_we = 1'b0;
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de_csr_we = 1'b0;
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de_txsz_we = 1'b0;
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de_txsz_we = 1'b0;
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de_adr0_we = 1'b0;
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de_adr0_we = 1'b0;
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de_adr1_we = 1'b0;
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de_adr1_we = 1'b0;
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de_fetch_descr = 1'b0;
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de_fetch_descr = 1'b0;
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m0_go = 1'b0;
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m0_go = 1'b0;
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m0_we = 1'b0;
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m0_we = 1'b0;
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ptr_adr_low = 2'h0;
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ptr_adr_low = 2'h0;
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ptr_set = 1'b0;
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ptr_set = 1'b0;
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ld_desc_sel = 1'b0;
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ld_desc_sel = 1'b0;
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paused = 1'b0;
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paused = 1'b0;
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case(state) // synopsys parallel_case full_case
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case(state) // synopsys parallel_case full_case
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IDLE:
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IDLE:
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begin
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begin
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if(pause_req) next_state = PAUSE;
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if(pause_req) next_state = PAUSE;
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else
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else
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if(de_start & !csr[`WDMA_ERR])
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if(de_start & !csr[`WDMA_ERR])
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begin
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begin
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if(use_ed & !ptr_valid) next_state = LD_DESC1;
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if(use_ed & !ptr_valid) next_state = LD_DESC1;
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else next_state = READ;
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else next_state = READ;
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end
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end
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end
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end
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PAUSE:
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PAUSE:
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begin
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begin
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paused = 1'b1;
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paused = 1'b1;
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if(!pause_req) next_state = IDLE;
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if(!pause_req) next_state = IDLE;
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end
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end
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READ: // Read From Source
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READ: // Read From Source
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begin
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begin
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if(dma_abort_r) next_state = UPDATE;
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if(dma_abort_r) next_state = UPDATE;
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else
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else
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if(!rd_ack) read = 1'b1;
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if(!rd_ack) read = 1'b1;
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else
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else
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begin
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begin
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write = 1'b1;
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write = 1'b1;
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next_state = WRITE;
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next_state = WRITE;
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end
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end
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end
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end
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WRITE: // Write To Destination
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WRITE: // Write To Destination
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begin
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begin
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if(dma_abort_r) next_state = UPDATE;
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if(dma_abort_r) next_state = UPDATE;
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else
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else
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if(!wr_ack) write = 1'b1;
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if(!wr_ack) write = 1'b1;
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else
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else
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begin
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begin
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if(done) next_state = UPDATE;
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if(done) next_state = UPDATE;
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else
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else
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begin
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begin
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read = 1'b1;
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read = 1'b1;
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next_state = READ;
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next_state = READ;
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end
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end
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end
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end
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end
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end
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UPDATE: // Update Registers
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UPDATE: // Update Registers
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begin
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begin
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dma_done_d = 1'b1;
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dma_done_d = 1'b1;
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de_txsz_we = 1'b1;
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de_txsz_we = 1'b1;
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de_adr0_we = 1'b1;
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de_adr0_we = 1'b1;
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de_adr1_we = 1'b1;
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de_adr1_we = 1'b1;
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if(use_ed & csr[`WDMA_WRB] & nd)
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if(use_ed & csr[`WDMA_WRB] & nd)
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begin
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begin
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m0_we = 1'b1;
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m0_we = 1'b1;
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m0_go = 1'b1;
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m0_go = 1'b1;
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next_state = WB;
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next_state = WB;
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end
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end
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else next_state = IDLE;
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else next_state = IDLE;
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end
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end
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WB:
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WB:
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begin
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begin
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m0_we = 1'b1;
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m0_we = 1'b1;
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if(mast0_drdy)
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if(mast0_drdy)
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begin
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begin
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next_state = IDLE;
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next_state = IDLE;
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end
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end
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else m0_go = 1'b1;
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else m0_go = 1'b1;
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end
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end
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LD_DESC1: // Load Descriptor from memory to registers
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LD_DESC1: // Load Descriptor from memory to registers
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begin
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begin
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ptr_adr_low = 2'h0;
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ptr_adr_low = 2'h0;
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ld_desc_sel = 1'b1;
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ld_desc_sel = 1'b1;
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m0_go = 1'b1;
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m0_go = 1'b1;
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de_csr_we = 1'b1;
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de_csr_we = 1'b1;
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de_txsz_we = 1'b1;
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de_txsz_we = 1'b1;
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de_fetch_descr = 1'b1;
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de_fetch_descr = 1'b1;
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if(mast0_drdy)
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if(mast0_drdy)
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begin
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begin
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ptr_adr_low = 2'h1;
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ptr_adr_low = 2'h1;
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next_state = LD_DESC2;
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next_state = LD_DESC2;
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end
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end
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end
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end
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LD_DESC2:
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LD_DESC2:
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begin
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begin
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de_fetch_descr = 1'b1;
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de_fetch_descr = 1'b1;
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if(mast0_drdy_r) de_csr_we = 1'b1;
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if(mast0_drdy_r) de_csr_we = 1'b1;
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if(mast0_drdy_r) de_txsz_we = 1'b1;
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if(mast0_drdy_r) de_txsz_we = 1'b1;
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ptr_adr_low = 2'h1;
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ptr_adr_low = 2'h1;
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ld_desc_sel = 1'b1;
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ld_desc_sel = 1'b1;
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m0_go = 1'b1;
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m0_go = 1'b1;
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if(mast0_drdy)
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if(mast0_drdy)
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begin
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begin
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ptr_adr_low = 2'h2;
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ptr_adr_low = 2'h2;
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next_state = LD_DESC3;
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next_state = LD_DESC3;
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end
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end
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end
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end
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LD_DESC3:
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LD_DESC3:
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begin
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begin
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de_fetch_descr = 1'b1;
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de_fetch_descr = 1'b1;
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if(mast0_drdy_r) de_adr0_we = 1'b1;
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if(mast0_drdy_r) de_adr0_we = 1'b1;
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ptr_adr_low = 2'h2;
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ptr_adr_low = 2'h2;
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ld_desc_sel = 1'b1;
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ld_desc_sel = 1'b1;
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m0_go = 1'b1;
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m0_go = 1'b1;
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if(mast0_drdy)
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if(mast0_drdy)
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begin
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begin
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ptr_adr_low = 2'h3;
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ptr_adr_low = 2'h3;
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next_state = LD_DESC4;
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next_state = LD_DESC4;
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end
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end
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end
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end
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LD_DESC4:
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LD_DESC4:
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begin
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begin
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de_fetch_descr = 1'b1;
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de_fetch_descr = 1'b1;
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if(mast0_drdy_r) de_adr1_we = 1'b1;
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if(mast0_drdy_r) de_adr1_we = 1'b1;
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ptr_adr_low = 2'h3;
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ptr_adr_low = 2'h3;
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ld_desc_sel = 1'b1;
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ld_desc_sel = 1'b1;
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if(mast0_drdy)
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if(mast0_drdy)
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begin
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begin
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next_state = LD_DESC5;
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next_state = LD_DESC5;
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end
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end
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else m0_go = 1'b1;
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else m0_go = 1'b1;
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end
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end
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LD_DESC5:
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LD_DESC5:
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begin
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begin
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de_fetch_descr = 1'b1;
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de_fetch_descr = 1'b1;
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ptr_set = 1'b1;
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ptr_set = 1'b1;
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next_state = READ;
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next_state = READ;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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