Subversion Repositories wb_dma

/////////////////////////////////////////////////////////////////////

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////                                                             ////

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////  WISHBONE DMA Register File                                 ////

////  WISHBONE DMA Register File                                 ////

////                                                             ////

////                                                             ////

////                                                             ////

////                                                             ////

////  Author: Rudolf Usselmann                                   ////

////  Author: Rudolf Usselmann                                   ////

////          rudi@asics.ws                                      ////

////          rudi@asics.ws                                      ////

////                                                             ////

////                                                             ////

////                                                             ////

////                                                             ////

////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////

////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

////                                                             ////

////                                                             ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

////                         www.asics.ws                        ////

////                         www.asics.ws                        ////

////                         rudi@asics.ws                       ////

////                         rudi@asics.ws                       ////

////                                                             ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: wb_dma_rf.v,v 1.4 2002-02-01 01:54:45 rudi Exp $

//  $Id: wb_dma_rf.v,v 1.4 2002-02-01 01:54:45 rudi Exp $

//

//

//  $Date: 2002-02-01 01:54:45 $

//  $Date: 2002-02-01 01:54:45 $

//  $Revision: 1.4 $

//  $Revision: 1.4 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.3  2001/10/19 04:35:04  rudi

//               Revision 1.3  2001/10/19 04:35:04  rudi

//

//

//               - Made the core parameterized

//               - Made the core parameterized

//

//

//               Revision 1.2  2001/08/15 05:40:30  rudi

//               Revision 1.2  2001/08/15 05:40:30  rudi

//

//

//               - Changed IO names to be more clear.

//               - Changed IO names to be more clear.

//               - Uniquifyed define names to be core specific.

//               - Uniquifyed define names to be core specific.

//               - Added Section 3.10, describing DMA restart.

//               - Added Section 3.10, describing DMA restart.

//

//

//               Revision 1.1  2001/07/29 08:57:02  rudi

//               Revision 1.1  2001/07/29 08:57:02  rudi

//

//

//

//

//               1) Changed Directory Structure

//               1) Changed Directory Structure

//               2) Added restart signal (REST)

//               2) Added restart signal (REST)

//

//

//               Revision 1.4  2001/06/14 08:50:46  rudi

//               Revision 1.4  2001/06/14 08:50:46  rudi

//

//

//               Changed name of channel register file module.

//               Changed name of channel register file module.

//

//

//               Revision 1.3  2001/06/13 02:26:48  rudi

//               Revision 1.3  2001/06/13 02:26:48  rudi

//

//

//

//

//               Small changes after running lint.

//               Small changes after running lint.

//

//

//               Revision 1.2  2001/06/05 10:22:37  rudi

//               Revision 1.2  2001/06/05 10:22:37  rudi

//

//

//

//

//               - Added Support of up to 31 channels

//               - Added Support of up to 31 channels

//               - Added support for 2,4 and 8 priority levels

//               - Added support for 2,4 and 8 priority levels

//               - Now can have up to 31 channels

//               - Now can have up to 31 channels

//               - Added many configuration items

//               - Added many configuration items

//               - Changed reset to async

//               - Changed reset to async

//

//

//               Revision 1.1.1.1  2001/03/19 13:10:11  rudi

//               Revision 1.1.1.1  2001/03/19 13:10:11  rudi

//               Initial Release

//               Initial Release

//

//

//

//

//

//

`include "wb_dma_defines.v"

`include "wb_dma_defines.v"

module wb_dma_rf(clk, rst,

module wb_dma_rf(clk, rst,

        // WISHBONE Access

        // WISHBONE Access

        wb_rf_adr, wb_rf_din, wb_rf_dout, wb_rf_re, wb_rf_we,

        wb_rf_adr, wb_rf_din, wb_rf_dout, wb_rf_re, wb_rf_we,

        // WISHBONE Interrupt outputs

        // WISHBONE Interrupt outputs

        inta_o, intb_o,

        inta_o, intb_o,

        // DMA Registers Outputs

        // DMA Registers Outputs

        pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1,

        pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1,

        pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1,

        pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1,

        pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1,

        pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1,

        pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1,

        pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1,

        pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1,

        pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1,

        pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1,

        pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1,

        pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1,

        pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1,

        pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1,

        pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1,

        pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1,

        pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1,

        pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1,

        pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1,

        pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1,

        pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1,

        pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1,

        pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1,

        pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1,

        pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1,

        pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1,

        pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1,

        pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1,

        pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1,

        pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1,

        pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1,

        pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1,

        pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1,

        pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1,

        pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1,

        pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1,

        pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1,

        pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1,

        pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1,

        pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1,

        pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1,

        pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1,

        pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1,

        pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1,

        pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1,

        pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1,

        pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1,

        pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1,

        pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1,

        pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1,

        pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1,

        pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1,

        pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1,

        pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1,

        pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1,

        pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1,

        pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1,

        pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1,

        pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1,

        pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1,

        pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1,

        // DMA Registers Write Back Channel Select

        // DMA Registers Write Back Channel Select

        ch_sel, ndnr,

        ch_sel, ndnr,

        // DMA Engine Status

        // DMA Engine Status

        pause_req, paused, dma_abort, dma_busy, dma_err, dma_done, dma_done_all,

        pause_req, paused, dma_abort, dma_busy, dma_err, dma_done, dma_done_all,

        // DMA Engine Reg File Update ctrl signals

        // DMA Engine Reg File Update ctrl signals

        de_csr, de_txsz, de_adr0, de_adr1,

        de_csr, de_txsz, de_adr0, de_adr1,

        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, de_fetch_descr, dma_rest,

        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, de_fetch_descr, dma_rest,

        ptr_set

        ptr_set

        );

        );

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Module Parameters

// Module Parameters

//

//

// chXX_conf = { CBUF, ED, ARS, EN }

// chXX_conf = { CBUF, ED, ARS, EN }

parameter       [3:0]    ch0_conf = 4'h1;

parameter       [3:0]    ch0_conf = 4'h1;

parameter       [3:0]    ch1_conf = 4'h0;

parameter       [3:0]    ch1_conf = 4'h0;

parameter       [3:0]    ch2_conf = 4'h0;

parameter       [3:0]    ch2_conf = 4'h0;

parameter       [3:0]    ch3_conf = 4'h0;

parameter       [3:0]    ch3_conf = 4'h0;

parameter       [3:0]    ch4_conf = 4'h0;

parameter       [3:0]    ch4_conf = 4'h0;

parameter       [3:0]    ch5_conf = 4'h0;

parameter       [3:0]    ch5_conf = 4'h0;

parameter       [3:0]    ch6_conf = 4'h0;

parameter       [3:0]    ch6_conf = 4'h0;

parameter       [3:0]    ch7_conf = 4'h0;

parameter       [3:0]    ch7_conf = 4'h0;

parameter       [3:0]    ch8_conf = 4'h0;

parameter       [3:0]    ch8_conf = 4'h0;

parameter       [3:0]    ch9_conf = 4'h0;

parameter       [3:0]    ch9_conf = 4'h0;

parameter       [3:0]    ch10_conf = 4'h0;

parameter       [3:0]    ch10_conf = 4'h0;

parameter       [3:0]    ch11_conf = 4'h0;

parameter       [3:0]    ch11_conf = 4'h0;

parameter       [3:0]    ch12_conf = 4'h0;

parameter       [3:0]    ch12_conf = 4'h0;

parameter       [3:0]    ch13_conf = 4'h0;

parameter       [3:0]    ch13_conf = 4'h0;

parameter       [3:0]    ch14_conf = 4'h0;

parameter       [3:0]    ch14_conf = 4'h0;

parameter       [3:0]    ch15_conf = 4'h0;

parameter       [3:0]    ch15_conf = 4'h0;

parameter       [3:0]    ch16_conf = 4'h0;

parameter       [3:0]    ch16_conf = 4'h0;

parameter       [3:0]    ch17_conf = 4'h0;

parameter       [3:0]    ch17_conf = 4'h0;

parameter       [3:0]    ch18_conf = 4'h0;

parameter       [3:0]    ch18_conf = 4'h0;

parameter       [3:0]    ch19_conf = 4'h0;

parameter       [3:0]    ch19_conf = 4'h0;

parameter       [3:0]    ch20_conf = 4'h0;

parameter       [3:0]    ch20_conf = 4'h0;

parameter       [3:0]    ch21_conf = 4'h0;

parameter       [3:0]    ch21_conf = 4'h0;

parameter       [3:0]    ch22_conf = 4'h0;

parameter       [3:0]    ch22_conf = 4'h0;

parameter       [3:0]    ch23_conf = 4'h0;

parameter       [3:0]    ch23_conf = 4'h0;

parameter       [3:0]    ch24_conf = 4'h0;

parameter       [3:0]    ch24_conf = 4'h0;

parameter       [3:0]    ch25_conf = 4'h0;

parameter       [3:0]    ch25_conf = 4'h0;

parameter       [3:0]    ch26_conf = 4'h0;

parameter       [3:0]    ch26_conf = 4'h0;

parameter       [3:0]    ch27_conf = 4'h0;

parameter       [3:0]    ch27_conf = 4'h0;

parameter       [3:0]    ch28_conf = 4'h0;

parameter       [3:0]    ch28_conf = 4'h0;

parameter       [3:0]    ch29_conf = 4'h0;

parameter       [3:0]    ch29_conf = 4'h0;

parameter       [3:0]    ch30_conf = 4'h0;

parameter       [3:0]    ch30_conf = 4'h0;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Module IOs

// Module IOs

//

//

input           clk, rst;

input           clk, rst;

// WISHBONE Access

// WISHBONE Access

input   [7:0]    wb_rf_adr;

input   [7:0]    wb_rf_adr;

input   [31:0]   wb_rf_din;

input   [31:0]   wb_rf_din;

output  [31:0]   wb_rf_dout;

output  [31:0]   wb_rf_dout;

input           wb_rf_re;

input           wb_rf_re;

input           wb_rf_we;

input           wb_rf_we;

// WISHBONE Interrupt outputs

// WISHBONE Interrupt outputs

output          inta_o, intb_o;

output          inta_o, intb_o;

// Channel Registers Inputs

// Channel Registers Inputs

output  [31:0]   pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;

output  [31:0]   pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;

output  [31:0]   pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;

output  [31:0]   pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;

output  [31:0]   pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;

output  [31:0]   pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;

output  [31:0]   pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;

output  [31:0]   pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;

output  [31:0]   pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;

output  [31:0]   pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;

output  [31:0]   pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;

output  [31:0]   pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;

output  [31:0]   pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;

output  [31:0]   pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;

output  [31:0]   pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;

output  [31:0]   pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;

output  [31:0]   pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;

output  [31:0]   pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;

output  [31:0]   pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;

output  [31:0]   pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;

output  [31:0]   pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;

output  [31:0]   pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;

output  [31:0]   pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;

output  [31:0]   pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;

output  [31:0]   pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;

output  [31:0]   pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;

output  [31:0]   pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;

output  [31:0]   pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;

output  [31:0]   pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;

output  [31:0]   pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;

output  [31:0]   pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;

output  [31:0]   pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;

output  [31:0]   pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;

output  [31:0]   pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;

output  [31:0]   pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;

output  [31:0]   pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;

output  [31:0]   pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;

output  [31:0]   pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;

output  [31:0]   pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;

output  [31:0]   pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;

output  [31:0]   pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;

output  [31:0]   pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;

output  [31:0]   pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;

output  [31:0]   pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;

output  [31:0]   pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;

output  [31:0]   pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;

output  [31:0]   pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;

output  [31:0]   pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;

output  [31:0]   pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;

output  [31:0]   pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;

output  [31:0]   pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;

output  [31:0]   pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;

output  [31:0]   pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;

output  [31:0]   pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;

output  [31:0]   pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;

output  [31:0]   pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;

output  [31:0]   pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;

output  [31:0]   pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;

output  [31:0]   pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;

output  [31:0]   pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;

output  [31:0]   pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;

output  [31:0]   pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;

input   [4:0]    ch_sel;         // Write Back Channel Select

input   [4:0]    ch_sel;         // Write Back Channel Select

input   [30:0]   ndnr;           // Next Descriptor No Request

input   [30:0]   ndnr;           // Next Descriptor No Request

// DMA Engine Abort

// DMA Engine Abort

output          dma_abort;

output          dma_abort;

// DMA Engine Status

// DMA Engine Status

output          pause_req;

output          pause_req;

input           paused;

input           paused;

input           dma_busy, dma_err, dma_done, dma_done_all;

input           dma_busy, dma_err, dma_done, dma_done_all;

// DMA Engine Reg File Update ctrl signals

// DMA Engine Reg File Update ctrl signals

input   [31:0]   de_csr;

input   [31:0]   de_csr;

input   [11:0]   de_txsz;

input   [11:0]   de_txsz;

input   [31:0]   de_adr0;

input   [31:0]   de_adr0;

input   [31:0]   de_adr1;

input   [31:0]   de_adr1;

input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;

input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;

input           de_fetch_descr;

input           de_fetch_descr;

input   [30:0]   dma_rest;

input   [30:0]   dma_rest;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Local Wires and Registers

// Local Wires and Registers

//

//

reg     [31:0]   wb_rf_dout;

reg     [31:0]   wb_rf_dout;

reg             inta_o, intb_o;

reg             inta_o, intb_o;

reg     [30:0]   int_maska_r, int_maskb_r;

reg     [30:0]   int_maska_r, int_maskb_r;

wire    [31:0]   int_maska, int_maskb;

wire    [31:0]   int_maska, int_maskb;

wire    [31:0]   int_srca, int_srcb;

wire    [31:0]   int_srca, int_srcb;

wire            int_maska_we, int_maskb_we;

wire            int_maska_we, int_maskb_we;

wire    [30:0]   ch_int;

wire    [30:0]   ch_int;

wire            csr_we;

wire            csr_we;

wire    [31:0]   csr;

wire    [31:0]   csr;

reg     [7:0]    csr_r;

reg     [7:0]    csr_r;

wire    [30:0]   ch_stop;

wire    [30:0]   ch_stop;

wire    [30:0]   ch_dis;

wire    [30:0]   ch_dis;

wire    [31:0]   ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;

wire    [31:0]   ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;

wire    [31:0]   ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;

wire    [31:0]   ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;

wire    [31:0]   ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;

wire    [31:0]   ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;

wire    [31:0]   ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;

wire    [31:0]   ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;

wire    [31:0]   ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;

wire    [31:0]   ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;

wire    [31:0]   ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;

wire    [31:0]   ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;

wire    [31:0]   ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;

wire    [31:0]   ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;

wire    [31:0]   ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;

wire    [31:0]   ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;

wire    [31:0]   ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;

wire    [31:0]   ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;

wire    [31:0]   ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;

wire    [31:0]   ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;

wire    [31:0]   ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;

wire    [31:0]   ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;

wire    [31:0]   ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;

wire    [31:0]   ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;

wire    [31:0]   ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;

wire    [31:0]   ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;

wire    [31:0]   ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;

wire    [31:0]   ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;

wire    [31:0]   ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;

wire    [31:0]   ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;

wire    [31:0]   ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;

wire    [31:0]   ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;

wire    [31:0]   ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;

wire    [31:0]   ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;

wire    [31:0]   ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;

wire    [31:0]   ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;

wire    [31:0]   ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;

wire    [31:0]   ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;

wire    [31:0]   ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;

wire    [31:0]   ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;

wire    [31:0]   ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;

wire    [31:0]   ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;

wire    [31:0]   ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;

wire    [31:0]   ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;

wire    [31:0]   ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;

wire    [31:0]   ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;

wire    [31:0]   ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;

wire    [31:0]   ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;

wire    [31:0]   ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;

wire    [31:0]   ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;

wire    [31:0]   ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;

wire    [31:0]   ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;

wire    [31:0]   ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;

wire    [31:0]   ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;

wire    [31:0]   ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;

wire    [31:0]   ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;

wire    [31:0]   ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;

wire    [31:0]   ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;

wire    [31:0]   ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;

wire    [31:0]   ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;

wire    [31:0]   ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;

wire    [31:0]   ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;

wire    [31:0]   sw_pointer0, sw_pointer1, sw_pointer2, sw_pointer3;

wire    [31:0]   sw_pointer0, sw_pointer1, sw_pointer2, sw_pointer3;

wire    [31:0]   sw_pointer4, sw_pointer5, sw_pointer6, sw_pointer7;

wire    [31:0]   sw_pointer4, sw_pointer5, sw_pointer6, sw_pointer7;

wire    [31:0]   sw_pointer8, sw_pointer9, sw_pointer10, sw_pointer11;

wire    [31:0]   sw_pointer8, sw_pointer9, sw_pointer10, sw_pointer11;

wire    [31:0]   sw_pointer12, sw_pointer13, sw_pointer14, sw_pointer15;

wire    [31:0]   sw_pointer12, sw_pointer13, sw_pointer14, sw_pointer15;

wire    [31:0]   sw_pointer16, sw_pointer17, sw_pointer18, sw_pointer19;

wire    [31:0]   sw_pointer16, sw_pointer17, sw_pointer18, sw_pointer19;

wire    [31:0]   sw_pointer20, sw_pointer21, sw_pointer22, sw_pointer23;

wire    [31:0]   sw_pointer20, sw_pointer21, sw_pointer22, sw_pointer23;

wire    [31:0]   sw_pointer24, sw_pointer25, sw_pointer26, sw_pointer27;

wire    [31:0]   sw_pointer24, sw_pointer25, sw_pointer26, sw_pointer27;

wire    [31:0]   sw_pointer28, sw_pointer29, sw_pointer30;

wire    [31:0]   sw_pointer28, sw_pointer29, sw_pointer30;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Aliases

// Aliases

//

//

assign int_maska = {1'h0, int_maska_r};

assign int_maska = {1'h0, int_maska_r};

assign int_maskb = {1'h0, int_maskb_r};

assign int_maskb = {1'h0, int_maskb_r};

assign csr = {31'h0, paused};

assign csr = {31'h0, paused};

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Misc Logic

// Misc Logic

//

//

assign dma_abort = |ch_stop;

assign dma_abort = |ch_stop;

assign pause_req = csr_r[0];

assign pause_req = csr_r[0];

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// WISHBONE Register Read Logic

// WISHBONE Register Read Logic

//

//

always @(posedge clk)

always @(posedge clk)

        case(wb_rf_adr)         // synopsys parallel_case full_case

        case(wb_rf_adr)         // synopsys parallel_case full_case

           8'h0:        wb_rf_dout <= #1 csr;

           8'h0:        wb_rf_dout <= #1 csr;

           8'h1:        wb_rf_dout <= #1 int_maska;

           8'h1:        wb_rf_dout <= #1 int_maska;

           8'h2:        wb_rf_dout <= #1 int_maskb;

           8'h2:        wb_rf_dout <= #1 int_maskb;

           8'h3:        wb_rf_dout <= #1 int_srca;

           8'h3:        wb_rf_dout <= #1 int_srca;

           8'h4:        wb_rf_dout <= #1 int_srcb;

           8'h4:        wb_rf_dout <= #1 int_srcb;

           8'h8:        wb_rf_dout <= #1 ch0_csr;

           8'h8:        wb_rf_dout <= #1 ch0_csr;

           8'h9:        wb_rf_dout <= #1 ch0_txsz;

           8'h9:        wb_rf_dout <= #1 ch0_txsz;

           8'ha:        wb_rf_dout <= #1 ch0_adr0;

           8'ha:        wb_rf_dout <= #1 ch0_adr0;

           8'hb:        wb_rf_dout <= #1 ch0_am0;

           8'hb:        wb_rf_dout <= #1 ch0_am0;

           8'hc:        wb_rf_dout <= #1 ch0_adr1;

           8'hc:        wb_rf_dout <= #1 ch0_adr1;

           8'hd:        wb_rf_dout <= #1 ch0_am1;

           8'hd:        wb_rf_dout <= #1 ch0_am1;

           8'he:        wb_rf_dout <= #1 pointer0;

           8'he:        wb_rf_dout <= #1 pointer0;

           8'hf:        wb_rf_dout <= #1 sw_pointer0;

           8'hf:        wb_rf_dout <= #1 sw_pointer0;

           8'h10:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr    : 32'h0;

           8'h10:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr    : 32'h0;

           8'h11:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz   : 32'h0;

           8'h11:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz   : 32'h0;

           8'h12:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0   : 32'h0;

           8'h12:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0   : 32'h0;

           8'h13:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0    : 32'h0;

           8'h13:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0    : 32'h0;

           8'h14:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1   : 32'h0;

           8'h14:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1   : 32'h0;

           8'h15:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1    : 32'h0;

           8'h15:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1    : 32'h0;

           8'h16:       wb_rf_dout <= #1 ch1_conf[0] ? pointer1   : 32'h0;

           8'h16:       wb_rf_dout <= #1 ch1_conf[0] ? pointer1   : 32'h0;

           8'h17:       wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1   : 32'h0;

           8'h17:       wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1   : 32'h0;