/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE DMA WISHBONE Master Interface ////
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//// WISHBONE DMA WISHBONE Master Interface ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $
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// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $
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//
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//
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// $Date: 2002-02-01 01:54:45 $
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// $Date: 2002-02-01 01:54:45 $
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// $Revision: 1.2 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 08:57:02 rudi
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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// 2) Added restart signal (REST)
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//
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//
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// Revision 1.2 2001/06/05 10:22:37 rudi
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// Revision 1.2 2001/06/05 10:22:37 rudi
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//
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//
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//
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//
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// - Added Support of up to 31 channels
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// - Added Support of up to 31 channels
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// - Added support for 2,4 and 8 priority levels
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// - Added support for 2,4 and 8 priority levels
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// - Now can have up to 31 channels
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// - Now can have up to 31 channels
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// - Added many configuration items
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// - Added many configuration items
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// - Changed reset to async
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// - Changed reset to async
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//
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//
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// Revision 1.1.1.1 2001/03/19 13:11:05 rudi
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// Revision 1.1.1.1 2001/03/19 13:11:05 rudi
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// Initial Release
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// Initial Release
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//
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//
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//
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//
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//
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//
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`include "wb_dma_defines.v"
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`include "wb_dma_defines.v"
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module wb_dma_wb_mast(clk, rst,
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module wb_dma_wb_mast(clk, rst,
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wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
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wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
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wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
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wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
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mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
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mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
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mast_drdy, mast_wait,
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mast_drdy, mast_wait,
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pt_sel, mast_pt_in, mast_pt_out
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pt_sel, mast_pt_in, mast_pt_out
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);
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);
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input clk, rst;
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input clk, rst;
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// --------------------------------------
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// --------------------------------------
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// WISHBONE INTERFACE
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// WISHBONE INTERFACE
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input [31:0] wb_data_i;
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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output [31:0] wb_data_o;
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output [31:0] wb_addr_o;
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output [31:0] wb_addr_o;
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output [3:0] wb_sel_o;
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output [3:0] wb_sel_o;
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output wb_we_o;
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output wb_we_o;
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output wb_cyc_o;
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output wb_cyc_o;
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output wb_stb_o;
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output wb_stb_o;
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input wb_ack_i;
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input wb_ack_i;
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input wb_err_i;
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input wb_err_i;
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input wb_rty_i;
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input wb_rty_i;
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// --------------------------------------
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// --------------------------------------
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// INTERNAL DMA INTERFACE
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// INTERNAL DMA INTERFACE
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input mast_go; // Perform a Master Cycle (as long as this
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input mast_go; // Perform a Master Cycle (as long as this
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// line is asserted)
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// line is asserted)
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input mast_we; // Read/Write
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input mast_we; // Read/Write
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input [31:0] mast_adr; // Address for the transfer
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input [31:0] mast_adr; // Address for the transfer
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input [31:0] mast_din; // Internal Input Data
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input [31:0] mast_din; // Internal Input Data
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output [31:0] mast_dout; // Internal Output Data
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output [31:0] mast_dout; // Internal Output Data
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output mast_err; // Indicates an error has occurred
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output mast_err; // Indicates an error has occurred
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output mast_drdy; // Indicated that either data is available
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output mast_drdy; // Indicated that either data is available
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// during a read, or that the master can accept
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// during a read, or that the master can accept
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// the next data during a write
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// the next data during a write
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input mast_wait; // Tells the master to insert wait cycles
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input mast_wait; // Tells the master to insert wait cycles
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// because data can not be accepted/provided
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// because data can not be accepted/provided
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// Pass Through Interface
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// Pass Through Interface
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input pt_sel; // Pass Through Mode Selected
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input pt_sel; // Pass Through Mode Selected
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input [70:0] mast_pt_in; // Grouped WISHBONE inputs
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input [70:0] mast_pt_in; // Grouped WISHBONE inputs
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output [34:0] mast_pt_out; // Grouped WISHBONE outputs
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output [34:0] mast_pt_out; // Grouped WISHBONE outputs
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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reg mast_cyc, mast_stb;
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reg mast_cyc, mast_stb;
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reg mast_we_r;
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reg mast_we_r;
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reg [3:0] mast_be;
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reg [3:0] mast_be;
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reg [31:0] mast_dout;
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reg [31:0] mast_dout;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Pass-Through Interface
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// Pass-Through Interface
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//
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//
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assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} =
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assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} =
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pt_sel ? mast_pt_in :
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pt_sel ? mast_pt_in :
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{mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb};
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{mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb};
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assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i};
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assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i};
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// DMA Engine Interface
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// DMA Engine Interface
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if(wb_ack_i) mast_dout <= #1 wb_data_i;
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if(wb_ack_i) mast_dout <= #1 wb_data_i;
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always @(posedge clk)
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always @(posedge clk)
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mast_be <= #1 4'hf;
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mast_be <= #1 4'hf;
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always @(posedge clk)
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always @(posedge clk)
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mast_we_r <= #1 mast_we;
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mast_we_r <= #1 mast_we;
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always @(posedge clk)
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always @(posedge clk)
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mast_cyc <= #1 mast_go;
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mast_cyc <= #1 mast_go;
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always @(posedge clk)
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always @(posedge clk)
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mast_stb <= #1 mast_go & !mast_wait;
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mast_stb <= #1 mast_go & !mast_wait;
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assign mast_drdy = wb_ack_i;
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assign mast_drdy = wb_ack_i;
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assign mast_err = wb_err_i;
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assign mast_err = wb_err_i;
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endmodule
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endmodule
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