|
|
all: sim
|
all: sim
|
SHELL = /bin/sh
|
SHELL = /bin/sh
|
MS=-s
|
MS=-s
|
|
|
##########################################################################
|
##########################################################################
|
#
|
#
|
# DUT Sources
|
# DUT Sources
|
#
|
#
|
##########################################################################
|
##########################################################################
|
DUT_SRC_DIR=../../../rtl/verilog
|
DUT_SRC_DIR=../../../rtl/verilog
|
_TARGETS_= $(DUT_SRC_DIR)/wb_dma_ch_pri_enc.v \
|
_TARGETS_= $(DUT_SRC_DIR)/wb_dma_ch_pri_enc.v \
|
$(DUT_SRC_DIR)/wb_dma_ch_arb.v \
|
$(DUT_SRC_DIR)/wb_dma_ch_arb.v \
|
$(DUT_SRC_DIR)/wb_dma_pri_enc_sub.v \
|
$(DUT_SRC_DIR)/wb_dma_pri_enc_sub.v \
|
$(DUT_SRC_DIR)/wb_dma_ch_sel.v \
|
$(DUT_SRC_DIR)/wb_dma_ch_sel.v \
|
$(DUT_SRC_DIR)/wb_dma_top.v \
|
$(DUT_SRC_DIR)/wb_dma_top.v \
|
$(DUT_SRC_DIR)/wb_dma_ch_rf.v \
|
$(DUT_SRC_DIR)/wb_dma_ch_rf.v \
|
$(DUT_SRC_DIR)/wb_dma_rf.v \
|
$(DUT_SRC_DIR)/wb_dma_rf.v \
|
$(DUT_SRC_DIR)/wb_dma_wb_if.v \
|
$(DUT_SRC_DIR)/wb_dma_wb_if.v \
|
$(DUT_SRC_DIR)/wb_dma_wb_mast.v \
|
$(DUT_SRC_DIR)/wb_dma_wb_mast.v \
|
$(DUT_SRC_DIR)/wb_dma_wb_slv.v \
|
$(DUT_SRC_DIR)/wb_dma_wb_slv.v \
|
$(DUT_SRC_DIR)/wb_dma_de.v \
|
$(DUT_SRC_DIR)/wb_dma_de.v \
|
$(DUT_SRC_DIR)/wb_dma_inc30r.v
|
$(DUT_SRC_DIR)/wb_dma_inc30r.v
|
|
|
##########################################################################
|
##########################################################################
|
#
|
#
|
# Test Bench Sources
|
# Test Bench Sources
|
#
|
#
|
##########################################################################
|
##########################################################################
|
_TOP_=test
|
_TOP_=test
|
TB_SRC_DIR=../../../bench/verilog
|
TB_SRC_DIR=../../../bench/verilog
|
_TB_= $(TB_SRC_DIR)/test_bench_top.v \
|
_TB_= $(TB_SRC_DIR)/test_bench_top.v \
|
$(TB_SRC_DIR)/wb_slv_model.v \
|
$(TB_SRC_DIR)/wb_slv_model.v \
|
$(TB_SRC_DIR)/wb_mast_model.v
|
$(TB_SRC_DIR)/wb_mast_model.v
|
|
|
##########################################################################
|
##########################################################################
|
#
|
#
|
# Misc Variables
|
# Misc Variables
|
#
|
#
|
##########################################################################
|
##########################################################################
|
|
|
#INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
|
#INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
|
#LOGF=-LOGFILE .nclog
|
#LOGF=-LOGFILE .nclog
|
#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
|
#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
|
|
|
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
|
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
|
LOGF=-l .nclog
|
LOGF=-l .nclog
|
|
|
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
|
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
|
GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v
|
GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v
|
|
|
##########################################################################
|
##########################################################################
|
#
|
#
|
# Make Targets
|
# Make Targets
|
#
|
#
|
##########################################################################
|
##########################################################################
|
|
|
ss:
|
ss:
|
signalscan -do waves/waves.do -waves waves/waves.trn &
|
signalscan -do waves/waves.do -waves waves/waves.trn &
|
|
|
simxl:
|
simxl:
|
verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
|
verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
|
$(_TARGETS_) $(_TB_)
|
$(_TARGETS_) $(_TB_)
|
|
|
simw:
|
simw:
|
@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
|
@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
|
|
|
sim:
|
sim:
|
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
|
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
|
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
|
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
|
+ncuid+`hostname`
|
+ncuid+`hostname`
|
|
|
gatew:
|
gatew:
|
@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
|
@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
|
|
|
gate:
|
gate:
|
ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
|
ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
|
$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
|
$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
|
$(LOGF) +ncstatus +ncuid+`hostname`
|
$(LOGF) +ncstatus +ncuid+`hostname`
|
|
|
hal:
|
hal:
|
@echo ""
|
@echo ""
|
@echo "----- Running HAL ... ----------"
|
@echo "----- Running HAL ... ----------"
|
@hal -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
|
@hal -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
|
+incdir+$(DUT_SRC_DIR) $(_TARGETS_)
|
+incdir+$(DUT_SRC_DIR) $(_TARGETS_)
|
@echo "----- DONE ... ----------"
|
@echo "----- DONE ... ----------"
|
|
|
clean:
|
clean:
|
rm -rf ./waves/*.dsn ./waves/*.trn \
|
rm -rf ./waves/*.dsn ./waves/*.trn \
|
ncwork/inc* ncwork/.inc* ncverilog.key \
|
ncwork/inc* ncwork/.inc* ncverilog.key \
|
./verilog.* .nclog hal.log INCA_libs
|
./verilog.* .nclog hal.log INCA_libs
|
|
|
##########################################################################
|
##########################################################################
|
|
|
