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https://opencores.org/ocsvn/wb_dma/wb_dma/trunk
[/] [wb_dma/] [trunk/] [syn/] [bin/] [design_spec.dc] - Diff between revs 6 and 17
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Rev 17 |
#################################################################################
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#################################################################################
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#
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#
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# Design Specification
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# Design Specification
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#
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#
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# Author: Rudolf Usselmann
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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# rudi@asics.ws
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#
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#
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# Revision:
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# Revision:
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# 3/7/01 RU Initial Sript
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# 3/7/01 RU Initial Sript
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#
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#
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#
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#
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#################################################################################
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#################################################################################
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# ==============================================
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# ==============================================
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# Setup Design Parameters
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# Setup Design Parameters
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set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top }
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set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top }
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set design_name wb_dma_top
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set design_name wb_dma_top
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set active_design wb_dma_top
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set active_design wb_dma_top
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# Next Statement defines all clocks and resets in the design
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# Next Statement defines all clocks and resets in the design
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set special_net {rst clk}
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set special_net {rst clk}
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set hdl_src_dir ../../rtl/verilog/
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set hdl_src_dir ../../rtl/verilog/
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