/*
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/*
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This file is part of the Memories project:
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This file is part of the Memories project:
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http://www.opencores.org/project,wb_fifo
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http://www.opencores.org/project,wb_fifo
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Description
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Description
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Implementation of FIFO transactor data structures and high-level API.
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Implementation of FIFO transactor data structures and high-level API.
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To Do:
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To Do:
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Author(s):
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
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/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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--use std.textio.all;
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--use std.textio.all;
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library tauhop; --use tauhop.transactor.all;
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library tauhop; --use tauhop.transactor.all;
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/* Record I/O data structures for AXI interface transactor (block interface). */
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package fifoTLM is
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package fifoTLM is
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generic(
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generic(
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package i_transactor is new tauhop.tlm generic map(<>)
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package i_transactor is new tauhop.tlm generic map(<>)
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);
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);
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/* Makes i_transactor.t_addr, i_transactor.t_msg, and i_transactor.t_cnt visible. */
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/* Makes i_transactor.t_addr, i_transactor.t_msg, and i_transactor.t_cnt visible. */
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use i_transactor.all;
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use i_transactor.all;
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/* FIFO Transactor block interface. */
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/* FIFO Transactor block interface. */
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type t_fifoTransactor is record
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type t_fifoTransactor is record
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writeRequest,readRequest:t_bfm;
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writeRequest,readRequest:t_bfm;
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writeResponse,readResponse:t_bfm;
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writeResponse,readResponse:t_bfm;
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end record t_fifoTransactor;
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end record t_fifoTransactor;
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/* Use separate record for FIFO signalling.
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/* Use separate record for FIFO signalling.
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This will make it easier when we need to split up the request and response
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This will make it easier when we need to split up the request and response
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structures into separate records (for different directions).
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structures into separate records (for different directions).
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*/
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*/
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type t_fifo is record
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type t_fifo is record
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pctFilled:unsigned(7 downto 0);
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pctFilled:unsigned(7 downto 0);
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nearFull,full:boolean;
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nearFull,full:boolean;
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nearEmpty,empty:boolean;
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nearEmpty,empty:boolean;
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overflow,underflow:boolean;
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overflow,underflow:boolean;
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end record t_fifo;
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end record t_fifo;
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end package fifoTLM;
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end package fifoTLM;
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package body fifoTLM is
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package body fifoTLM is
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end package body fifoTLM;
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end package body fifoTLM;
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/* FIFO Transactor API.
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/* FIFO Transactor API.
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* Generally, transactors are high-level bus interface models that perform
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* Generally, transactors are high-level bus interface models that perform
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* read/write transactions to/from the bus. These models are not concerned
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* read/write transactions to/from the bus. These models are not concerned
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* with the low-level implementation of the bus protocol. However, the
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* with the low-level implementation of the bus protocol. However, the
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* TLM models encapsulate the lower-level models known as the BFM.
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* TLM models encapsulate the lower-level models known as the BFM.
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* fifoTLM uses generic package tauhop.tlm, hence inherits basic TLM types and
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* fifoTLM uses generic package tauhop.tlm, hence inherits basic TLM types and
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* procedures generally used in any messaging system (i.e. address and message
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* procedures generally used in any messaging system (i.e. address and message
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* information, and bus read/write methods). It also extends the tauhop.tlm
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* information, and bus read/write methods). It also extends the tauhop.tlm
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* package with application-specific types, such as record structures specific
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* package with application-specific types, such as record structures specific
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* to the AXI protocol.
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* to the AXI protocol.
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* fifoTransactor instantiates the fifoTLM, and assigns specific types to the
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* fifoTransactor instantiates the fifoTLM, and assigns specific types to the
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* transactor model.
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* transactor model.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop;
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library tauhop;
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package transactor is new tauhop.tlm generic map(
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package transactor is new tauhop.tlm generic map(
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t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces.
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t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces.
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t_msg=>unsigned(63 downto 0),
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t_msg=>unsigned(63 downto 0),
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t_cnt=>unsigned(127 downto 0)
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t_cnt=>unsigned(127 downto 0)
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);
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);
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop; use tauhop.transactor.all;
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library tauhop; use tauhop.transactor.all;
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package fifoTransactor is new tauhop.fifoTLM generic map(
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package fifoTransactor is new tauhop.fifoTLM generic map(
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--t_data=>unsigned(31 downto 0),
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--t_data=>unsigned(31 downto 0),
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i_transactor=>tauhop.transactor
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i_transactor=>tauhop.transactor
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);
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);
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