//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: top_pci_lpc_host.v,v 1.1 2008-03-05 05:58:41 hharte Exp $ ////
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//// $Id: top_pci_lpc_host.v,v 1.2 2008-03-05 16:14:32 hharte Exp $ ////
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//// top_pci_lpc_host.v - Top Level for PCI to LPC Host ////
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//// top_pci_lpc_host.v - Top Level for PCI to LPC Host ////
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//// for the Enterpoint Raggedstone1 PCI Card. Based on the ////
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//// for the Enterpoint Raggedstone1 PCI Card. Based on the ////
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//// OpenCores raggedstone project, and uses the OpenCores ////
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//// OpenCores raggedstone project, and uses the OpenCores ////
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//// pci32tlite core. ////
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//// pci32tlite core. ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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//// Author: ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module pci_lpc_host
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module pci_lpc_host
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(
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(
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CLK,
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CLK,
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RST, // Active Low
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RST, // Active Low
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INTA,
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INTA,
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REQ,
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REQ,
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GNT,
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GNT,
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FRAME,
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FRAME,
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IRDY,
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IRDY,
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IDSEL,
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IDSEL,
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DEVSEL,
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DEVSEL,
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TRDY,
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TRDY,
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STOP,
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STOP,
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PAR,
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PAR,
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PERR,
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PERR,
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SERR,
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SERR,
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PCI_AD,
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PCI_AD,
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CBE0,
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CBE0,
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CBE1,
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CBE1,
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CBE2,
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CBE2,
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CBE3,
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CBE3,
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DISP_SEL,
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DISP_SEL,
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DISP_LED,
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DISP_LED,
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LPC_CLK,
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LPC_CLK,
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LFRAME,
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LFRAME,
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LAD,
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LAD,
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LAD_OE,
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LAD_OE,
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LPC_INT,
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LPC_INT,
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PREVENT_STRIPPING_OF_UNUSED_INPUTS
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PREVENT_STRIPPING_OF_UNUSED_INPUTS
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);
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);
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input CLK ;
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input CLK ;
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input RST ;
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input RST ;
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inout [31:0] PCI_AD ;
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inout [31:0] PCI_AD ;
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input CBE0,
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input CBE0,
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CBE1,
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CBE1,
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CBE2,
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CBE2,
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CBE3 ;
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CBE3 ;
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output PAR ;
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output PAR ;
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input FRAME ;
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input FRAME ;
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input IRDY ;
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input IRDY ;
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output TRDY ;
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output TRDY ;
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output DEVSEL ;
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output DEVSEL ;
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inout STOP ;
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inout STOP ;
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input IDSEL ;
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input IDSEL ;
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inout PERR ;
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inout PERR ;
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inout SERR ;
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inout SERR ;
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output INTA ;
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output INTA ;
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//attribute s: string; -- SAVE NET FLAG
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//attribute s: string; -- SAVE NET FLAG
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input REQ ; // attribute s of PCI_nREQ: signal is "yes";
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input REQ ; // attribute s of PCI_nREQ: signal is "yes";
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input GNT ; // attribute s of PCI_nGNT: signal is "yes";
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input GNT ; // attribute s of PCI_nGNT: signal is "yes";
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output [3:0] DISP_SEL ;
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output [3:0] DISP_SEL ;
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output [6:0] DISP_LED ;
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output [6:0] DISP_LED ;
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output LPC_CLK;
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output LPC_CLK;
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output LFRAME;
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output LFRAME;
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inout [3:0] LAD;
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inout [3:0] LAD;
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input LPC_INT;
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input LPC_INT;
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output LAD_OE;
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output LAD_OE;
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output PREVENT_STRIPPING_OF_UNUSED_INPUTS ;
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output PREVENT_STRIPPING_OF_UNUSED_INPUTS ;
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assign PREVENT_STRIPPING_OF_UNUSED_INPUTS = REQ & GNT;
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assign PREVENT_STRIPPING_OF_UNUSED_INPUTS = REQ & GNT;
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wire [2:0] dma_chan_i = 3'b000;
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wire [2:0] dma_chan_i = 3'b000;
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wire dma_tc_i = 1'b0;
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wire dma_tc_i = 1'b0;
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wire lframe_o;
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wire lframe_o;
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wire [3:0] lad_i;
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wire [3:0] lad_i;
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wire [3:0] lad_o;
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wire [3:0] lad_o;
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wire host_lad_oe;
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wire host_lad_oe;
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assign LAD = (host_lad_oe ? lad_o : 4'bzzzz);
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assign LAD = (host_lad_oe ? lad_o : 4'bzzzz);
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assign LAD_OE = host_lad_oe;
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assign LAD_OE = host_lad_oe;
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assign LPC_CLK = CLK;
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assign LPC_CLK = CLK;
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assign LFRAME = ~lframe_o;
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assign LFRAME = ~lframe_o;
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wire [3:0] CBE_in =
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wire [3:0] CBE_in =
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{
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{
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CBE3,
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CBE3,
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CBE2,
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CBE2,
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CBE1,
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CBE1,
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CBE0
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CBE0
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} ;
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} ;
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wire PCI_CLK = CLK;
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wire PCI_CLK = CLK;
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wire [24:0] wb_adr_o;
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wire [24:0] wb_adr_o;
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wire [31:0] wb_dat_i;
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wire [31:0] wb_dat_i;
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wire [31:0] wb_dat_o;
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wire [31:0] wb_dat_o;
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wire [3:0] wb_sel_o;
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wire [3:0] wb_sel_o;
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wire [1:0] wb_tga;
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wire [1:0] wb_tga;
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wire wb_we_o;
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wire wb_we_o;
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wire wb_stb_o;
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wire wb_stb_o;
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wire wb_cyc_o;
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wire wb_cyc_o;
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wire wb_ack_i;
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wire wb_ack_i;
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wire wb_rty_i = 1'b0;
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wire wb_rty_i = 1'b0;
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wire wb_err_i = 1'b0;
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wire wb_err_i = 1'b0;
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wire wb_int_i;
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wire wb_int_i;
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//assign wb_tga = wb_adr_o[17:16]; // I/O Cycle
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//assign wb_tga = wb_adr_o[17:16]; // I/O Cycle
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assign wb_tga = 2'b10; // Firmware cycle
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assign wb_tga = 2'b10; // Firmware cycle
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assign wb_int_i = ~LPC_INT;
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assign wb_int_i = ~LPC_INT;
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// Instantiate the pci32tlite module
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// Instantiate the pci32tlite module
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pci32tLite #(
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pci32tLite #(
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// .vendorID(16'h10ee),
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.vendorID(16'h10ee),
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// .deviceID(16'hf00d),
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.deviceID(16'hf00d),
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// .revisionID(8'h01),
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.revisionID(8'h01),
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.vendorID(16'h14e4),
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.deviceID(16'h43f5),
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.revisionID(8'h0a),
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.subsystemID(16'h0),
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.subsystemID(16'h0),
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.subsystemvID(16'h0),
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.subsystemvID(16'h0),
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.BARS("1BARMEM"),
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.BARS("1BARMEM"),
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.WBSIZE(32),
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.WBSIZE(32),
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.WBENDIAN("LITTLE"))
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.WBENDIAN("LITTLE"))
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pci_target (
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pci_target (
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.clk33(PCI_CLK),
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.clk33(PCI_CLK),
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.rst(~RST),
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.rst(~RST),
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.ad(PCI_AD),
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.ad(PCI_AD),
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.cbe(CBE_in),
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.cbe(CBE_in),
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.par(PAR),
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.par(PAR),
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.frame(FRAME),
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.frame(FRAME),
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.irdy(IRDY),
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.irdy(IRDY),
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.trdy(TRDY),
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.trdy(TRDY),
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.devsel(DEVSEL),
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.devsel(DEVSEL),
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.stop(STOP),
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.stop(STOP),
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.idsel(IDSEL),
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.idsel(IDSEL),
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.perr(PERR),
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.perr(PERR),
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.serr(SERR),
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.serr(SERR),
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.intb(INTA),
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.intb(INTA),
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.wb_adr_o(wb_adr_o),
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.wb_adr_o(wb_adr_o),
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.wb_dat_i(wb_dat_i),
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.wb_dat_i(wb_dat_i),
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.wb_dat_o(wb_dat_o),
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.wb_dat_o(wb_dat_o),
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.wb_sel_o(wb_sel_o),
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.wb_sel_o(wb_sel_o),
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.wb_we_o(wb_we_o),
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.wb_we_o(wb_we_o),
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.wb_stb_o(wb_stb_o),
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.wb_stb_o(wb_stb_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_ack_i(wb_ack_i),
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.wb_ack_i(wb_ack_i),
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.wb_rty_i(wb_rty_i),
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.wb_rty_i(wb_rty_i),
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.wb_err_i(wb_err_i),
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.wb_err_i(wb_err_i),
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.wb_int_i(wb_int_i)
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.wb_int_i(wb_int_i)
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);
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);
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wb_lpc_host lpc_host (
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wb_lpc_host lpc_host (
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.clk_i(CLK),
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.clk_i(CLK),
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.nrst_i(RST),
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.nrst_i(RST),
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.wbs_adr_i(wb_adr_o),
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.wbs_adr_i(wb_adr_o),
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.wbs_dat_o(wb_dat_i),
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.wbs_dat_o(wb_dat_i),
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.wbs_dat_i(wb_dat_o),
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.wbs_dat_i(wb_dat_o),
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.wbs_sel_i(wb_sel_o),
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.wbs_sel_i(wb_sel_o),
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.wbs_tga_i(wb_tga),
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.wbs_tga_i(wb_tga),
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.wbs_we_i(wb_we_o),
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.wbs_we_i(wb_we_o),
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.wbs_stb_i(wb_stb_o),
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.wbs_stb_i(wb_stb_o),
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.wbs_cyc_i(wb_cyc_o),
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.wbs_cyc_i(wb_cyc_o),
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.wbs_ack_o(wb_ack_i),
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.wbs_ack_o(wb_ack_i),
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.dma_chan_i(dma_chan_i),
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.dma_chan_i(dma_chan_i),
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.dma_tc_i(dma_tc_i),
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.dma_tc_i(dma_tc_i),
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.lframe_o(lframe_o),
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.lframe_o(lframe_o),
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.lad_i(LAD),
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.lad_i(LAD),
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.lad_o(lad_o),
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.lad_o(lad_o),
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.lad_oe(host_lad_oe)
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.lad_oe(host_lad_oe)
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);
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);
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// The 7-segment display is write-only from the PCI interface.
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// The 7-segment display is write-only from the PCI interface.
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// Use some dummy nets for inputs that are ignored.
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// Use some dummy nets for inputs that are ignored.
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wire [31:0] wb2_dat_i;
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wire [31:0] wb2_dat_i;
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wire wb2_ack_i;
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wire wb2_ack_i;
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wire wb2_err_i;
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wire wb2_err_i;
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wire wb2_int_i;
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wire wb2_int_i;
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// Instantiate the 7-Segment module on the host
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// Instantiate the 7-Segment module on the host
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wb_7seg seven_seg0 (
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wb_7seg seven_seg0 (
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.clk_i(CLK),
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.clk_i(CLK),
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.nrst_i(RST),
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.nrst_i(RST),
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.wb_adr_i(wb_adr_o),
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.wb_adr_i(wb_adr_o),
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.wb_dat_o(wb2_dat_i),
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.wb_dat_o(wb2_dat_i),
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.wb_dat_i(wb_dat_o),
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.wb_dat_i(wb_dat_o),
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.wb_sel_i(wb_sel_o),
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.wb_sel_i(wb_sel_o),
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.wb_we_i(wb_we_o),
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.wb_we_i(wb_we_o),
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.wb_stb_i(wb_stb_o),
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.wb_stb_i(wb_stb_o),
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.wb_cyc_i(wb_cyc_o),
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.wb_cyc_i(wb_cyc_o),
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.wb_ack_o(wb2_ack_i),
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.wb_ack_o(wb2_ack_i),
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.wb_err_o(wb2_err_i),
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.wb_err_o(wb2_err_i),
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.wb_int_o(wb2_int_i),
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.wb_int_o(wb2_int_i),
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.DISP_SEL(DISP_SEL),
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.DISP_SEL(DISP_SEL),
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.DISP_LED(DISP_LED)
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.DISP_LED(DISP_LED)
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);
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);
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endmodule
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endmodule
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