//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
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//// $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
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//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
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//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/lpc/ ////
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//// http://www.opencores.org/projects/lpc/ ////
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//// ////
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//// ////
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//// Author: ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ns
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`timescale 1 ns / 1 ns
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`include "../../rtl/verilog/serirq_defines.v"
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`include "../../rtl/verilog/serirq_defines.v"
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module serirq_slave(clk_i, nrst_i,
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module serirq_slave(clk_i, nrst_i,
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irq_i,
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irq_i,
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serirq_o, serirq_i, serirq_oe
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serirq_o, serirq_i, serirq_oe
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);
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);
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// Wishbone Slave Interface
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// Wishbone Slave Interface
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input clk_i;
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input clk_i;
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input nrst_i; // Active low reset.
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input nrst_i; // Active low reset.
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// SERIRQ Master Interface
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// SERIRQ Master Interface
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output reg serirq_o; // SERIRQ output
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output reg serirq_o; // SERIRQ output
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input serirq_i; // SERIRQ Input
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input serirq_i; // SERIRQ Input
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output reg serirq_oe; // SERIRQ Output Enable
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output reg serirq_oe; // SERIRQ Output Enable
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input [31:0] irq_i; // IRQ Input Bus
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input [31:0] irq_i; // IRQ Input Bus
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reg [31:0] current_irq;
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reg [31:0] current_irq;
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reg [12:0] state; // Current state
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reg [12:0] state; // Current state
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reg [4:0] irq_cnt; // IRQ Frame counter
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reg [4:0] irq_cnt; // IRQ Frame counter
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reg found_stop;
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reg found_stop;
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reg found_start;
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reg found_start;
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reg serirq_mode;
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reg serirq_mode;
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wire irq_changed = (serirq_mode & (current_irq != irq_i));
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wire irq_changed = (serirq_mode & (current_irq != irq_i));
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always @(posedge clk_i or negedge nrst_i)
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always @(posedge clk_i or negedge nrst_i)
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if(~nrst_i)
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if(~nrst_i)
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begin
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begin
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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serirq_o <= 4'b1;
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serirq_o <= 4'b1;
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irq_cnt <= 5'h00;
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irq_cnt <= 5'h00;
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current_irq <= irq_i;
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current_irq <= irq_i;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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`SERIRQ_ST_IDLE:
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`SERIRQ_ST_IDLE:
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begin
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begin
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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irq_cnt <= 5'h00;
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irq_cnt <= 5'h00;
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serirq_o <= 1'b1;
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serirq_o <= 1'b1;
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if(found_start == 1'b1) // Wait for Start cycle
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if(found_start == 1'b1) // Wait for Start cycle
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begin
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begin
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current_irq <= irq_i;
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current_irq <= irq_i;
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if(irq_i[irq_cnt] == 1'b0) begin
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if(irq_i[irq_cnt] == 1'b0) begin
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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end
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end
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state <= `SERIRQ_ST_IRQ_R;
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state <= `SERIRQ_ST_IRQ_R;
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end
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end
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else if(irq_changed) begin
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else if(irq_changed) begin
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current_irq <= irq_i;
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current_irq <= irq_i;
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end else
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end else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end
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end
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`SERIRQ_ST_IRQ:
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`SERIRQ_ST_IRQ:
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begin
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begin
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if(irq_i[irq_cnt] == 1'b0) begin
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if(irq_i[irq_cnt] == 1'b0) begin
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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end
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end
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if(found_stop == 1'b0)
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if(found_stop == 1'b0)
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state <= `SERIRQ_ST_IRQ_R;
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state <= `SERIRQ_ST_IRQ_R;
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else
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else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end
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end
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`SERIRQ_ST_IRQ_R:
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`SERIRQ_ST_IRQ_R:
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begin
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begin
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serirq_o <= 1'b1;
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serirq_o <= 1'b1;
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if(found_stop == 1'b0)
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if(found_stop == 1'b0)
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state <= `SERIRQ_ST_IRQ_T;
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state <= `SERIRQ_ST_IRQ_T;
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else
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else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end
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end
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`SERIRQ_ST_IRQ_T:
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`SERIRQ_ST_IRQ_T:
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begin
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begin
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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if(irq_cnt == 5'h1f)
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if(irq_cnt == 5'h1f)
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begin
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begin
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state <= `SERIRQ_ST_WAIT_STOP;
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state <= `SERIRQ_ST_WAIT_STOP;
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end
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end
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else begin
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else begin
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irq_cnt <= irq_cnt + 1;
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irq_cnt <= irq_cnt + 1;
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if(found_stop == 1'b0)
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if(found_stop == 1'b0)
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state <= `SERIRQ_ST_IRQ;
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state <= `SERIRQ_ST_IRQ;
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else
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else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end
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end
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end
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end
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`SERIRQ_ST_WAIT_STOP:
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`SERIRQ_ST_WAIT_STOP:
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begin
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begin
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if(found_stop == 1'b0)
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if(found_stop == 1'b0)
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state <= `SERIRQ_ST_WAIT_STOP;
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state <= `SERIRQ_ST_WAIT_STOP;
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else
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else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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reg [3:0] stop_clk_cnt;
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reg [3:0] stop_clk_cnt;
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// Look for STOP cycles
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// Look for STOP cycles
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always @(posedge clk_i or negedge nrst_i)
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always @(posedge clk_i or negedge nrst_i)
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if(~nrst_i)
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if(~nrst_i)
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begin
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begin
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found_stop <= 1'b0;
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found_stop <= 1'b0;
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found_start <= 1'b0;
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found_start <= 1'b0;
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serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
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serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
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stop_clk_cnt <= 4'h0;
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stop_clk_cnt <= 4'h0;
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end
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end
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else begin
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else begin
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if(serirq_i == 1'b0) begin
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if(serirq_i == 1'b0) begin
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stop_clk_cnt <= stop_clk_cnt + 1;
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stop_clk_cnt <= stop_clk_cnt + 1;
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end
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end
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else begin
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else begin
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case (stop_clk_cnt)
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case (stop_clk_cnt)
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4'h2:
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4'h2:
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begin
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begin
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found_stop <= 1'b1;
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found_stop <= 1'b1;
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found_start <= 1'b0;
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found_start <= 1'b0;
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serirq_mode <= `SERIRQ_MODE_QUIET;
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serirq_mode <= `SERIRQ_MODE_QUIET;
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end
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end
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4'h3:
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4'h3:
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begin
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begin
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found_stop <= 1'b1;
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found_stop <= 1'b1;
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found_start <= 1'b0;
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found_start <= 1'b0;
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serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
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serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
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end
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end
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4'h4:
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4'h4:
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begin
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begin
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found_stop <= 1'b0;
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found_stop <= 1'b0;
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found_start <= 1'b1;
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found_start <= 1'b1;
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end
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end
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4'h6:
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4'h6:
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begin
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begin
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found_stop <= 1'b0;
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found_stop <= 1'b0;
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found_start <= 1'b1;
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found_start <= 1'b1;
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end
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end
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4'h8:
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4'h8:
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begin
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begin
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found_stop <= 1'b0;
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found_stop <= 1'b0;
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found_start <= 1'b1;
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found_start <= 1'b1;
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end
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end
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default:
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default:
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begin
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begin
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found_stop <= 1'b0;
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found_stop <= 1'b0;
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found_start <= 1'b0;
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found_start <= 1'b0;
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end
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end
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endcase
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endcase
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stop_clk_cnt <= 4'h0;
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stop_clk_cnt <= 4'h0;
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end
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end
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end
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end
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endmodule
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endmodule
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