//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// wb_lpc_defines.v ////
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//// wb_lpc_defines.v ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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//// Author: ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// Wishbone LPC Master/Slave Interface Definitions
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// Wishbone LPC Master/Slave Interface Definitions
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`define LPC_START 4'b0000
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`define LPC_START 4'b0000
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`define LPC_STOP 4'b1111
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`define LPC_STOP 4'b1111
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`define LPC_FW_READ 4'b1101
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`define LPC_FW_READ 4'b1101
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`define LPC_FW_WRITE 4'b1110
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`define LPC_FW_WRITE 4'b1110
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`define LPC_SYNC_READY 4'b0000 // LPC Sync Ready
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`define LPC_SYNC_READY 4'b0000 // LPC Sync Ready
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`define LPC_SYNC_SWAIT 4'b0101 // LPC Sync Short Wait
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`define LPC_SYNC_SWAIT 4'b0101 // LPC Sync Short Wait (up to 8 cycles)
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`define LPC_SYNC_LWAIT 4'b0110 // LPC Sync Long Wait
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`define LPC_SYNC_LWAIT 4'b0110 // LPC Sync Long Wait (no limit)
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`define LPC_SYNC_MORE 4'b1001 // LPC Sync Ready More (DMA only)
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`define LPC_SYNC_MORE 4'b1001 // LPC Sync Ready More (DMA only)
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`define LPC_SYNC_ERROR 4'b1010 // LPC Sync Error
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`define LPC_SYNC_ERROR 4'b1010 // LPC Sync Error
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`define LPC_ST_IDLE 13'h000 // LPC Idle state
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`define LPC_ST_IDLE 13'h000 // LPC Idle state
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`define LPC_ST_START 13'h001 // LPC Start state
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`define LPC_ST_START 13'h001 // LPC Start state
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`define LPC_ST_CYCTYP 13'h002 // LPC Cycle Type State
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`define LPC_ST_CYCTYP 13'h002 // LPC Cycle Type State
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`define LPC_ST_ADDR 13'h004 // LPC Address state (4 cycles)
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`define LPC_ST_ADDR 13'h004 // LPC Address state (4 cycles)
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`define LPC_ST_CHAN 13'h008 // LPC Address state (4 cycles)
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`define LPC_ST_CHAN 13'h008 // LPC Address state (4 cycles)
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`define LPC_ST_SIZE 13'h010 // LPC Address state (4 cycles)
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`define LPC_ST_SIZE 13'h010 // LPC Address state (4 cycles)
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`define LPC_ST_H_DATA 13'h020 // LPC Host Data state (2 cycles)
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`define LPC_ST_H_DATA 13'h020 // LPC Host Data state (2 cycles)
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`define LPC_ST_P_DATA 13'h040 // LPC Peripheral Data state (2 cycles)
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`define LPC_ST_P_DATA 13'h040 // LPC Peripheral Data state (2 cycles)
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`define LPC_ST_H_TAR1 13'h080 // LPC Host Turnaround 1 (Drive LAD 4'hF)
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`define LPC_ST_H_TAR1 13'h080 // LPC Host Turnaround 1 (Drive LAD 4'hF)
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`define LPC_ST_H_TAR2 13'h100 // LPC Host Turnaround 2 (Float LAD)
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`define LPC_ST_H_TAR2 13'h100 // LPC Host Turnaround 2 (Float LAD)
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`define LPC_ST_P_TAR1 13'h200 // LPC Peripheral Turnaround 1 (Drive LAD = 4'hF)
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`define LPC_ST_P_TAR1 13'h200 // LPC Peripheral Turnaround 1 (Drive LAD = 4'hF)
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`define LPC_ST_P_TAR2 13'h400 // LPC Peripheral Turnaround 2 (Float LAD)
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`define LPC_ST_P_TAR2 13'h400 // LPC Peripheral Turnaround 2 (Float LAD)
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`define LPC_ST_WB_RETIRE 13'h400 // Retire Wishbone transfer (Host only), ends WB cycle.
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`define LPC_ST_WB_RETIRE 13'h400 // Retire Wishbone transfer (Host only), ends WB cycle.
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`define LPC_ST_SYNC 13'h800 // LPC Sync State (may be multiple cycles for wait-states)
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`define LPC_ST_SYNC 13'h800 // LPC Sync State (may be multiple cycles for wait-states)
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`define LPC_ST_P_WAIT1 13'h1000 // LPC Sync State (may be multiple cycles for wait-states)
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`define LPC_ST_P_WAIT1 13'h1000 // LPC Sync State (may be multiple cycles for wait-states)
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`define WB_SEL_BYTE 4'b0001 // Byte Transfer
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`define WB_SEL_BYTE 4'b0001 // Byte Transfer
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`define WB_SEL_SHORT 4'b0011 // Short Transfer
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`define WB_SEL_SHORT 4'b0011 // Short Transfer
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`define WB_SEL_WORD 4'b1111 // Word Transfer
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`define WB_SEL_WORD 4'b1111 // Word Transfer
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`define WB_TGA_MEM 2'b00 // Memory Cycle
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`define WB_TGA_MEM 2'b00 // Memory Cycle
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`define WB_TGA_IO 2'b01 // I/O Cycle
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`define WB_TGA_IO 2'b01 // I/O Cycle
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`define WB_TGA_FW 2'b10 // Firmware Cycle
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`define WB_TGA_FW 2'b10 // Firmware Cycle
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`define WB_TGA_DMA 2'b11 // DMA Cycle
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`define WB_TGA_DMA 2'b11 // DMA Cycle
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// LDRQ States
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// LDRQ States
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`define LDRQ_ST_IDLE 4'h0
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`define LDRQ_ST_IDLE 4'h0
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`define LDRQ_ST_ADDR 4'h1
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`define LDRQ_ST_ADDR 4'h1
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`define LDRQ_ST_ACT 4'h2
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`define LDRQ_ST_ACT 4'h2
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`define LDRQ_ST_DONE 4'h4
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`define LDRQ_ST_DONE 4'h4
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