//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_serirq_top.v ////
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//// tb_serirq_top.v ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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//// Author: ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ns
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`timescale 1 ns / 1 ns
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`include "../../rtl/verilog/serirq_defines.v"
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`include "../../rtl/verilog/serirq_defines.v"
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// Define Module for Test Fixture
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// Define Module for Test Fixture
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module serirq_host_bench();
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module serirq_host_bench();
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// SERIRQ Host Inputs
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// SERIRQ Host Inputs
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reg clk_i;
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reg clk_i;
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reg nrst_i;
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reg nrst_i;
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reg serirq_mode;
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reg serirq_mode;
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// SERIRQ Host Outputs
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// SERIRQ Host Outputs
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wire serirq_o;
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wire serirq_o;
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wire serirq_oe;
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wire serirq_oe;
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wire [31:0] irq_o;
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wire [31:0] irq_o;
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// Bidirs
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// Bidirs
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wire serirq;
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wire serirq;
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// SERIRQ Slave
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// SERIRQ Slave
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wire slave_serirq_o;
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wire slave_serirq_o;
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wire slave_serirq_oe;
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wire slave_serirq_oe;
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reg [31:0] irq_i;
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reg [31:0] irq_i;
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task Reset;
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task Reset;
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begin
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begin
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nrst_i = 1; # 1000;
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nrst_i = 1; # 1000;
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nrst_i = 0; # 1000;
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nrst_i = 0; # 1000;
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nrst_i = 1; # 1000;
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nrst_i = 1; # 1000;
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end
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end
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endtask
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endtask
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always begin
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always begin
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#50 clk_i = 0;
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#50 clk_i = 0;
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#50 clk_i = 1;
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#50 clk_i = 1;
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end
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end
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// Instantiate the UUT
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// Instantiate the UUT
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serirq_host UUT_Serirq_Host (
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serirq_host UUT_Serirq_Host (
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.clk_i(clk_i),
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.clk_i(clk_i),
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.nrst_i(nrst_i),
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.nrst_i(nrst_i),
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.serirq_mode_i(serirq_mode),
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.serirq_mode_i(serirq_mode),
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.irq_o(irq_o),
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.irq_o(irq_o),
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.serirq_o(serirq_o),
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.serirq_o(serirq_o),
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.serirq_i(serirq),
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.serirq_i(serirq),
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.serirq_oe(serirq_oe)
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.serirq_oe(serirq_oe)
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);
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);
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// Instantiate the UUT Slave
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// Instantiate the UUT Slave
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serirq_slave UUT_Serirq_Slave (
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serirq_slave UUT_Serirq_Slave (
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.clk_i(clk_i),
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.clk_i(clk_i),
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.nrst_i(nrst_i),
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.nrst_i(nrst_i),
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.irq_i(irq_i),
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.irq_i(irq_i),
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.serirq_o(slave_serirq_o),
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.serirq_o(slave_serirq_o),
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.serirq_i(serirq),
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.serirq_i(serirq),
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.serirq_oe(slave_serirq_oe)
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.serirq_oe(slave_serirq_oe)
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);
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);
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assign serirq = (serirq_oe ? serirq_o : (slave_serirq_oe ? slave_serirq_o : 1'bz));
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assign serirq = (serirq_oe ? serirq_o : (slave_serirq_oe ? slave_serirq_o : 1'bz));
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// Initialize Inputs
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// Initialize Inputs
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initial begin
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initial begin
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// $monitor("Time: %d clk_i=%b",
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// $monitor("Time: %d clk_i=%b",
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// $time, clk_i);
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// $time, clk_i);
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clk_i = 0;
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clk_i = 0;
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nrst_i = 1;
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nrst_i = 1;
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irq_i = 32'hA5a51234;
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irq_i = 32'hA5a51234;
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serirq_mode = `SERIRQ_MODE_CONTINUOUS;
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serirq_mode = `SERIRQ_MODE_CONTINUOUS;
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Reset();
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Reset();
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$display($time, " Testing SERIRQ Accesses in Continuous mode.");
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$display($time, " Testing SERIRQ Accesses in Continuous mode.");
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# 40000;
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# 40000;
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if(irq_i != irq_o) begin
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if(irq_i != irq_o) begin
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$display($time, " Error, irq_i: expected %x, got %x", irq_i, irq_o); $stop(1);
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$display($time, " Error, irq_i: expected %x, got %x", irq_i, irq_o); $stop(1);
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end
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end
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irq_i = 32'h5a5a4321;
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irq_i = 32'h5a5a4321;
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$display($time, " Testing SERIRQ Accesses, Switch to Quiet Mode");
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$display($time, " Testing SERIRQ Accesses, Switch to Quiet Mode");
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serirq_mode = `SERIRQ_MODE_QUIET;
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serirq_mode = `SERIRQ_MODE_QUIET;
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# 40000;
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# 40000;
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if(irq_i != irq_o) begin
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if(irq_i != irq_o) begin
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$display($time, " Error, irq_i: expected %x, got %x", irq_i, irq_o); $stop(1);
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$display($time, " Error, irq_i: expected %x, got %x", irq_i, irq_o); $stop(1);
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end
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end
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irq_i = 32'h5555aaaa;
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irq_i = 32'h5555aaaa;
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$display($time, " Slave should start serirq sequence");
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$display($time, " Slave should start serirq sequence");
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# 15000;
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# 15000;
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irq_i = 32'ha5a5a5a5;
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irq_i = 32'ha5a5a5a5;
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$display($time, " Testing SERIRQ Accesses");
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$display($time, " Testing SERIRQ Accesses");
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# 40000;
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# 40000;
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$display($time, " Switch back to Continuous");
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$display($time, " Switch back to Continuous");
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serirq_mode = `SERIRQ_MODE_CONTINUOUS;
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serirq_mode = `SERIRQ_MODE_CONTINUOUS;
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# 80000;
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# 80000;
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if(irq_i != irq_o) begin
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if(irq_i != irq_o) begin
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$display($time, " Error, irq_i: expected %x, got %x", irq_i, irq_o); $stop(1);
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$display($time, " Error, irq_i: expected %x, got %x", irq_i, irq_o); $stop(1);
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end
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end
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$display($time, " Simulation passed"); $stop(1);
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$display($time, " Simulation passed"); $stop(1);
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end
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end
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endmodule // serirq_tb
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endmodule // serirq_tb
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