//////////////////////////////////////////////////////////////////////
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//
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//// ////
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//
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module async_mem_if( async_dq, async_addr, async_ub_n, async_lb_n,
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module async_mem_if( async_dq, async_addr, async_ub_n, async_lb_n,
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async_we_n, async_ce_n, async_oe_n,
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async_we_n, async_ce_n, async_oe_n,
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i,
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_sel_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_sel_i,
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wb_dat_o, wb_ack_o,
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wb_dat_o, wb_ack_o,
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ce_setup, op_hold, ce_hold,
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ce_setup, op_hold, ce_hold,
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big_endian_if_i, lo_byte_if_i
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big_endian_if_i, lo_byte_if_i
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);
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);
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parameter AW = 32;
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parameter AW = 32;
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parameter DW = 8;
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parameter DW = 8;
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inout [(DW-1):0] async_dq;
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inout [(DW-1):0] async_dq;
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output [(AW-1):0] async_addr;
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output [(AW-1):0] async_addr;
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output async_ub_n;
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output async_ub_n;
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output async_lb_n;
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output async_lb_n;
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output async_we_n;
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output async_we_n;
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output async_ce_n;
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output async_ce_n;
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output async_oe_n;
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output async_oe_n;
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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input [31:0] wb_adr_i;
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input [31:0] wb_adr_i;
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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input wb_we_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input [3:0] wb_sel_i;
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input [3:0] wb_sel_i;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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output wb_ack_o;
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output wb_ack_o;
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input [3:0] ce_setup;
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input [3:0] ce_setup;
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input [3:0] op_hold; // do not set to zero.
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input [3:0] op_hold; // do not set to zero.
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input [3:0] ce_hold;
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input [3:0] ce_hold;
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input big_endian_if_i;
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input big_endian_if_i;
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input lo_byte_if_i;
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input lo_byte_if_i;
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//---------------------------------------------------
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//---------------------------------------------------
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// big endian bridge
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// big endian bridge
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wire [31:0] beb_wb_dat_i;
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wire [31:0] beb_wb_dat_i;
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assign beb_wb_dat_i[7:0] = big_endian_if_i ? wb_dat_i[31:24] : wb_dat_i[7:0];
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assign beb_wb_dat_i[7:0] = big_endian_if_i ? wb_dat_i[31:24] : wb_dat_i[7:0];
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assign beb_wb_dat_i[15:8] = big_endian_if_i ? wb_dat_i[23:16] : wb_dat_i[15:8];
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assign beb_wb_dat_i[15:8] = big_endian_if_i ? wb_dat_i[23:16] : wb_dat_i[15:8];
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assign beb_wb_dat_i[23:16] = big_endian_if_i ? wb_dat_i[15:8] : wb_dat_i[23:16];
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assign beb_wb_dat_i[23:16] = big_endian_if_i ? wb_dat_i[15:8] : wb_dat_i[23:16];
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assign beb_wb_dat_i[31:24] = big_endian_if_i ? wb_dat_i[7:0] : wb_dat_i[31:24];
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assign beb_wb_dat_i[31:24] = big_endian_if_i ? wb_dat_i[7:0] : wb_dat_i[31:24];
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wire [31:0] beb_wb_dat_o;
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wire [31:0] beb_wb_dat_o;
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assign wb_dat_o[7:0] = big_endian_if_i ? beb_wb_dat_o[31:24] : beb_wb_dat_o[7:0];
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assign wb_dat_o[7:0] = big_endian_if_i ? beb_wb_dat_o[31:24] : beb_wb_dat_o[7:0];
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assign wb_dat_o[15:8] = big_endian_if_i ? beb_wb_dat_o[23:16] : beb_wb_dat_o[15:8];
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assign wb_dat_o[15:8] = big_endian_if_i ? beb_wb_dat_o[23:16] : beb_wb_dat_o[15:8];
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assign wb_dat_o[23:16] = big_endian_if_i ? beb_wb_dat_o[15:8] : beb_wb_dat_o[23:16];
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assign wb_dat_o[23:16] = big_endian_if_i ? beb_wb_dat_o[15:8] : beb_wb_dat_o[23:16];
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assign wb_dat_o[31:24] = big_endian_if_i ? beb_wb_dat_o[7:0] : beb_wb_dat_o[31:24];
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assign wb_dat_o[31:24] = big_endian_if_i ? beb_wb_dat_o[7:0] : beb_wb_dat_o[31:24];
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wire [3:0] beb_wb_sel_i;
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wire [3:0] beb_wb_sel_i;
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assign beb_wb_sel_i[0] = big_endian_if_i ? wb_sel_i[3] : wb_sel_i[0];
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assign beb_wb_sel_i[0] = big_endian_if_i ? wb_sel_i[3] : wb_sel_i[0];
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assign beb_wb_sel_i[1] = big_endian_if_i ? wb_sel_i[2] : wb_sel_i[1];
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assign beb_wb_sel_i[1] = big_endian_if_i ? wb_sel_i[2] : wb_sel_i[1];
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assign beb_wb_sel_i[2] = big_endian_if_i ? wb_sel_i[1] : wb_sel_i[2];
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assign beb_wb_sel_i[2] = big_endian_if_i ? wb_sel_i[1] : wb_sel_i[2];
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assign beb_wb_sel_i[3] = big_endian_if_i ? wb_sel_i[0] : wb_sel_i[3];
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assign beb_wb_sel_i[3] = big_endian_if_i ? wb_sel_i[0] : wb_sel_i[3];
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//---------------------------------------------------
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//---------------------------------------------------
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// wb_size_bridge
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// wb_size_bridge
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wire [15:0] wb_lo_dat_o;
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wire [15:0] wb_lo_dat_o;
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wire [15:0] wb_lo_dat_i;
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wire [15:0] wb_lo_dat_i;
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wire [31:0] wb_lo_adr_o;
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wire [31:0] wb_lo_adr_o;
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wire wb_lo_cyc_o;
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wire wb_lo_cyc_o;
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wire wb_lo_stb_o;
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wire wb_lo_stb_o;
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wire wb_lo_we_o;
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wire wb_lo_we_o;
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wire [1:0] wb_lo_sel_o;
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wire [1:0] wb_lo_sel_o;
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wire wb_lo_ack_i;
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wire wb_lo_ack_i;
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wire wb_lo_err_i = 1'b0;
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wire wb_lo_err_i = 1'b0;
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wire wb_lo_rty_i = 1'b0;
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wire wb_lo_rty_i = 1'b0;
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wb_size_bridge i_wb_size_bridge(
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wb_size_bridge i_wb_size_bridge(
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.wb_hi_clk_i(wb_clk_i),
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.wb_hi_clk_i(wb_clk_i),
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.wb_hi_rst_i(wb_rst_i),
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.wb_hi_rst_i(wb_rst_i),
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.wb_hi_dat_o(beb_wb_dat_o),
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.wb_hi_dat_o(beb_wb_dat_o),
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.wb_hi_dat_i(beb_wb_dat_i),
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.wb_hi_dat_i(beb_wb_dat_i),
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.wb_hi_adr_i( wb_adr_i ),
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.wb_hi_adr_i( wb_adr_i ),
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.wb_hi_cyc_i(wb_cyc_i),
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.wb_hi_cyc_i(wb_cyc_i),
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.wb_hi_stb_i(wb_stb_i),
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.wb_hi_stb_i(wb_stb_i),
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.wb_hi_we_i(wb_we_i),
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.wb_hi_we_i(wb_we_i),
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.wb_hi_sel_i(beb_wb_sel_i),
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.wb_hi_sel_i(beb_wb_sel_i),
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.wb_hi_ack_o(wb_ack_o),
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.wb_hi_ack_o(wb_ack_o),
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.wb_hi_err_o(),
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.wb_hi_err_o(),
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.wb_hi_rty_o(),
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.wb_hi_rty_o(),
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.wb_lo_clk_o(),
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.wb_lo_clk_o(),
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.wb_lo_rst_o(),
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.wb_lo_rst_o(),
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.wb_lo_dat_i(wb_lo_dat_i),
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.wb_lo_dat_i(wb_lo_dat_i),
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.wb_lo_dat_o(wb_lo_dat_o),
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.wb_lo_dat_o(wb_lo_dat_o),
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.wb_lo_adr_o(wb_lo_adr_o),
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.wb_lo_adr_o(wb_lo_adr_o),
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.wb_lo_cyc_o(wb_lo_cyc_o),
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.wb_lo_cyc_o(wb_lo_cyc_o),
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.wb_lo_stb_o(wb_lo_stb_o),
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.wb_lo_stb_o(wb_lo_stb_o),
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.wb_lo_we_o(wb_lo_we_o),
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.wb_lo_we_o(wb_lo_we_o),
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.wb_lo_sel_o(wb_lo_sel_o),
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.wb_lo_sel_o(wb_lo_sel_o),
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.wb_lo_ack_i(wb_lo_ack_i),
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.wb_lo_ack_i(wb_lo_ack_i),
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.wb_lo_err_i(wb_lo_err_i),
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.wb_lo_err_i(wb_lo_err_i),
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.wb_lo_rty_i(wb_lo_rty_i),
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.wb_lo_rty_i(wb_lo_rty_i),
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.lo_byte_if_i(lo_byte_if_i)
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.lo_byte_if_i(lo_byte_if_i)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine inputs
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// state machine inputs
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wire zero_ce_setup = (ce_setup == 4'h0);
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wire zero_ce_setup = (ce_setup == 4'h0);
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wire zero_ce_hold = (ce_hold == 4'h0);
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wire zero_ce_hold = (ce_hold == 4'h0);
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wire wait_for_counter;
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wire wait_for_counter;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine
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// state machine
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localparam STATE_DONT_CARE = 4'b????;
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localparam STATE_DONT_CARE = 4'b????;
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localparam STATE_IDLE = 4'b0001;
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localparam STATE_IDLE = 4'b0001;
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localparam STATE_CE_SETUP = 4'b0010;
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localparam STATE_CE_SETUP = 4'b0010;
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localparam STATE_OP_HOLD = 4'b0100;
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localparam STATE_OP_HOLD = 4'b0100;
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localparam STATE_CE_HOLD = 4'b1000;
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localparam STATE_CE_HOLD = 4'b1000;
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reg [3:0] state;
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reg [3:0] state;
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reg [3:0] next_state;
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reg [3:0] next_state;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if(wb_rst_i)
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if(wb_rst_i)
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state <= STATE_IDLE;
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state <= STATE_IDLE;
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else
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else
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state <= next_state;
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state <= next_state;
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always @(*)
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always @(*)
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case( state )
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case( state )
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STATE_IDLE: if( wb_stb_i & wb_cyc_i )
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STATE_IDLE: if( wb_stb_i & wb_cyc_i )
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if( zero_ce_setup )
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if( zero_ce_setup )
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next_state = STATE_OP_HOLD;
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next_state = STATE_OP_HOLD;
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else
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else
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next_state = STATE_CE_SETUP;
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next_state = STATE_CE_SETUP;
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else
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else
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next_state = STATE_IDLE;
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next_state = STATE_IDLE;
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STATE_CE_SETUP: if( wait_for_counter )
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STATE_CE_SETUP: if( wait_for_counter )
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next_state = STATE_CE_SETUP;
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next_state = STATE_CE_SETUP;
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else
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else
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next_state = STATE_OP_HOLD;
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next_state = STATE_OP_HOLD;
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STATE_OP_HOLD: if( wait_for_counter )
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STATE_OP_HOLD: if( wait_for_counter )
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next_state = STATE_OP_HOLD;
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next_state = STATE_OP_HOLD;
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else
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else
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if( zero_ce_hold )
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if( zero_ce_hold )
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next_state = STATE_IDLE;
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next_state = STATE_IDLE;
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else
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else
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next_state = STATE_CE_HOLD;
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next_state = STATE_CE_HOLD;
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STATE_CE_HOLD: if( wait_for_counter )
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STATE_CE_HOLD: if( wait_for_counter )
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next_state = STATE_CE_HOLD;
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next_state = STATE_CE_HOLD;
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else
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else
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next_state = STATE_IDLE;
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next_state = STATE_IDLE;
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default: next_state = STATE_IDLE;
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default: next_state = STATE_IDLE;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine outputs
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// state machine outputs
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wire assert_ce = (state != STATE_IDLE);
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wire assert_ce = (state != STATE_IDLE);
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// wire assert_op = (state == STATE_OP_HOLD) | (state == STATE_CE_HOLD);
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wire assert_op = (state == STATE_OP_HOLD);
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wire assert_op = (state == STATE_OP_HOLD);
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assign wb_lo_ack_i = ( (state == STATE_OP_HOLD) & ~wait_for_counter & zero_ce_hold) |
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assign wb_lo_ack_i = ( (state == STATE_OP_HOLD) & ~wait_for_counter & zero_ce_hold) |
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( (state == STATE_CE_HOLD) & ~wait_for_counter );
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( (state == STATE_CE_HOLD) & ~wait_for_counter );
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//---------------------------------------------------
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//---------------------------------------------------
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// async_dq_buffer
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// async_dq_buffer
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reg [(DW-1):0] async_dq_buffer;
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reg [(DW-1):0] async_dq_buffer;
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wire async_dq_buffer_en = (state == STATE_OP_HOLD);
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wire async_dq_buffer_en = (state == STATE_OP_HOLD);
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if(async_dq_buffer_en)
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if(async_dq_buffer_en)
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async_dq_buffer <= async_dq;
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async_dq_buffer <= async_dq;
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else
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else
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async_dq_buffer <= async_dq_buffer;
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async_dq_buffer <= async_dq_buffer;
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//---------------------------------------------------
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//---------------------------------------------------
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// bypass_mux
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// bypass_mux
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wire bypass_mux_en = (state == STATE_OP_HOLD) & zero_ce_hold;
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wire bypass_mux_en = (state == STATE_OP_HOLD) & zero_ce_hold;
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wire [(DW-1):0] bypass_mux;
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wire [(DW-1):0] bypass_mux;
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assign bypass_mux = bypass_mux_en ? async_dq : async_dq_buffer;
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assign bypass_mux = bypass_mux_en ? async_dq : async_dq_buffer;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// wait counter mux
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// wait counter mux
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reg [3:0] counter_mux;
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reg [3:0] counter_mux;
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always @(*)
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always @(*)
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case( next_state )
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case( next_state )
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STATE_CE_SETUP: counter_mux = ce_setup;
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STATE_CE_SETUP: counter_mux = ce_setup;
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STATE_OP_HOLD: counter_mux = op_hold;
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STATE_OP_HOLD: counter_mux = op_hold;
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STATE_CE_HOLD: counter_mux = ce_hold;
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STATE_CE_HOLD: counter_mux = ce_hold;
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default: counter_mux = 4'bxxxx;
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default: counter_mux = 4'bxxxx;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// wait counter
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// wait counter
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reg [3:0] counter;
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reg [3:0] counter;
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wire counter_load = ~(state == next_state);
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wire counter_load = ~(state == next_state);
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if( counter_load )
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if( counter_load )
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counter <= counter_mux - 1'b1;
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counter <= counter_mux - 1'b1;
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else
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else
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counter <= counter - 1'b1;
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counter <= counter - 1'b1;
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assign wait_for_counter = (counter != 4'h0);
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assign wait_for_counter = (counter != 4'h0);
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//---------------------------------------------------
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//---------------------------------------------------
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// outputs
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// outputs
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generate
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generate
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if( DW == 16 )
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if( DW == 16 )
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begin
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begin
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assign async_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
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assign async_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
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assign async_addr = wb_lo_adr_o[AW:1];
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assign async_addr = wb_lo_adr_o[AW:1];
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assign wb_lo_dat_i = bypass_mux;
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assign wb_lo_dat_i = bypass_mux;
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end
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end
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else
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else
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begin
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begin
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assign async_dq = wb_lo_we_o ? wb_lo_dat_o : 8'hz;
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assign async_dq = wb_lo_we_o ? wb_lo_dat_o : 8'hz;
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assign async_addr = wb_lo_adr_o[(AW-1):0];
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assign async_addr = wb_lo_adr_o[(AW-1):0];
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assign wb_lo_dat_i = {8'h00, bypass_mux};
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assign wb_lo_dat_i = {8'h00, bypass_mux};
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end
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end
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endgenerate
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endgenerate
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assign async_ub_n = ~wb_lo_sel_o[1];
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assign async_ub_n = ~wb_lo_sel_o[1];
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assign async_lb_n = ~wb_lo_sel_o[0];
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assign async_lb_n = ~wb_lo_sel_o[0];
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assign async_we_n = ~( wb_lo_we_o & assert_op );
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assign async_we_n = ~( wb_lo_we_o & assert_op );
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assign async_ce_n = ~( wb_stb_i & wb_cyc_i & assert_ce );
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assign async_ce_n = ~( wb_stb_i & wb_cyc_i & assert_ce );
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assign async_oe_n = ~( ~wb_lo_we_o & assert_op );
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assign async_oe_n = ~( ~wb_lo_we_o & assert_op );
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endmodule
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endmodule
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