//////////////////////////////////////////////////////////////////////
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// --------------------------------------------------------------------
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//// ////
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//
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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// --------------------------------------------------------------------
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module wb_size_bridge(
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module wb_size_bridge(
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input wb_hi_clk_i,
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input wb_hi_clk_i,
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input wb_hi_rst_i,
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input wb_hi_rst_i,
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output [31:0] wb_hi_dat_o,
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output [31:0] wb_hi_dat_o,
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input [31:0] wb_hi_dat_i,
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input [31:0] wb_hi_dat_i,
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input [31:0] wb_hi_adr_i,
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input [31:0] wb_hi_adr_i,
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input wb_hi_cyc_i,
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input wb_hi_cyc_i,
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input wb_hi_stb_i,
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input wb_hi_stb_i,
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input wb_hi_we_i,
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input wb_hi_we_i,
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input [3:0] wb_hi_sel_i,
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input [3:0] wb_hi_sel_i,
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output wb_hi_ack_o,
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output wb_hi_ack_o,
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output wb_hi_err_o,
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output wb_hi_err_o,
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output wb_hi_rty_o,
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output wb_hi_rty_o,
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output wb_lo_clk_o,
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output wb_lo_clk_o,
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output wb_lo_rst_o,
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output wb_lo_rst_o,
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input [15:0] wb_lo_dat_i,
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input [15:0] wb_lo_dat_i,
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output [15:0] wb_lo_dat_o,
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output [15:0] wb_lo_dat_o,
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output [31:0] wb_lo_adr_o,
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output [31:0] wb_lo_adr_o,
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output wb_lo_cyc_o,
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output wb_lo_cyc_o,
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output wb_lo_stb_o,
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output wb_lo_stb_o,
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output wb_lo_we_o,
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output wb_lo_we_o,
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output [1:0] wb_lo_sel_o,
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output [1:0] wb_lo_sel_o,
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input wb_lo_ack_i,
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input wb_lo_ack_i,
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input wb_lo_err_i,
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input wb_lo_err_i,
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input wb_lo_rty_i,
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input wb_lo_rty_i,
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input lo_byte_if_i
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input lo_byte_if_i
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine encoder
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// state machine encoder
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reg [2:0] state_enc;
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reg [2:0] state_enc;
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wire state_enc_3_more_chunks = state_enc[2];
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wire state_enc_3_more_chunks = state_enc[2];
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wire state_enc_1_more_chunks = state_enc[1];
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wire state_enc_1_more_chunks = state_enc[1];
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wire state_enc_error = state_enc[0];
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wire state_enc_error = state_enc[0];
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always @(*)
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always @(*)
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case( { lo_byte_if_i, wb_hi_sel_i } )
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case( { lo_byte_if_i, wb_hi_sel_i } )
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5'b1_0001: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_0001: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_0010: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_0010: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_0100: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_0100: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_1000: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_1000: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b1_0011: state_enc = { 1'b0, 1'b1, 1'b0 };
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5'b1_0011: state_enc = { 1'b0, 1'b1, 1'b0 };
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5'b1_1100: state_enc = { 1'b0, 1'b1, 1'b0 };
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5'b1_1100: state_enc = { 1'b0, 1'b1, 1'b0 };
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5'b1_1111: state_enc = { 1'b1, 1'b0, 1'b0 };
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5'b1_1111: state_enc = { 1'b1, 1'b0, 1'b0 };
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5'b0_0001: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0001: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0010: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0010: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0100: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0100: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_1000: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_1000: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0011: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_0011: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_1100: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_1100: state_enc = { 1'b0, 1'b0, 1'b0 };
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5'b0_1111: state_enc = { 1'b0, 1'b1, 1'b0 };
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5'b0_1111: state_enc = { 1'b0, 1'b1, 1'b0 };
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default: state_enc = { 1'b0, 1'b0, 1'b1 };
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default: state_enc = { 1'b0, 1'b0, 1'b1 };
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine
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// state machine
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localparam STATE_DONT_CARE = 4'b????;
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localparam STATE_DONT_CARE = 4'b????;
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localparam STATE_PASS_THROUGH = 4'b0001;
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localparam STATE_PASS_THROUGH = 4'b0001;
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localparam STATE_1_MORE_CHUNK = 4'b0010;
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localparam STATE_1_MORE_CHUNK = 4'b0010;
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localparam STATE_2_MORE_CHUNK = 4'b0100;
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localparam STATE_2_MORE_CHUNK = 4'b0100;
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localparam STATE_3_MORE_CHUNK = 4'b1000;
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localparam STATE_3_MORE_CHUNK = 4'b1000;
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reg [3:0] state;
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reg [3:0] state;
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reg [3:0] next_state;
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reg [3:0] next_state;
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always @(posedge wb_hi_clk_i or posedge wb_hi_rst_i)
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always @(posedge wb_hi_clk_i or posedge wb_hi_rst_i)
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if(wb_hi_rst_i)
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if(wb_hi_rst_i)
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state <= STATE_PASS_THROUGH;
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state <= STATE_PASS_THROUGH;
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else
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else
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state <= next_state;
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state <= next_state;
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always @(*)
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always @(*)
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case( state )
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case( state )
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STATE_PASS_THROUGH: if( state_enc_1_more_chunks & wb_lo_ack_i & wb_hi_stb_i & wb_hi_cyc_i )
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STATE_PASS_THROUGH: if( state_enc_1_more_chunks & wb_lo_ack_i & wb_hi_stb_i & wb_hi_cyc_i )
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next_state = STATE_1_MORE_CHUNK;
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next_state = STATE_1_MORE_CHUNK;
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else if( state_enc_3_more_chunks & wb_lo_ack_i & wb_hi_stb_i & wb_hi_cyc_i )
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else if( state_enc_3_more_chunks & wb_lo_ack_i & wb_hi_stb_i & wb_hi_cyc_i )
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next_state = STATE_3_MORE_CHUNK;
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next_state = STATE_3_MORE_CHUNK;
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else
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else
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next_state = STATE_PASS_THROUGH;
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next_state = STATE_PASS_THROUGH;
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STATE_3_MORE_CHUNK: if( wb_lo_ack_i )
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STATE_3_MORE_CHUNK: if( wb_lo_ack_i )
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next_state = STATE_2_MORE_CHUNK;
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next_state = STATE_2_MORE_CHUNK;
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else
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else
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next_state = STATE_3_MORE_CHUNK;
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next_state = STATE_3_MORE_CHUNK;
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STATE_2_MORE_CHUNK: if( wb_lo_ack_i )
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STATE_2_MORE_CHUNK: if( wb_lo_ack_i )
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next_state = STATE_1_MORE_CHUNK;
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next_state = STATE_1_MORE_CHUNK;
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else
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else
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next_state = STATE_2_MORE_CHUNK;
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next_state = STATE_2_MORE_CHUNK;
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STATE_1_MORE_CHUNK: if( wb_lo_ack_i )
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STATE_1_MORE_CHUNK: if( wb_lo_ack_i )
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next_state = STATE_PASS_THROUGH;
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next_state = STATE_PASS_THROUGH;
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else
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else
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next_state = STATE_1_MORE_CHUNK;
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next_state = STATE_1_MORE_CHUNK;
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default: next_state = STATE_PASS_THROUGH;
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default: next_state = STATE_PASS_THROUGH;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// byte enable & select
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// byte enable & select
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reg [3:0] byte_enable;
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reg [3:0] byte_enable;
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localparam BYTE_N_ENABLED = 4'b0000;
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localparam BYTE_N_ENABLED = 4'b0000;
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localparam BYTE_0_ENABLED = 4'b0001;
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localparam BYTE_0_ENABLED = 4'b0001;
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localparam BYTE_1_ENABLED = 4'b0010;
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localparam BYTE_1_ENABLED = 4'b0010;
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localparam BYTE_2_ENABLED = 4'b0100;
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localparam BYTE_2_ENABLED = 4'b0100;
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localparam BYTE_3_ENABLED = 4'b1000;
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localparam BYTE_3_ENABLED = 4'b1000;
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reg [1:0] byte_select;
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reg [1:0] byte_select;
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localparam BYTE_0_SELECTED = 2'b00;
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localparam BYTE_0_SELECTED = 2'b00;
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localparam BYTE_1_SELECTED = 2'b01;
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localparam BYTE_1_SELECTED = 2'b01;
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localparam BYTE_2_SELECTED = 2'b10;
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localparam BYTE_2_SELECTED = 2'b10;
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localparam BYTE_3_SELECTED = 2'b11;
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localparam BYTE_3_SELECTED = 2'b11;
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localparam BYTE_X_SELECTED = 2'b??;
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localparam BYTE_X_SELECTED = 2'b??;
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always @(*)
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always @(*)
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casez( { lo_byte_if_i, wb_hi_sel_i, state } )
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casez( { lo_byte_if_i, wb_hi_sel_i, state } )
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{ 1'b1, 4'b0001, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
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{ 1'b1, 4'b0001, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
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{ 1'b1, 4'b0010, STATE_PASS_THROUGH }: byte_enable = BYTE_1_ENABLED;
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{ 1'b1, 4'b0010, STATE_PASS_THROUGH }: byte_enable = BYTE_1_ENABLED;
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{ 1'b1, 4'b0100, STATE_PASS_THROUGH }: byte_enable = BYTE_2_ENABLED;
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{ 1'b1, 4'b0100, STATE_PASS_THROUGH }: byte_enable = BYTE_2_ENABLED;
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{ 1'b1, 4'b1000, STATE_PASS_THROUGH }: byte_enable = BYTE_3_ENABLED;
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{ 1'b1, 4'b1000, STATE_PASS_THROUGH }: byte_enable = BYTE_3_ENABLED;
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{ 1'b1, 4'b0011, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
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{ 1'b1, 4'b0011, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
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{ 1'b1, 4'b0011, STATE_1_MORE_CHUNK }: byte_enable = BYTE_1_ENABLED;
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{ 1'b1, 4'b0011, STATE_1_MORE_CHUNK }: byte_enable = BYTE_1_ENABLED;
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{ 1'b1, 4'b1100, STATE_PASS_THROUGH }: byte_enable = BYTE_2_ENABLED;
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{ 1'b1, 4'b1100, STATE_PASS_THROUGH }: byte_enable = BYTE_2_ENABLED;
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{ 1'b1, 4'b1100, STATE_1_MORE_CHUNK }: byte_enable = BYTE_3_ENABLED;
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{ 1'b1, 4'b1100, STATE_1_MORE_CHUNK }: byte_enable = BYTE_3_ENABLED;
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{ 1'b1, 4'b1111, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
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{ 1'b1, 4'b1111, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
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{ 1'b1, 4'b1111, STATE_3_MORE_CHUNK }: byte_enable = BYTE_1_ENABLED;
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{ 1'b1, 4'b1111, STATE_3_MORE_CHUNK }: byte_enable = BYTE_1_ENABLED;
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{ 1'b1, 4'b1111, STATE_2_MORE_CHUNK }: byte_enable = BYTE_2_ENABLED;
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{ 1'b1, 4'b1111, STATE_2_MORE_CHUNK }: byte_enable = BYTE_2_ENABLED;
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{ 1'b1, 4'b1111, STATE_1_MORE_CHUNK }: byte_enable = BYTE_3_ENABLED;
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{ 1'b1, 4'b1111, STATE_1_MORE_CHUNK }: byte_enable = BYTE_3_ENABLED;
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{ 1'b0, 4'b????, STATE_DONT_CARE }: byte_enable = BYTE_N_ENABLED;
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{ 1'b0, 4'b????, STATE_DONT_CARE }: byte_enable = BYTE_N_ENABLED;
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default: byte_enable = BYTE_N_ENABLED;
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default: byte_enable = BYTE_N_ENABLED;
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endcase
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endcase
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always @(*)
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always @(*)
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case( byte_enable )
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case( byte_enable )
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BYTE_0_ENABLED: byte_select = BYTE_0_SELECTED;
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BYTE_0_ENABLED: byte_select = BYTE_0_SELECTED;
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BYTE_1_ENABLED: byte_select = BYTE_1_SELECTED;
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BYTE_1_ENABLED: byte_select = BYTE_1_SELECTED;
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BYTE_2_ENABLED: byte_select = BYTE_2_SELECTED;
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BYTE_2_ENABLED: byte_select = BYTE_2_SELECTED;
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BYTE_3_ENABLED: byte_select = BYTE_3_SELECTED;
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BYTE_3_ENABLED: byte_select = BYTE_3_SELECTED;
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default: byte_select = 2'bxx;
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default: byte_select = 2'bxx;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// word enable & select
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// word enable & select
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reg [1:0] word_enable;
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reg [1:0] word_enable;
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localparam WORD_N_ENABLED = 2'b00;
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localparam WORD_N_ENABLED = 2'b00;
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localparam WORD_0_ENABLED = 2'b01;
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localparam WORD_0_ENABLED = 2'b01;
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localparam WORD_1_ENABLED = 2'b10;
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localparam WORD_1_ENABLED = 2'b10;
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reg word_select;
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reg word_select;
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localparam WORD_0_SELECTED = 1'b0;
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localparam WORD_0_SELECTED = 1'b0;
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localparam WORD_1_SELECTED = 1'b1;
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localparam WORD_1_SELECTED = 1'b1;
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localparam WORD_X_SELECTED = 1'b?;
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localparam WORD_X_SELECTED = 1'b?;
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always @(*)
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always @(*)
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casez( { lo_byte_if_i, wb_hi_sel_i, state } )
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casez( { lo_byte_if_i, wb_hi_sel_i, state } )
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{ 1'b0, 4'b0011, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b0011, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b1100, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b1100, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b0001, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b0001, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b0010, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b0010, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b0100, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b0100, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b1000, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b1000, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b1111, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b1111, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
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{ 1'b0, 4'b1111, STATE_1_MORE_CHUNK }: word_enable = WORD_1_ENABLED;
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{ 1'b0, 4'b1111, STATE_1_MORE_CHUNK }: word_enable = WORD_1_ENABLED;
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{ 1'b1, 4'b????, STATE_DONT_CARE }: word_enable = WORD_N_ENABLED;
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{ 1'b1, 4'b????, STATE_DONT_CARE }: word_enable = WORD_N_ENABLED;
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default: word_enable = WORD_N_ENABLED;
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default: word_enable = WORD_N_ENABLED;
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endcase
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endcase
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always @(*)
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always @(*)
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case( word_enable )
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case( word_enable )
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WORD_0_ENABLED: word_select = WORD_0_SELECTED;
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WORD_0_ENABLED: word_select = WORD_0_SELECTED;
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WORD_1_ENABLED: word_select = WORD_1_SELECTED;
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WORD_1_ENABLED: word_select = WORD_1_SELECTED;
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default: word_select = 1'bx;
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default: word_select = 1'bx;
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// write mux
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// write mux
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reg [1:0] byte_write_mux_enc;
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reg [1:0] byte_write_mux_enc;
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always @(*)
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always @(*)
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casez( {lo_byte_if_i, byte_select, word_select} )
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casez( {lo_byte_if_i, byte_select, word_select} )
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{ 1'b1, BYTE_0_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b00;
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{ 1'b1, BYTE_0_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b00;
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{ 1'b1, BYTE_1_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b01;
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{ 1'b1, BYTE_1_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b01;
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{ 1'b1, BYTE_2_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b10;
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{ 1'b1, BYTE_2_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b10;
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{ 1'b1, BYTE_3_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b11;
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{ 1'b1, BYTE_3_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b11;
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{ 1'b0, BYTE_X_SELECTED, WORD_0_SELECTED }: byte_write_mux_enc = 2'b00;
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{ 1'b0, BYTE_X_SELECTED, WORD_0_SELECTED }: byte_write_mux_enc = 2'b00;
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{ 1'b0, BYTE_X_SELECTED, WORD_1_SELECTED }: byte_write_mux_enc = 2'b10;
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{ 1'b0, BYTE_X_SELECTED, WORD_1_SELECTED }: byte_write_mux_enc = 2'b10;
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default: byte_write_mux_enc = 2'b00;
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default: byte_write_mux_enc = 2'b00;
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endcase
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endcase
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reg [7:0] byte_write_mux;
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reg [7:0] byte_write_mux;
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always @(*)
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always @(*)
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case( byte_write_mux_enc )
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case( byte_write_mux_enc )
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2'b00: byte_write_mux = wb_hi_dat_i[7:0];
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2'b00: byte_write_mux = wb_hi_dat_i[7:0];
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2'b01: byte_write_mux = wb_hi_dat_i[15:8];
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2'b01: byte_write_mux = wb_hi_dat_i[15:8];
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2'b10: byte_write_mux = wb_hi_dat_i[23:16];
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2'b10: byte_write_mux = wb_hi_dat_i[23:16];
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2'b11: byte_write_mux = wb_hi_dat_i[31:24];
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2'b11: byte_write_mux = wb_hi_dat_i[31:24];
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default: byte_write_mux = wb_hi_dat_i[7:0];
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default: byte_write_mux = wb_hi_dat_i[7:0];
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endcase
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endcase
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reg [7:0] word_write_mux;
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reg [7:0] word_write_mux;
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|
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always @(*)
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always @(*)
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case( word_select )
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case( word_select )
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WORD_0_SELECTED: word_write_mux = wb_hi_dat_i[15:8];
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WORD_0_SELECTED: word_write_mux = wb_hi_dat_i[15:8];
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WORD_1_SELECTED: word_write_mux = wb_hi_dat_i[31:24];
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WORD_1_SELECTED: word_write_mux = wb_hi_dat_i[31:24];
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default: word_write_mux = wb_hi_dat_i[15:8];
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default: word_write_mux = wb_hi_dat_i[15:8];
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endcase
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endcase
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// read buffer & bypass mux
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// read buffer & bypass mux
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|
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// low side input mux
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// low side input mux
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wire [7:0] read_word_lo_mux = wb_lo_dat_i[7:0];
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wire [7:0] read_word_lo_mux = wb_lo_dat_i[7:0];
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wire [7:0] read_word_hi_mux = ( word_enable[0] | word_enable[1] )? wb_lo_dat_i[15:8] : wb_lo_dat_i[7:0];
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wire [7:0] read_word_hi_mux = ( word_enable[0] | word_enable[1] )? wb_lo_dat_i[15:8] : wb_lo_dat_i[7:0];
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|
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reg [31:0] read_buffer;
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reg [31:0] read_buffer;
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|
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wire read_buffer_0_enable = (byte_enable[0] | word_enable[0]) & ~wb_hi_we_i;
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wire read_buffer_0_enable = (byte_enable[0] | word_enable[0]) & ~wb_hi_we_i;
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wire read_buffer_1_enable = (byte_enable[1] | word_enable[0]) & ~wb_hi_we_i;
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wire read_buffer_1_enable = (byte_enable[1] | word_enable[0]) & ~wb_hi_we_i;
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wire read_buffer_2_enable = (byte_enable[2] | word_enable[1]) & ~wb_hi_we_i;
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wire read_buffer_2_enable = (byte_enable[2] | word_enable[1]) & ~wb_hi_we_i;
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wire read_buffer_3_enable = (byte_enable[3] | word_enable[1]) & ~wb_hi_we_i;
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wire read_buffer_3_enable = (byte_enable[3] | word_enable[1]) & ~wb_hi_we_i;
|
|
|
always @(posedge wb_hi_clk_i)
|
always @(posedge wb_hi_clk_i)
|
if( read_buffer_0_enable )
|
if( read_buffer_0_enable )
|
read_buffer[7:0] <= read_word_lo_mux;
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read_buffer[7:0] <= read_word_lo_mux;
|
|
|
always @(posedge wb_hi_clk_i)
|
always @(posedge wb_hi_clk_i)
|
if( read_buffer_1_enable )
|
if( read_buffer_1_enable )
|
read_buffer[15:8] <= read_word_hi_mux;
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read_buffer[15:8] <= read_word_hi_mux;
|
|
|
always @(posedge wb_hi_clk_i)
|
always @(posedge wb_hi_clk_i)
|
if( read_buffer_2_enable )
|
if( read_buffer_2_enable )
|
read_buffer[23:16] <= read_word_lo_mux;
|
read_buffer[23:16] <= read_word_lo_mux;
|
|
|
always @(posedge wb_hi_clk_i)
|
always @(posedge wb_hi_clk_i)
|
if( read_buffer_3_enable )
|
if( read_buffer_3_enable )
|
read_buffer[31:24] <= read_word_hi_mux;
|
read_buffer[31:24] <= read_word_hi_mux;
|
|
|
wire [31:0] read_buffer_mux;
|
wire [31:0] read_buffer_mux;
|
|
|
// bypass read mux
|
// bypass read mux
|
assign read_buffer_mux[7:0] = read_buffer_0_enable ? read_word_lo_mux : read_buffer[7:0];
|
assign read_buffer_mux[7:0] = read_buffer_0_enable ? read_word_lo_mux : read_buffer[7:0];
|
assign read_buffer_mux[15:8] = read_buffer_1_enable ? read_word_hi_mux : read_buffer[15:8];
|
assign read_buffer_mux[15:8] = read_buffer_1_enable ? read_word_hi_mux : read_buffer[15:8];
|
assign read_buffer_mux[23:16] = read_buffer_2_enable ? read_word_lo_mux : read_buffer[23:16];
|
assign read_buffer_mux[23:16] = read_buffer_2_enable ? read_word_lo_mux : read_buffer[23:16];
|
assign read_buffer_mux[31:24] = read_buffer_3_enable ? read_word_hi_mux : read_buffer[31:24];
|
assign read_buffer_mux[31:24] = read_buffer_3_enable ? read_word_hi_mux : read_buffer[31:24];
|
|
|
|
|
// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
// misc logic
|
// misc logic
|
wire [1:0] lo_addr_bits;
|
wire [1:0] lo_addr_bits;
|
assign lo_addr_bits = ( |byte_enable ) ? byte_select : { word_select, 1'b0 };
|
assign lo_addr_bits = ( |byte_enable ) ? byte_select : { word_select, 1'b0 };
|
|
|
wire all_done = ( ~(|state_enc) & (state == STATE_PASS_THROUGH) ) |
|
wire all_done = ( ~(|state_enc) & (state == STATE_PASS_THROUGH) ) |
|
( |state_enc & (state == STATE_1_MORE_CHUNK) );
|
( |state_enc & (state == STATE_1_MORE_CHUNK) );
|
|
|
reg [1:0] wb_lo_sel_r;
|
reg [1:0] wb_lo_sel_r;
|
always @(*)
|
always @(*)
|
casez( { lo_byte_if_i, wb_hi_sel_i, state } )
|
casez( { lo_byte_if_i, wb_hi_sel_i, state } )
|
{ 1'b0, 4'b0001, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b01;
|
{ 1'b0, 4'b0001, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b01;
|
{ 1'b0, 4'b0010, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b10;
|
{ 1'b0, 4'b0010, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b10;
|
{ 1'b0, 4'b0100, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b01;
|
{ 1'b0, 4'b0100, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b01;
|
{ 1'b0, 4'b1000, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b10;
|
{ 1'b0, 4'b1000, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b10;
|
default: wb_lo_sel_r = 2'b11;
|
default: wb_lo_sel_r = 2'b11;
|
endcase
|
endcase
|
|
|
|
|
|
|
// --------------------------------------------------------------------
|
// --------------------------------------------------------------------
|
// output port assignments
|
// output port assignments
|
assign wb_hi_dat_o = read_buffer_mux;
|
assign wb_hi_dat_o = read_buffer_mux;
|
assign wb_hi_err_o = (wb_lo_err_i | state_enc_error) & wb_hi_stb_i & wb_hi_cyc_i;
|
assign wb_hi_err_o = (wb_lo_err_i | state_enc_error) & wb_hi_stb_i & wb_hi_cyc_i;
|
assign wb_hi_rty_o = wb_lo_rty_i;
|
assign wb_hi_rty_o = wb_lo_rty_i;
|
assign wb_hi_ack_o = all_done & wb_hi_stb_i & wb_hi_cyc_i & wb_lo_ack_i;
|
assign wb_hi_ack_o = all_done & wb_hi_stb_i & wb_hi_cyc_i & wb_lo_ack_i;
|
|
|
assign wb_lo_adr_o = { wb_hi_adr_i[31:2], lo_addr_bits };
|
assign wb_lo_adr_o = { wb_hi_adr_i[31:2], lo_addr_bits };
|
assign wb_lo_clk_o = wb_hi_clk_i;
|
assign wb_lo_clk_o = wb_hi_clk_i;
|
assign wb_lo_rst_o = wb_hi_rst_i;
|
assign wb_lo_rst_o = wb_hi_rst_i;
|
assign wb_lo_cyc_o = wb_hi_cyc_i;
|
assign wb_lo_cyc_o = wb_hi_cyc_i;
|
assign wb_lo_stb_o = wb_hi_stb_i;
|
assign wb_lo_stb_o = wb_hi_stb_i;
|
assign wb_lo_we_o = wb_hi_we_i & wb_hi_stb_i & wb_hi_cyc_i;
|
assign wb_lo_we_o = wb_hi_we_i & wb_hi_stb_i & wb_hi_cyc_i;
|
assign wb_lo_dat_o = {word_write_mux, byte_write_mux};
|
assign wb_lo_dat_o = {word_write_mux, byte_write_mux};
|
assign wb_lo_sel_o = wb_lo_sel_r;
|
assign wb_lo_sel_o = wb_lo_sel_r;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|