///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// WISHBONE rev.B2 Wishbone Master model ////
|
//// WISHBONE rev.B2 Wishbone Master model ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author: Richard Herveille ////
|
//// Author: Richard Herveille ////
|
//// richard@asics.ws ////
|
//// richard@asics.ws ////
|
//// www.asics.ws ////
|
//// www.asics.ws ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
|
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
|
//// ////
|
//// ////
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Richard Herveille ////
|
//// Copyright (C) 2001 Richard Herveille ////
|
//// richard@asics.ws ////
|
//// richard@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// ////
|
//// ////
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
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|
|
|
|
`timescale 1ns/10ps
|
`timescale 1ns/10ps
|
|
|
|
|
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
|
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
|
|
|
//
|
//
|
// parameters
|
// parameters
|
//
|
//
|
parameter dwidth = 32;
|
parameter dwidth = 32;
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parameter awidth = 32;
|
parameter awidth = 32;
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|
|
parameter log_level = 3;
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parameter log_level = 3;
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|
|
//
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//
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// inputs & outputs
|
// inputs & outputs
|
//
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//
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input clk, rst;
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input clk, rst;
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output [awidth -1:0] adr;
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output [awidth -1:0] adr;
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input [dwidth -1:0] din;
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input [dwidth -1:0] din;
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output [dwidth -1:0] dout;
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output [dwidth -1:0] dout;
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output cyc, stb;
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output cyc, stb;
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output we;
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output we;
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output [dwidth/8 -1:0] sel;
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output [dwidth/8 -1:0] sel;
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input ack, err, rty;
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input ack, err, rty;
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|
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//
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//
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// variables
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// variables
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//
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//
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reg [awidth -1:0] adr;
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reg [awidth -1:0] adr;
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reg [dwidth -1:0] dout;
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reg [dwidth -1:0] dout;
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reg cyc, stb;
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reg cyc, stb;
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reg we;
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reg we;
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reg [dwidth/8 -1:0] sel;
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reg [dwidth/8 -1:0] sel;
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|
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reg [dwidth -1:0] q;
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reg [dwidth -1:0] q;
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|
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integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
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integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
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|
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|
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//
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//
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// module body
|
// module body
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//
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//
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|
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// check ack, err and rty assertion
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// check ack, err and rty assertion
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always@(ack or err or rty)
|
always@(ack or err or rty)
|
begin
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begin
|
case ({ack, err, rty})
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case ({ack, err, rty})
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// ok-states
|
// ok-states
|
// 3'b000: // none asserted
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// 3'b000: // none asserted
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// 3'b001: // only rty asserted
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// 3'b001: // only rty asserted
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// 3'b010: // only err asserted
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// 3'b010: // only err asserted
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// 3'b100: // only ack asserted
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// 3'b100: // only ack asserted
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|
|
// fault-states
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// fault-states
|
3'b011: // oops, err and rty
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3'b011: // oops, err and rty
|
begin
|
begin
|
err_wb_cnt = err_wb_cnt +1;
|
err_wb_cnt = err_wb_cnt +1;
|
$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
|
$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
|
end
|
end
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3'b101: // oops, ack and rty
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3'b101: // oops, ack and rty
|
begin
|
begin
|
err_wb_cnt = err_wb_cnt +1;
|
err_wb_cnt = err_wb_cnt +1;
|
$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
|
$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
|
end
|
end
|
3'b110: // oops, ack and err
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3'b110: // oops, ack and err
|
begin
|
begin
|
err_wb_cnt = err_wb_cnt +1;
|
err_wb_cnt = err_wb_cnt +1;
|
$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
|
$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
|
end
|
end
|
3'b111: // oops, ack, err and rty
|
3'b111: // oops, ack, err and rty
|
begin
|
begin
|
err_wb_cnt = err_wb_cnt +1;
|
err_wb_cnt = err_wb_cnt +1;
|
$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
|
$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
|
end
|
end
|
endcase
|
endcase
|
|
|
if (err_wb_cnt > err_watchdog)
|
if (err_wb_cnt > err_watchdog)
|
begin
|
begin
|
$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
|
$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
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|
|
// initial settings
|
// initial settings
|
initial
|
initial
|
begin
|
begin
|
//adr = 32'hxxxx_xxxx;
|
//adr = 32'hxxxx_xxxx;
|
//adr = 0;
|
//adr = 0;
|
adr = {awidth{1'bx}};
|
adr = {awidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
dout = {dwidth{1'bx}};
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cyc = 1'b0;
|
cyc = 1'b0;
|
stb = 1'bx;
|
stb = 1'bx;
|
we = 1'hx;
|
we = 1'hx;
|
sel = {dwidth/8{1'bx}};
|
sel = {dwidth/8{1'bx}};
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|
|
err_tot_cnt = 0;
|
err_tot_cnt = 0;
|
err_cur_cnt = 0;
|
err_cur_cnt = 0;
|
err_wb_cnt = 0;
|
err_wb_cnt = 0;
|
err_watchdog = 3;
|
err_watchdog = 3;
|
|
|
#1;
|
#1;
|
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
|
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
|
end
|
end
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|
|
|
|
////////////////////////////
|
////////////////////////////
|
//
|
//
|
// Wishbone write cycle
|
// Wishbone write cycle
|
//
|
//
|
|
|
task wb_write;
|
task wb_write;
|
input delay;
|
input delay;
|
integer delay;
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integer delay;
|
input stb_delay;
|
input stb_delay;
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integer stb_delay;
|
integer stb_delay;
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|
|
input [awidth -1:0] a;
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input [awidth -1:0] a;
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input [dwidth -1:0] d;
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input [dwidth -1:0] d;
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|
|
begin
|
begin
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|
|
if( log_level > 2 )
|
if( log_level > 2 )
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$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
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$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
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|
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// wait initial delay
|
// wait initial delay
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repeat(delay) @(posedge clk);
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repeat(delay) @(posedge clk);
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|
|
#1;
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#1;
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// assert cyc_signal
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// assert cyc_signal
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cyc = 1'b1;
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cyc = 1'b1;
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stb = 1'b0;
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stb = 1'b0;
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|
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// wait for stb_assertion
|
// wait for stb_assertion
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repeat(stb_delay) @(posedge clk);
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repeat(stb_delay) @(posedge clk);
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|
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// assert wishbone signals
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// assert wishbone signals
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adr = a;
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adr = a;
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dout = d;
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dout = d;
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stb = 1'b1;
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stb = 1'b1;
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we = 1'b1;
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we = 1'b1;
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sel = {dwidth/8{1'b1}};
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sel = {dwidth/8{1'b1}};
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@(posedge clk);
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@(posedge clk);
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|
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// wait for acknowledge from slave
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// wait for acknowledge from slave
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// err is treated as normal ack
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// err is treated as normal ack
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// rty is ignored (thus retrying cycle)
|
// rty is ignored (thus retrying cycle)
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while(~ (ack || err)) @(posedge clk);
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while(~ (ack || err)) @(posedge clk);
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|
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// negate wishbone signals
|
// negate wishbone signals
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#1;
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#1;
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cyc = 1'b0;
|
cyc = 1'b0;
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stb = 1'bx;
|
stb = 1'bx;
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adr = {awidth{1'bx}};
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
|
we = 1'hx;
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sel = {dwidth/8{1'bx}};
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sel = {dwidth/8{1'bx}};
|
|
|
end
|
end
|
endtask
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endtask
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|
|
task wb_write_sel;
|
task wb_write_sel;
|
input delay;
|
input delay;
|
integer delay;
|
integer delay;
|
input stb_delay;
|
input stb_delay;
|
integer stb_delay;
|
integer stb_delay;
|
|
|
input [dwidth/8 -1:0] s;
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input [dwidth/8 -1:0] s;
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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input [dwidth -1:0] d;
|
input [dwidth -1:0] d;
|
|
|
begin
|
begin
|
|
|
if( log_level > 2 )
|
if( log_level > 2 )
|
$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
|
$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
|
|
|
// wait initial delay
|
// wait initial delay
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
#1;
|
#1;
|
// assert cyc_signal
|
// assert cyc_signal
|
cyc = 1'b1;
|
cyc = 1'b1;
|
stb = 1'b0;
|
stb = 1'b0;
|
|
|
// wait for stb_assertion
|
// wait for stb_assertion
|
repeat(stb_delay) @(posedge clk);
|
repeat(stb_delay) @(posedge clk);
|
|
|
// assert wishbone signals
|
// assert wishbone signals
|
adr = a;
|
adr = a;
|
dout = d;
|
dout = d;
|
stb = 1'b1;
|
stb = 1'b1;
|
we = 1'b1;
|
we = 1'b1;
|
sel = s;
|
sel = s;
|
@(posedge clk);
|
@(posedge clk);
|
|
|
// wait for acknowledge from slave
|
// wait for acknowledge from slave
|
// err is treated as normal ack
|
// err is treated as normal ack
|
// rty is ignored (thus retrying cycle)
|
// rty is ignored (thus retrying cycle)
|
while(~ (ack || err)) @(posedge clk);
|
while(~ (ack || err)) @(posedge clk);
|
|
|
// negate wishbone signals
|
// negate wishbone signals
|
#1;
|
#1;
|
cyc = 1'b0;
|
cyc = 1'b0;
|
stb = 1'bx;
|
stb = 1'bx;
|
adr = {awidth{1'bx}};
|
adr = {awidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
we = 1'hx;
|
we = 1'hx;
|
sel = {dwidth/8{1'bx}};
|
sel = {dwidth/8{1'bx}};
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////
|
////////////////////////////
|
//
|
//
|
// Wishbone read cycle
|
// Wishbone read cycle
|
//
|
//
|
|
|
task wb_read;
|
task wb_read;
|
input delay;
|
input delay;
|
integer delay;
|
integer delay;
|
input stb_delay;
|
input stb_delay;
|
integer stb_delay;
|
integer stb_delay;
|
|
|
input [awidth -1:0] a;
|
input [awidth -1:0] a;
|
output [dwidth -1:0] d;
|
output [dwidth -1:0] d;
|
|
|
begin
|
begin
|
|
|
// wait initial delay
|
// wait initial delay
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
#1;
|
#1;
|
// assert cyc_signal
|
// assert cyc_signal
|
cyc = 1'b1;
|
cyc = 1'b1;
|
stb = 1'b0;
|
stb = 1'b0;
|
|
|
// wait for stb_assertion
|
// wait for stb_assertion
|
repeat(stb_delay) @(posedge clk);
|
repeat(stb_delay) @(posedge clk);
|
|
|
// assert wishbone signals
|
// assert wishbone signals
|
adr = a;
|
adr = a;
|
dout = {dwidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
stb = 1'b1;
|
stb = 1'b1;
|
we = 1'b0;
|
we = 1'b0;
|
sel = {dwidth/8{1'b1}};
|
sel = {dwidth/8{1'b1}};
|
@(posedge clk);
|
@(posedge clk);
|
|
|
// wait for acknowledge from slave
|
// wait for acknowledge from slave
|
// err is treated as normal ack
|
// err is treated as normal ack
|
// rty is ignored (thus retrying cycle)
|
// rty is ignored (thus retrying cycle)
|
while(~ (ack || err)) @(posedge clk);
|
while(~ (ack || err)) @(posedge clk);
|
|
|
// negate wishbone signals
|
// negate wishbone signals
|
#1;
|
#1;
|
cyc = 1'b0;
|
cyc = 1'b0;
|
stb = 1'bx;
|
stb = 1'bx;
|
adr = {awidth{1'bx}};
|
adr = {awidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
we = 1'hx;
|
we = 1'hx;
|
sel = {dwidth/8{1'bx}};
|
sel = {dwidth/8{1'bx}};
|
d = din;
|
d = din;
|
|
|
if( log_level > 2 )
|
if( log_level > 2 )
|
$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
|
$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
|
end
|
end
|
endtask
|
endtask
|
|
|
task wb_read_sel;
|
task wb_read_sel;
|
input delay;
|
input delay;
|
integer delay;
|
integer delay;
|
input stb_delay;
|
input stb_delay;
|
integer stb_delay;
|
integer stb_delay;
|
|
|
input [dwidth/8 -1:0] s;
|
input [dwidth/8 -1:0] s;
|
input [awidth -1:0] a;
|
input [awidth -1:0] a;
|
output [dwidth -1:0] d;
|
output [dwidth -1:0] d;
|
|
|
begin
|
begin
|
|
|
// wait initial delay
|
// wait initial delay
|
repeat(delay) @(posedge clk);
|
repeat(delay) @(posedge clk);
|
|
|
#1;
|
#1;
|
// assert cyc_signal
|
// assert cyc_signal
|
cyc = 1'b1;
|
cyc = 1'b1;
|
stb = 1'b0;
|
stb = 1'b0;
|
|
|
// wait for stb_assertion
|
// wait for stb_assertion
|
repeat(stb_delay) @(posedge clk);
|
repeat(stb_delay) @(posedge clk);
|
|
|
// assert wishbone signals
|
// assert wishbone signals
|
adr = a;
|
adr = a;
|
dout = {dwidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
stb = 1'b1;
|
stb = 1'b1;
|
we = 1'b0;
|
we = 1'b0;
|
sel = s;
|
sel = s;
|
@(posedge clk);
|
@(posedge clk);
|
|
|
// wait for acknowledge from slave
|
// wait for acknowledge from slave
|
// err is treated as normal ack
|
// err is treated as normal ack
|
// rty is ignored (thus retrying cycle)
|
// rty is ignored (thus retrying cycle)
|
while(~ (ack || err)) @(posedge clk);
|
while(~ (ack || err)) @(posedge clk);
|
|
|
// negate wishbone signals
|
// negate wishbone signals
|
#1;
|
#1;
|
cyc = 1'b0;
|
cyc = 1'b0;
|
stb = 1'bx;
|
stb = 1'bx;
|
adr = {awidth{1'bx}};
|
adr = {awidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
dout = {dwidth{1'bx}};
|
we = 1'hx;
|
we = 1'hx;
|
sel = {dwidth/8{1'bx}};
|
sel = {dwidth/8{1'bx}};
|
d = din;
|
d = din;
|
|
|
if( log_level > 2 )
|
if( log_level > 2 )
|
$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
|
$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////
|
////////////////////////////
|
//
|
//
|
// Wishbone compare cycle
|
// Wishbone compare cycle
|
// read data from location and compare with expected data
|
// read data from location and compare with expected data
|
//
|
//
|
|
|
task wb_cmp;
|
task wb_cmp;
|
input delay;
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input delay;
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integer delay;
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integer delay;
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input stb_delay;
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input stb_delay;
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integer stb_delay;
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integer stb_delay;
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|
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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input [dwidth -1:0] d_exp;
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input [dwidth -1:0] d_exp;
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begin
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begin
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wb_read (delay, stb_delay, a, q);
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wb_read (delay, stb_delay, a, q);
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|
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if (d_exp !== q)
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if (d_exp !== q)
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begin
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begin
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err_tot_cnt = err_tot_cnt +1;
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err_tot_cnt = err_tot_cnt +1;
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err_cur_cnt = err_cur_cnt +1;
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err_cur_cnt = err_cur_cnt +1;
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$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
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$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
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end
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end
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if (err_tot_cnt > err_watchdog)
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if (err_tot_cnt > err_watchdog)
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begin
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begin
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$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
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$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
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$stop;
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$stop;
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end
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end
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end
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end
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endtask
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endtask
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|
|
|
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task wb_cmp_sel;
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task wb_cmp_sel;
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input delay;
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input delay;
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integer delay;
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integer delay;
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input stb_delay;
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input stb_delay;
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integer stb_delay;
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integer stb_delay;
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|
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input [dwidth/8 -1:0] s;
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input [dwidth/8 -1:0] s;
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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input [dwidth -1:0] d_exp;
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input [dwidth -1:0] d_exp;
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|
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begin
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begin
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wb_read_sel (delay, stb_delay, s, a, q);
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wb_read_sel (delay, stb_delay, s, a, q);
|
|
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if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
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if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
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begin
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begin
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err_tot_cnt = err_tot_cnt +1;
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err_tot_cnt = err_tot_cnt +1;
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err_cur_cnt = err_cur_cnt +1;
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err_cur_cnt = err_cur_cnt +1;
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$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
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$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
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end
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end
|
|
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if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
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if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
|
begin
|
begin
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err_tot_cnt = err_tot_cnt +1;
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err_tot_cnt = err_tot_cnt +1;
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err_cur_cnt = err_cur_cnt +1;
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err_cur_cnt = err_cur_cnt +1;
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$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
|
end
|
end
|
|
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if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
|
if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
|
begin
|
begin
|
err_tot_cnt = err_tot_cnt +1;
|
err_tot_cnt = err_tot_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
|
end
|
end
|
|
|
if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
|
if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
|
begin
|
begin
|
err_tot_cnt = err_tot_cnt +1;
|
err_tot_cnt = err_tot_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
|
end
|
end
|
|
|
if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
|
if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
|
begin
|
begin
|
err_tot_cnt = err_tot_cnt +1;
|
err_tot_cnt = err_tot_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
|
end
|
end
|
|
|
if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
|
if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
|
begin
|
begin
|
err_tot_cnt = err_tot_cnt +1;
|
err_tot_cnt = err_tot_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
|
end
|
end
|
|
|
if( (d_exp !== q) & s == 4'b1111 )
|
if( (d_exp !== q) & s == 4'b1111 )
|
begin
|
begin
|
err_tot_cnt = err_tot_cnt +1;
|
err_tot_cnt = err_tot_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
err_cur_cnt = err_cur_cnt +1;
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
|
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
|
end
|
end
|
|
|
case( s )
|
case( s )
|
4'b0001: ;
|
4'b0001: ;
|
4'b0010: ;
|
4'b0010: ;
|
4'b0100: ;
|
4'b0100: ;
|
4'b1000: ;
|
4'b1000: ;
|
4'b0011: ;
|
4'b0011: ;
|
4'b1100: ;
|
4'b1100: ;
|
4'b1111: ;
|
4'b1111: ;
|
default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
|
default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
|
endcase
|
endcase
|
|
|
|
|
if (err_tot_cnt > err_watchdog)
|
if (err_tot_cnt > err_watchdog)
|
begin
|
begin
|
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
|
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
////////////////////////////
|
////////////////////////////
|
//
|
//
|
// Error counter handlers
|
// Error counter handlers
|
//
|
//
|
task set_cur_err_cnt;
|
task set_cur_err_cnt;
|
input value;
|
input value;
|
begin
|
begin
|
err_cur_cnt = value;
|
err_cur_cnt = value;
|
end
|
end
|
endtask
|
endtask
|
|
|
task show_cur_err_cnt;
|
task show_cur_err_cnt;
|
$display("\nCurrent errors detected: %d\n", err_cur_cnt);
|
$display("\nCurrent errors detected: %d\n", err_cur_cnt);
|
endtask
|
endtask
|
|
|
task show_tot_err_cnt;
|
task show_tot_err_cnt;
|
$display("\nTotal errors detected: %d\n", err_tot_cnt);
|
$display("\nTotal errors detected: %d\n", err_tot_cnt);
|
endtask
|
endtask
|
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if( err & (cyc == 1'b1) & (stb == 1'b1) )
|
if( err & (cyc == 1'b1) & (stb == 1'b1) )
|
$display( "!!!- WB Bus Error at time %t. ", $time );
|
$display( "!!!- WB Bus Error at time %t. ", $time );
|
|
|
endmodule
|
endmodule
|
|
|
|
|