// --------------------------------------------------------------------
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//////////////////////////////////////////////////////////////////////
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//
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//// ////
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// --------------------------------------------------------------------
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module tb_top();
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module tb_top();
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parameter CLK_PERIOD = 10;
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parameter CLK_PERIOD = 10;
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reg tb_clk, tb_rst;
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reg tb_clk, tb_rst;
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initial
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initial
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begin
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begin
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tb_clk <= 1'b1;
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tb_clk <= 1'b1;
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tb_rst <= 1'b1;
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tb_rst <= 1'b1;
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#(CLK_PERIOD); #(CLK_PERIOD/3);
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#(CLK_PERIOD); #(CLK_PERIOD/3);
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tb_rst = 1'b0;
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tb_rst = 1'b0;
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end
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end
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always
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always
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#(CLK_PERIOD/2) tb_clk = ~tb_clk;
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#(CLK_PERIOD/2) tb_clk = ~tb_clk;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// tb_dut
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// tb_dut
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tb_dut dut( tb_clk, tb_rst );
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tb_dut dut( tb_clk, tb_rst );
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// insert test below
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// insert test below
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initial
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initial
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begin
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begin
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wait( ~tb_rst );
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wait( ~tb_rst );
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repeat(2) @(posedge tb_clk);
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repeat(2) @(posedge tb_clk);
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// 8 bit if
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// 8 bit if
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$display("\n^^^- testing 8 bit interface\n");
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$display("\n^^^- testing 8 bit interface\n");
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dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988);
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dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc);
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dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc);
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dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef);
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dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef);
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dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
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// 16 bit if
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// 16 bit if
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$display("\n^^^- testing 16 bit interface\n");
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$display("\n^^^- testing 16 bit interface\n");
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dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988);
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dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc);
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dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc);
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dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef);
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dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef);
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dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
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dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
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dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
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// do illegal byte boundary access
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// do illegal byte boundary access
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$display("\n^^^- testing illegal byte boundary access\n");
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$display("\n^^^- testing illegal byte boundary access\n");
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dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx);
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dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx);
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repeat(2) @(posedge tb_clk);
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repeat(2) @(posedge tb_clk);
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$display("\n^^^---------------------------------\n");
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$display("\n^^^---------------------------------\n");
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$display("^^^- Testbench done. %t.\n", $time);
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$display("^^^- Testbench done. %t.\n", $time);
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$stop();
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$stop();
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end
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end
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endmodule
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endmodule
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