library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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use wb_tk.all;
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use wb_tk.all;
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entity wb_arbiter_tb is
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entity wb_arbiter_tb is
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end wb_arbiter_tb;
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end wb_arbiter_tb;
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architecture TB of wb_arbiter_tb is
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architecture TB of wb_arbiter_tb is
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-- Component declaration of the tested unit
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-- Component declaration of the tested unit
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component wb_arbiter is
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component wb_arbiter is
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port (
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port (
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-- clk: in std_logic;
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-- clk: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- interface to master device a
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-- interface to master device a
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a_we_i: in std_logic;
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a_we_i: in std_logic;
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a_stb_i: in std_logic;
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a_stb_i: in std_logic;
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a_cyc_i: in std_logic;
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a_cyc_i: in std_logic;
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a_ack_o: out std_logic;
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a_ack_o: out std_logic;
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a_ack_oi: in std_logic := '-';
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a_ack_oi: in std_logic := '-';
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a_err_o: out std_logic;
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a_err_o: out std_logic;
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a_err_oi: in std_logic := '-';
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a_err_oi: in std_logic := '-';
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a_rty_o: out std_logic;
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a_rty_o: out std_logic;
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a_rty_oi: in std_logic := '-';
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a_rty_oi: in std_logic := '-';
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-- interface to master device b
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-- interface to master device b
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b_we_i: in std_logic;
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b_we_i: in std_logic;
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b_stb_i: in std_logic;
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b_stb_i: in std_logic;
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b_cyc_i: in std_logic;
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b_cyc_i: in std_logic;
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b_ack_o: out std_logic;
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b_ack_o: out std_logic;
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b_ack_oi: in std_logic := '-';
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b_ack_oi: in std_logic := '-';
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b_err_o: out std_logic;
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b_err_o: out std_logic;
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b_err_oi: in std_logic := '-';
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b_err_oi: in std_logic := '-';
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b_rty_o: out std_logic;
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b_rty_o: out std_logic;
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b_rty_oi: in std_logic := '-';
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b_rty_oi: in std_logic := '-';
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-- interface to shared devices
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-- interface to shared devices
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s_we_o: out std_logic;
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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s_stb_o: out std_logic;
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s_cyc_o: out std_logic;
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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-- misc control lines
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-- misc control lines
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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);
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);
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end component;
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end component;
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signal clk_i: std_logic;
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signal clk_i: std_logic;
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signal rst_i: std_logic := '0';
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signal rst_i: std_logic := '0';
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-- interface to master device a
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-- interface to master device a
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signal a_we_i: std_logic;
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signal a_we_i: std_logic;
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signal a_stb_i: std_logic;
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signal a_stb_i: std_logic;
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signal a_cyc_i: std_logic;
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signal a_cyc_i: std_logic;
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signal a_ack_o: std_logic;
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signal a_ack_o: std_logic;
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signal a_ack_oi: std_logic := 'U';
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signal a_ack_oi: std_logic := 'U';
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signal a_err_o: std_logic;
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signal a_err_o: std_logic;
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signal a_err_oi: std_logic := 'U';
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signal a_err_oi: std_logic := 'U';
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signal a_rty_o: std_logic;
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signal a_rty_o: std_logic;
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signal a_rty_oi: std_logic := 'U';
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signal a_rty_oi: std_logic := 'U';
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-- interface to master device b
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-- interface to master device b
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signal b_we_i: std_logic;
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signal b_we_i: std_logic;
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signal b_stb_i: std_logic;
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signal b_stb_i: std_logic;
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signal b_cyc_i: std_logic;
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signal b_cyc_i: std_logic;
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signal b_ack_o: std_logic;
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signal b_ack_o: std_logic;
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signal b_ack_oi: std_logic := 'U';
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signal b_ack_oi: std_logic := 'U';
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signal b_err_o: std_logic;
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signal b_err_o: std_logic;
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signal b_err_oi: std_logic := 'U';
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signal b_err_oi: std_logic := 'U';
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signal b_rty_o: std_logic;
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signal b_rty_o: std_logic;
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signal b_rty_oi: std_logic := 'U';
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signal b_rty_oi: std_logic := 'U';
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-- interface to shared devices
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-- interface to shared devices
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signal s_we_o: std_logic;
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signal s_we_o: std_logic;
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signal s_stb_o: std_logic;
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signal s_stb_o: std_logic;
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signal s_cyc_o: std_logic;
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signal s_cyc_o: std_logic;
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signal s_ack_i: std_logic;
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signal s_ack_i: std_logic;
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signal s_err_i: std_logic := 'U';
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signal s_err_i: std_logic := 'U';
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signal s_rty_i: std_logic := 'U';
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signal s_rty_i: std_logic := 'U';
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signal mux_signal: std_logic; -- 0: select A signals, 1: select B signals
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signal mux_signal: std_logic; -- 0: select A signals, 1: select B signals
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-- misc control lines
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-- misc control lines
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signal priority: std_logic; -- 0: A have priority over B, 1: B have priority over A
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signal priority: std_logic; -- 0: A have priority over B, 1: B have priority over A
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signal start: std_logic := '0';
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signal start: std_logic := '0';
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begin
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begin
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-- Unit Under Test port map
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-- Unit Under Test port map
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UUT : wb_arbiter
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UUT : wb_arbiter
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port map (
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port map (
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rst_i => rst_i,
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rst_i => rst_i,
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-- interface to master device a
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-- interface to master device a
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a_we_i => a_we_i,
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a_we_i => a_we_i,
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a_stb_i => a_stb_i,
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a_stb_i => a_stb_i,
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a_cyc_i => a_cyc_i,
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a_cyc_i => a_cyc_i,
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a_ack_o => a_ack_o,
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a_ack_o => a_ack_o,
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a_ack_oi => a_ack_oi,
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a_ack_oi => a_ack_oi,
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a_err_o => a_err_o,
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a_err_o => a_err_o,
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a_err_oi => a_err_oi,
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a_err_oi => a_err_oi,
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a_rty_o => a_rty_o,
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a_rty_o => a_rty_o,
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a_rty_oi => a_rty_oi,
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a_rty_oi => a_rty_oi,
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-- interface to master device b
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-- interface to master device b
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b_we_i => b_we_i,
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b_we_i => b_we_i,
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b_stb_i => b_stb_i,
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b_stb_i => b_stb_i,
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b_cyc_i => b_cyc_i,
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b_cyc_i => b_cyc_i,
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b_ack_o => b_ack_o,
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b_ack_o => b_ack_o,
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b_ack_oi => b_ack_oi,
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b_ack_oi => b_ack_oi,
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b_err_o => b_err_o,
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b_err_o => b_err_o,
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b_err_oi => b_err_oi,
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b_err_oi => b_err_oi,
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b_rty_o => b_rty_o,
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b_rty_o => b_rty_o,
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b_rty_oi => b_rty_oi,
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b_rty_oi => b_rty_oi,
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-- interface to shared devices
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-- interface to shared devices
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s_we_o => s_we_o,
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s_we_o => s_we_o,
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s_stb_o => s_stb_o,
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s_stb_o => s_stb_o,
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s_cyc_o => s_cyc_o,
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s_cyc_o => s_cyc_o,
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s_ack_i => s_ack_i,
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s_ack_i => s_ack_i,
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s_err_i => s_err_i,
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s_err_i => s_err_i,
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s_rty_i => s_rty_i,
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s_rty_i => s_rty_i,
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mux_signal => mux_signal,
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mux_signal => mux_signal,
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-- misc control lines
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-- misc control lines
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priority => priority
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priority => priority
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);
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);
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-- Reset the machine
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-- Reset the machine
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rst: process is
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rst: process is
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begin
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begin
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rst_i <= '1';
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rst_i <= '1';
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wait for 10ns;
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wait for 10ns;
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rst_i <= '0';
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rst_i <= '0';
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start <= '1';
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start <= '1';
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wait;
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wait;
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end process;
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end process;
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clock: process is
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clock: process is
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begin
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begin
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clk_i <= '0';
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clk_i <= '0';
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wait for 10ns;
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wait for 10ns;
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clk_i <= '1';
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clk_i <= '1';
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wait for 10ns;
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wait for 10ns;
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end process;
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end process;
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-- Simulate a 3WS access time memory
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-- Simulate a 3WS access time memory
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memory: process is
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memory: process is
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begin
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begin
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s_ack_i <= '0';
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s_ack_i <= '0';
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wait until (s_stb_o = '1' and clk_i'EVENT and clk_i = '1');
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wait until (s_stb_o = '1' and clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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s_ack_i <= '1';
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s_ack_i <= '1';
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wait until (clk_i'EVENT and clk_i = '1');
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wait until (clk_i'EVENT and clk_i = '1');
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end process;
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end process;
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-- Generate requests
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-- Generate requests
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a_req: process is
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a_req: process is
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begin
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begin
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a_we_i <= '0';
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a_we_i <= '0';
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a_cyc_i <= '0';
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a_cyc_i <= '0';
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a_stb_i <= '0';
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a_stb_i <= '0';
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wait for 100ns;
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wait for 100ns;
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a_cyc_i <= '1';
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a_cyc_i <= '1';
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a_stb_i <= '1';
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a_stb_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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a_cyc_i <= '0';
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a_cyc_i <= '0';
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a_stb_i <= '0';
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a_stb_i <= '0';
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wait for 20ns;
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wait for 20ns;
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a_cyc_i <= '1';
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a_cyc_i <= '1';
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a_stb_i <= '1';
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a_stb_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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a_cyc_i <= '0';
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a_cyc_i <= '0';
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a_stb_i <= '0';
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a_stb_i <= '0';
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-- Request 4 burst reads
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-- Request 4 burst reads
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wait for 100ns;
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wait for 100ns;
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a_cyc_i <= '1';
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a_cyc_i <= '1';
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a_stb_i <= '1';
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a_stb_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and a_ack_o = '1';
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a_cyc_i <= '0';
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a_cyc_i <= '0';
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a_stb_i <= '0';
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a_stb_i <= '0';
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end process;
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end process;
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b_req: process is
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b_req: process is
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begin
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begin
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b_we_i <= '0';
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b_we_i <= '0';
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b_cyc_i <= '0';
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b_cyc_i <= '0';
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b_stb_i <= '0';
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b_stb_i <= '0';
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wait for 120ns;
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wait for 120ns;
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b_cyc_i <= '1';
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b_cyc_i <= '1';
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b_stb_i <= '1';
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b_stb_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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b_cyc_i <= '0';
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b_cyc_i <= '0';
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b_stb_i <= '0';
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b_stb_i <= '0';
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wait for 30ns;
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wait for 30ns;
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b_cyc_i <= '1';
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b_cyc_i <= '1';
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b_stb_i <= '1';
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b_stb_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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b_cyc_i <= '0';
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b_cyc_i <= '0';
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b_stb_i <= '0';
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b_stb_i <= '0';
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-- Request 4 burst reads
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-- Request 4 burst reads
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wait for 120ns;
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wait for 120ns;
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b_cyc_i <= '1';
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b_cyc_i <= '1';
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b_stb_i <= '1';
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b_stb_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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wait until clk_i'EVENT and clk_i = '1' and b_ack_o = '1';
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b_cyc_i <= '0';
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b_cyc_i <= '0';
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b_stb_i <= '0';
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b_stb_i <= '0';
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end process;
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end process;
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pri: process is
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pri: process is
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begin
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begin
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priority <= '0';
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priority <= '0';
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wait for 500ns;
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wait for 500ns;
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priority <= '1';
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priority <= '1';
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wait for 500ns;
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wait for 500ns;
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end process;
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end process;
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end TB;
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end TB;
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configuration TB_wb_arbiter of wb_arbiter_tb is
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configuration TB_wb_arbiter of wb_arbiter_tb is
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for TB
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for TB
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for UUT : wb_arbiter
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for UUT : wb_arbiter
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use entity wb_arbiter(FPGA);
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use entity wb_arbiter(FPGA);
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end for;
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end for;
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end for;
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end for;
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end TB_wb_arbiter;
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end TB_wb_arbiter;
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