//
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//
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//
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//
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//
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//
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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module
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module
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wb_arm_slave_top
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wb_arm_slave_top
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#(
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#(
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parameter AWIDTH = 8,
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parameter AWIDTH = 32,
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parameter DWIDTH = 32
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parameter DWIDTH = 32
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)
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)
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(
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(
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// -----------------------------
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// -----------------------------
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// AHB interface
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// AHB interface
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input ahb_hclk,
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input ahb_hclk,
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input ahb_hreset,
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input ahb_hreset,
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output [DWIDTH-1:0] ahb_hrdata,
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output [DWIDTH-1:0] ahb_hrdata,
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output [1:0] ahb_hresp,
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output [1:0] ahb_hresp,
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output ahb_hready_out,
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output ahb_hready_out,
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output [15:0] ahb_hsplit,
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output [15:0] ahb_hsplit,
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input [DWIDTH-1:0] ahb_hwdata,
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input [DWIDTH-1:0] ahb_hwdata,
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input [AWIDTH-1:0] ahb_haddr,
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input [AWIDTH-1:0] ahb_haddr,
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input [2:0] ahb_hsize,
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input [2:0] ahb_hsize,
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input ahb_hwrite,
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input ahb_hwrite,
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input [2:0] ahb_hburst,
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input [2:0] ahb_hburst,
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input [1:0] ahb_htrans,
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input [1:0] ahb_htrans,
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input [3:0] ahb_hprot,
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input [3:0] ahb_hprot,
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input ahb_hsel,
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input ahb_hsel,
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input ahb_hready_in,
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input ahb_hready_in,
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// -----------------------------
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// -----------------------------
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// Data WISHBONE interface
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// Data WISHBONE interface
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input wb_ack_i, // normal termination
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input wb_ack_i, // normal termination
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input wb_err_i, // termination w/ error
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input wb_err_i, // termination w/ error
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input wb_rty_i, // termination w/ retry
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input wb_rty_i, // termination w/ retry
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input [DWIDTH-1:0] wb_dat_i, // input data bus
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input [DWIDTH-1:0] wb_dat_i, // input data bus
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output wb_cyc_o, // cycle valid output
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output wb_cyc_o, // cycle valid output
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output [AWIDTH-1:0] wb_adr_o, // address bus outputs
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output [AWIDTH-1:0] wb_adr_o, // address bus outputs
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output wb_stb_o, // strobe output
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output wb_stb_o, // strobe output
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output wb_we_o, // indicates write transfer
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output wb_we_o, // indicates write transfer
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output [3:0] wb_sel_o, // byte select outputs
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output [3:0] wb_sel_o, // byte select outputs
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output [DWIDTH-1:0] wb_dat_o, // output data bus
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output [DWIDTH-1:0] wb_dat_o, // output data bus
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output wb_clk_o, // clock input
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output wb_clk_o, // clock input
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output wb_rst_o // reset input
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output wb_rst_o // reset input
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);
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);
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// -----------------------------
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// -----------------------------
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// ahb_haddr & control flops
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// ahb_haddr & control flops
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wire flop_en = ahb_hready_in & ahb_hsel;
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wire flop_en = ahb_hready_in & ahb_hsel & ~ahb_data_phase;
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reg [AWIDTH-1:0] ahb_haddr_r;
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reg [AWIDTH-1:0] ahb_haddr_r;
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always @ (posedge ahb_hclk)
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always @ (posedge ahb_hclk)
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if ( flop_en )
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if ( flop_en )
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ahb_haddr_r <= ahb_haddr;
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ahb_haddr_r <= ahb_haddr;
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reg [1:0] ahb_htrans_r;
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reg [1:0] ahb_htrans_r;
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always @ (posedge ahb_hclk)
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always @ (posedge ahb_hclk)
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if ( flop_en )
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if ( flop_en )
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ahb_htrans_r <= ahb_htrans;
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ahb_htrans_r <= ahb_htrans;
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reg ahb_hwrite_r;
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reg ahb_hwrite_r;
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always @ (posedge ahb_hclk)
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always @ (posedge ahb_hclk)
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if ( flop_en )
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if ( flop_en )
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ahb_hwrite_r <= ahb_hwrite;
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ahb_hwrite_r <= ahb_hwrite;
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reg [2:0] ahb_hsize_r;
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reg [2:0] ahb_hsize_r;
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always @ (posedge ahb_hclk)
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always @ (posedge ahb_hclk)
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if ( flop_en )
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if ( flop_en )
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ahb_hsize_r <= ahb_hsize;
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ahb_hsize_r <= ahb_hsize;
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reg [2:0] ahb_hburst_r;
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reg [2:0] ahb_hburst_r;
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always @ (posedge ahb_hclk)
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always @ (posedge ahb_hclk)
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if ( flop_en )
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if ( flop_en )
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ahb_hburst_r <= ahb_hburst;
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ahb_hburst_r <= ahb_hburst;
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// -----------------------------
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// -----------------------------
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// wb_arm_phase_fsm
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// wb_arm_phase_fsm
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wire ahb_data_phase;
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wire ahb_data_phase;
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wire fsm_error;
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wire fsm_error;
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wb_arm_phase_fsm i_wb_arm_phase_fsm(
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wb_arm_phase_fsm
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i_wb_arm_phase_fsm(
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.ahb_hclk (ahb_hclk),
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.ahb_hclk (ahb_hclk),
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.ahb_hreset (ahb_hreset),
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.ahb_hreset (ahb_hreset),
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.ahb_hsel (ahb_hsel),
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.ahb_hsel (ahb_hsel),
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.ahb_hready_in (ahb_hready_in),
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.ahb_hready_in (ahb_hready_in),
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.ahb_hready_out (ahb_hready_out),
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.ahb_hready_out (ahb_hready_out),
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.ahb_htrans (ahb_htrans),
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.ahb_data_phase (ahb_data_phase),
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.ahb_data_phase (ahb_data_phase),
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.fsm_error (fsm_error)
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.fsm_error (fsm_error)
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);
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);
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// -----------------------------
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// -----------------------------
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// hresp encoder
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// hresp encoder
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reg [1:0] enc_hresp;
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reg [1:0] enc_hresp;
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always @(*)
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always @(*)
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casez( { ahb_htrans_r, fsm_error } )
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casez( { ahb_htrans_r, fsm_error } )
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{ 2'b??, 1'b1 }: enc_hresp = 2'b01;
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{ 2'b??, 1'b1 }: enc_hresp = 2'b01;
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{ 2'b11, 1'b? }: enc_hresp = 2'b01; // burst not supported yet
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{ 2'b11, 1'b? }: enc_hresp = 2'b01; // burst not supported yet
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default: enc_hresp = 2'b00;
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default: enc_hresp = 2'b00;
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endcase
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endcase
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// -----------------------------
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// -----------------------------
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// wb_sel encoder
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// wb_sel encoder
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reg [3:0] enc_wb_sel;
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reg [3:0] enc_wb_sel;
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always @(*)
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always @(*)
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casez( { ahb_hsize_r, ahb_haddr_r[1:0] } )
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casez( { ahb_hsize_r, ahb_haddr_r[1:0] } )
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{ 3'b010, 2'b?? }: enc_wb_sel = 4'b1111;
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{ 3'b010, 2'b?? }: enc_wb_sel = 4'b1111;
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{ 3'b001, 2'b0? }: enc_wb_sel = 4'b0011;
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{ 3'b001, 2'b0? }: enc_wb_sel = 4'b0011;
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{ 3'b001, 2'b1? }: enc_wb_sel = 4'b1100;
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{ 3'b001, 2'b1? }: enc_wb_sel = 4'b1100;
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{ 3'b000, 2'b00 }: enc_wb_sel = 4'b0001;
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{ 3'b000, 2'b00 }: enc_wb_sel = 4'b0001;
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{ 3'b000, 2'b01 }: enc_wb_sel = 4'b0010;
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{ 3'b000, 2'b01 }: enc_wb_sel = 4'b0010;
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{ 3'b000, 2'b10 }: enc_wb_sel = 4'b0100;
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{ 3'b000, 2'b10 }: enc_wb_sel = 4'b0100;
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{ 3'b000, 2'b11 }: enc_wb_sel = 4'b1000;
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{ 3'b000, 2'b11 }: enc_wb_sel = 4'b1000;
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default: enc_wb_sel = 4'b0000;
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default: enc_wb_sel = 4'b0000;
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endcase
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endcase
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// -----------------------------
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// -----------------------------
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// outputs
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// outputs
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assign ahb_hresp = enc_hresp;
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assign ahb_hresp = enc_hresp;
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assign ahb_hready_out = wb_ack_i;
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assign ahb_hready_out = wb_ack_i;
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assign ahb_hsplit = 0;
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assign ahb_hsplit = 0;
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assign wb_sel_o = enc_wb_sel;
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assign wb_sel_o = enc_wb_sel;
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assign wb_adr_o = ahb_haddr_r;
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assign wb_adr_o = ahb_haddr_r;
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assign ahb_hrdata = wb_dat_i;
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assign ahb_hrdata = wb_dat_i;
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assign wb_we_o = ahb_hwrite_r & ( (ahb_htrans_r != 2'b00) | (ahb_htrans_r != 2'b01) );
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assign wb_we_o = ahb_hwrite_r & ( (ahb_htrans_r != 2'b00) | (ahb_htrans_r != 2'b01) );
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assign wb_cyc_o = ahb_data_phase;
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assign wb_cyc_o = ahb_data_phase;
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assign wb_stb_o = ahb_data_phase;
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assign wb_stb_o = ahb_data_phase;
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assign wb_dat_o = ahb_hwdata;
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assign wb_dat_o = ahb_hwdata;
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assign wb_clk_o = ahb_hclk;
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assign wb_clk_o = ahb_hclk;
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assign wb_rst_o = ~ahb_hreset;
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assign wb_rst_o = ~ahb_hreset;
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endmodule
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endmodule
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