--
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--
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-- Technology mapping library. ALTERA edition.
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-- Technology mapping library. ALTERA edition.
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--
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library exemplar;
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library exemplar;
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use exemplar.exemplar_1164.all;
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use exemplar.exemplar_1164.all;
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package technology is
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package technology is
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function add_one(inp : std_logic_vector) return std_logic_vector;
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function add_one(inp : std_logic_vector) return std_logic_vector;
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function is_zero(inp : std_logic_vector) return boolean;
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function is_zero(inp : std_logic_vector) return boolean;
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function sl(l: std_logic_vector; r: integer) return std_logic_vector;
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function sl(l: std_logic_vector; r: integer) return std_logic_vector;
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-- procedure inc(data : inout std_logic_vector);
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-- procedure inc(data : inout std_logic_vector);
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function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
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function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
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component d_ff is
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component d_ff is
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port ( d : in STD_LOGIC;
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port ( d : in STD_LOGIC;
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clk: in STD_LOGIC;
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clk: in STD_LOGIC;
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ena: in STD_LOGIC := '1';
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ena: in STD_LOGIC := '1';
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clr: in STD_LOGIC := '0';
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clr: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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q : out STD_LOGIC
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q : out STD_LOGIC
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);
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);
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end component;
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end component;
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component fifo is
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component fifo is
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generic (fifo_width : positive;
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generic (fifo_width : positive;
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used_width : positive;
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used_width : positive;
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fifo_depth : positive
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fifo_depth : positive
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);
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);
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port (d_in : in std_logic_vector(fifo_width-1 downto 0);
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port (d_in : in std_logic_vector(fifo_width-1 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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wr : in std_logic;
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wr : in std_logic;
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rd : in std_logic;
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rd : in std_logic;
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a_clr : in std_logic := '0';
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a_clr : in std_logic := '0';
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s_clr : in std_logic := '0';
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s_clr : in std_logic := '0';
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d_out : out std_logic_vector(fifo_width-1 downto 0);
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d_out : out std_logic_vector(fifo_width-1 downto 0);
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used : out std_logic_vector(used_width-1 downto 0);
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used : out std_logic_vector(used_width-1 downto 0);
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full : out std_logic;
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full : out std_logic;
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empty : out std_logic
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empty : out std_logic
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);
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);
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end component;
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end component;
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end technology;
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end technology;
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library exemplar;
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library exemplar;
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use exemplar.exemplar_1164.all;
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use exemplar.exemplar_1164.all;
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package body technology is
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package body technology is
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function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
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function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
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begin
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begin
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return exemplar_1164."+"(op_l, op_r);
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return exemplar_1164."+"(op_l, op_r);
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end;
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end;
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function add_one(inp : std_logic_vector) return std_logic_vector is
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function add_one(inp : std_logic_vector) return std_logic_vector is
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variable one: std_logic_vector(inp'RANGE) := (others => '0');
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variable one: std_logic_vector(inp'RANGE) := (others => '0');
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begin
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begin
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one(0) := '1';
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one(0) := '1';
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return exemplar_1164."+"(inp,one);
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return exemplar_1164."+"(inp,one);
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end;
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end;
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function is_zero(inp : std_logic_vector) return boolean is
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function is_zero(inp : std_logic_vector) return boolean is
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variable zero: std_logic_vector(inp'RANGE) := (others => '0');
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variable zero: std_logic_vector(inp'RANGE) := (others => '0');
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begin
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begin
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return (inp = zero);
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return (inp = zero);
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end;
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end;
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function sl(l: std_logic_vector; r: integer) return std_logic_vector is
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function sl(l: std_logic_vector; r: integer) return std_logic_vector is
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begin
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begin
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return exemplar_1164.sl(l,r);
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return exemplar_1164.sl(l,r);
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end;
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end;
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-- procedure inc(data : inout std_logic_vector) is
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-- procedure inc(data : inout std_logic_vector) is
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-- begin
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-- begin
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-- data := addone(data);
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-- data := addone(data);
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-- end;
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-- end;
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end package body technology;
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end package body technology;
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library exemplar;
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library exemplar;
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use exemplar.exemplar_1164.all;
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use exemplar.exemplar_1164.all;
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library lpm;
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library lpm;
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use lpm.all;
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use lpm.all;
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entity fifo is
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entity fifo is
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generic (fifo_width : positive;
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generic (fifo_width : positive;
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used_width : positive;
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used_width : positive;
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fifo_depth : positive
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fifo_depth : positive
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);
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);
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port (d_in : in std_logic_vector(fifo_width-1 downto 0);
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port (d_in : in std_logic_vector(fifo_width-1 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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wr : in std_logic;
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wr : in std_logic;
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rd : in std_logic;
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rd : in std_logic;
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a_clr : in std_logic := '0';
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a_clr : in std_logic := '0';
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s_clr : in std_logic := '0';
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s_clr : in std_logic := '0';
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d_out : out std_logic_vector(fifo_width-1 downto 0);
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d_out : out std_logic_vector(fifo_width-1 downto 0);
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used : out std_logic_vector(used_width-1 downto 0);
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used : out std_logic_vector(used_width-1 downto 0);
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full : out std_logic;
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full : out std_logic;
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empty : out std_logic
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empty : out std_logic
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);
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);
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end fifo;
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end fifo;
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architecture altera of fifo is
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architecture altera of fifo is
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component lpm_fifo
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component lpm_fifo
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generic (LPM_WIDTH : positive;
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generic (LPM_WIDTH : positive;
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LPM_WIDTHU : positive;
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LPM_WIDTHU : positive;
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LPM_NUMWORDS : positive;
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LPM_NUMWORDS : positive;
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LPM_SHOWAHEAD : string := "OFF";
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LPM_SHOWAHEAD : string := "OFF";
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LPM_TYPE : string := "LPM_FIFO";
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LPM_TYPE : string := "LPM_FIFO";
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LPM_HINT : string := "UNUSED");
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LPM_HINT : string := "UNUSED");
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port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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WRREQ : in std_logic;
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WRREQ : in std_logic;
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RDREQ : in std_logic;
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RDREQ : in std_logic;
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ACLR : in std_logic;
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ACLR : in std_logic;
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SCLR : in std_logic;
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SCLR : in std_logic;
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
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USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
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USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
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FULL : out std_logic;
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FULL : out std_logic;
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EMPTY : out std_logic);
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EMPTY : out std_logic);
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end component;
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end component;
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begin
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begin
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altera_fifo: lpm_fifo
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altera_fifo: lpm_fifo
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generic map (
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generic map (
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LPM_WIDTH => fifo_width,
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LPM_WIDTH => fifo_width,
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LPM_WIDTHU => used_width,
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LPM_WIDTHU => used_width,
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LPM_NUMWORDS => fifo_depth,
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LPM_NUMWORDS => fifo_depth,
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LPM_SHOWAHEAD => "OFF",
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LPM_SHOWAHEAD => "OFF",
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LPM_TYPE => "LPM_FIFO",
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LPM_TYPE => "LPM_FIFO",
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LPM_HINT => "UNUSED"
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LPM_HINT => "UNUSED"
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)
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)
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port map (
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port map (
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DATA => d_in,
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DATA => d_in,
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CLOCK => clk,
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CLOCK => clk,
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WRREQ => wr,
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WRREQ => wr,
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RDREQ => rd,
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RDREQ => rd,
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ACLR => a_clr,
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ACLR => a_clr,
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SCLR => s_clr,
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SCLR => s_clr,
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Q => d_out,
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Q => d_out,
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USEDW => used,
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USEDW => used,
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FULL => full,
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FULL => full,
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EMPTY => empty
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EMPTY => empty
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);
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);
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end altera;
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end altera;
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library altera_exemplar;
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library altera_exemplar;
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use altera_exemplar.all;
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use altera_exemplar.all;
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entity d_ff is
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entity d_ff is
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port ( d : in STD_LOGIC;
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port ( d : in STD_LOGIC;
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clk: in STD_LOGIC;
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clk: in STD_LOGIC;
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ena: in STD_LOGIC := '1';
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ena: in STD_LOGIC := '1';
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clr: in STD_LOGIC := '0';
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clr: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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q : out STD_LOGIC
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q : out STD_LOGIC
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);
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);
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end d_ff;
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end d_ff;
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architecture altera of d_ff is
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architecture altera of d_ff is
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component dffe
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component dffe
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port ( D : in STD_LOGIC;
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port ( D : in STD_LOGIC;
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CLK: in STD_LOGIC;
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CLK: in STD_LOGIC;
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ENA: in STD_LOGIC;
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ENA: in STD_LOGIC;
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CLRN: in STD_LOGIC;
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CLRN: in STD_LOGIC;
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PRN: in STD_LOGIC;
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PRN: in STD_LOGIC;
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Q : out STD_LOGIC);
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Q : out STD_LOGIC);
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end component;
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end component;
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signal clrn,prn: std_logic;
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signal clrn,prn: std_logic;
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begin
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begin
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clrn <= not clr;
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clrn <= not clr;
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prn <= not pre;
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prn <= not pre;
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ff: dffe port map (
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ff: dffe port map (
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D => d,
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D => d,
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CLK => clk,
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CLK => clk,
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ENA => ena,
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ENA => ena,
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CLRN => clrn,
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CLRN => clrn,
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PRN => prn,
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PRN => prn,
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Q => q
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Q => q
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);
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);
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end altera;
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end altera;
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-- Sythetizer library. Contains STD_LOGIC arithmetics
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-- Sythetizer library. Contains STD_LOGIC arithmetics
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