--
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--
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-- File: vga_core.vhd
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-- File: vga_core.vhd
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--
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library work;
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library work;
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--use wb_tk.all;
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--use wb_tk.all;
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use work.wb_tk.all;
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use work.wb_tk.all;
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entity vga_core is
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entity vga_core is
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generic (
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generic (
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-- cannot be overwritten at the moment...
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-- cannot be overwritten at the moment...
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v_mem_width: positive := 16;
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v_mem_width: positive := 16;
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fifo_size: positive := 256;
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fifo_size: positive := 256;
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v_addr_width : positive := 20;
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v_addr_width : positive := 20;
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bus_width: positive := 8
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bus_width: positive := 8
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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clk_en: in std_logic := '1';
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- CPU bus interface
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-- CPU bus interface
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0);
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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cyc_i: in std_logic;
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic;
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ack_oi: in std_logic;
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we_i: in std_logic;
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we_i: in std_logic;
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vmem_stb_i: in std_logic;
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vmem_stb_i: in std_logic;
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reg_stb_i: in std_logic;
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reg_stb_i: in std_logic;
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adr_i: in std_logic_vector (v_addr_width downto 0);
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adr_i: in std_logic_vector (v_addr_width downto 0);
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-- video memory SRAM interface
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-- video memory SRAM interface
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s_data : inout std_logic_vector((v_mem_width-1) downto 0);
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s_data : inout std_logic_vector((v_mem_width-1) downto 0);
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s_addr : out std_logic_vector((v_addr_width-1) downto 0);
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s_addr : out std_logic_vector((v_addr_width-1) downto 0);
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s_oen : out std_logic;
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s_oen : out std_logic;
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s_wrhn : out std_logic;
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s_wrhn : out std_logic;
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s_wrln : out std_logic;
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s_wrln : out std_logic;
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s_cen : out std_logic;
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s_cen : out std_logic;
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-- sync blank and video signal outputs
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_sync: out std_logic;
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h_blank: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
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video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
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-- TEST SIGNALS
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-- TEST SIGNALS
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T_v_we_o: out std_logic;
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T_v_we_o: out std_logic;
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T_v_stb_o: out std_logic;
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T_v_stb_o: out std_logic;
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T_v_ack_i: out std_logic;
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T_v_ack_i: out std_logic;
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T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
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T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
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T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
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T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
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T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
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T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
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T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
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T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
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);
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);
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end vga_core;
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end vga_core;
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architecture vga_core of vga_core is
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architecture vga_core of vga_core is
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component video_engine
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component video_engine
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generic (
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generic (
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v_mem_width: positive := 16;
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v_mem_width: positive := 16;
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v_addr_width: positive:= 20;
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v_addr_width: positive:= 20;
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fifo_size: positive := 256;
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fifo_size: positive := 256;
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dual_scan_fifo_size: positive := 256
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dual_scan_fifo_size: positive := 256
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);
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);
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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clk_en: in std_logic := '1';
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clk_en: in std_logic := '1';
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reset: in std_logic := '0';
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reset: in std_logic := '0';
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total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
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total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
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fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
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fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
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bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
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bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
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multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
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multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
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hbs: in std_logic_vector(7 downto 0);
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hbs: in std_logic_vector(7 downto 0);
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hss: in std_logic_vector(7 downto 0);
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hss: in std_logic_vector(7 downto 0);
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hse: in std_logic_vector(7 downto 0);
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hse: in std_logic_vector(7 downto 0);
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htotal: in std_logic_vector(7 downto 0);
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htotal: in std_logic_vector(7 downto 0);
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vbs: in std_logic_vector(7 downto 0);
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vbs: in std_logic_vector(7 downto 0);
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vss: in std_logic_vector(7 downto 0);
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vss: in std_logic_vector(7 downto 0);
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vse: in std_logic_vector(7 downto 0);
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vse: in std_logic_vector(7 downto 0);
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vtotal: in std_logic_vector(7 downto 0);
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vtotal: in std_logic_vector(7 downto 0);
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pps: in std_logic_vector(7 downto 0);
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pps: in std_logic_vector(7 downto 0);
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high_prior: out std_logic; -- signals to the memory arbitrer to give high
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high_prior: out std_logic; -- signals to the memory arbitrer to give high
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-- priority to the video engine
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-- priority to the video engine
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v_mem_rd: out std_logic; -- video memory read request
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v_mem_rd: out std_logic; -- video memory read request
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v_mem_rdy: in std_logic; -- video memory data ready
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v_mem_rdy: in std_logic; -- video memory data ready
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v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
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v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
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v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
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v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
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h_sync: out std_logic;
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h_sync: out std_logic;
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h_blank: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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);
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end component video_engine;
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end component video_engine;
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component wb_async_slave
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component wb_async_slave
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generic (
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generic (
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width: positive := 16;
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width: positive := 16;
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addr_width: positive := 20
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addr_width: positive := 20
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- interface for wait-state generator state-machine
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-- interface for wait-state generator state-machine
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wait_state: in std_logic_vector (3 downto 0);
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wait_state: in std_logic_vector (3 downto 0);
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-- interface to wishbone master device
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-- interface to wishbone master device
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
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sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
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dat_i: in std_logic_vector (width-1 downto 0);
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dat_i: in std_logic_vector (width-1 downto 0);
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dat_o: out std_logic_vector (width-1 downto 0);
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dat_o: out std_logic_vector (width-1 downto 0);
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dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
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dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
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we_i: in std_logic;
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we_i: in std_logic;
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stb_i: in std_logic;
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stb_i: in std_logic;
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ack_o: out std_logic := '0';
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ack_o: out std_logic := '0';
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ack_oi: in std_logic := '-';
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ack_oi: in std_logic := '-';
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-- interface to async slave
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-- interface to async slave
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_rdn: out std_logic := '1';
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a_rdn: out std_logic := '1';
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a_wrn: out std_logic := '1';
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a_wrn: out std_logic := '1';
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a_cen: out std_logic := '1';
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a_cen: out std_logic := '1';
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-- byte-enable signals
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-- byte-enable signals
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a_byen: out std_logic_vector ((addr_width/8)-1 downto 0)
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a_byen: out std_logic_vector ((addr_width/8)-1 downto 0)
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);
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);
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end component;
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end component;
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component wb_arbiter
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component wb_arbiter
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port (
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port (
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-- clk: in std_logic;
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-- clk: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- interface to master device a
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-- interface to master device a
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a_we_i: in std_logic;
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a_we_i: in std_logic;
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a_stb_i: in std_logic;
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a_stb_i: in std_logic;
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a_cyc_i: in std_logic;
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a_cyc_i: in std_logic;
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a_ack_o: out std_logic;
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a_ack_o: out std_logic;
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a_ack_oi: in std_logic := '-';
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a_ack_oi: in std_logic := '-';
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a_err_o: out std_logic;
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a_err_o: out std_logic;
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a_err_oi: in std_logic := '-';
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a_err_oi: in std_logic := '-';
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a_rty_o: out std_logic;
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a_rty_o: out std_logic;
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a_rty_oi: in std_logic := '-';
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a_rty_oi: in std_logic := '-';
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-- interface to master device b
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-- interface to master device b
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b_we_i: in std_logic;
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b_we_i: in std_logic;
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b_stb_i: in std_logic;
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b_stb_i: in std_logic;
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b_cyc_i: in std_logic;
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b_cyc_i: in std_logic;
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b_ack_o: out std_logic;
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b_ack_o: out std_logic;
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b_ack_oi: in std_logic := '-';
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b_ack_oi: in std_logic := '-';
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b_err_o: out std_logic;
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b_err_o: out std_logic;
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b_err_oi: in std_logic := '-';
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b_err_oi: in std_logic := '-';
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b_rty_o: out std_logic;
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b_rty_o: out std_logic;
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b_rty_oi: in std_logic := '-';
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b_rty_oi: in std_logic := '-';
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-- interface to shared devices
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-- interface to shared devices
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s_we_o: out std_logic;
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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s_stb_o: out std_logic;
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s_cyc_o: out std_logic;
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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-- misc control lines
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-- misc control lines
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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);
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);
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end component;
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end component;
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component wb_out_reg
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component wb_out_reg
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generic (
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generic (
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width : positive := 8;
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width : positive := 8;
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bus_width: positive := 8;
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bus_width: positive := 8;
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offset: integer := 0
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offset: integer := 0
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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|
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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q: out std_logic_vector (width-1 downto 0);
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q: out std_logic_vector (width-1 downto 0);
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we_i: in std_logic;
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we_i: in std_logic;
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stb_i: in std_logic;
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stb_i: in std_logic;
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ack_o: out std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-'
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ack_oi: in std_logic := '-'
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);
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);
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end component;
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end component;
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component wb_bus_upsize
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component wb_bus_upsize
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generic (
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generic (
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m_bus_width: positive := 8; -- master bus width
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m_bus_width: positive := 8; -- master bus width
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m_addr_width: positive := 21; -- master bus width
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m_addr_width: positive := 21; -- master bus width
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s_bus_width: positive := 16; -- slave bus width
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s_bus_width: positive := 16; -- slave bus width
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little_endien: boolean := true -- if set to false, big endien
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little_endien: boolean := true -- if set to false, big endien
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);
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);
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port (
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port (
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-- clk_i: in std_logic;
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- rst_i: in std_logic := '0';
|
|
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-- Master bus interface
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
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m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
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m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
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m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
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m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
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m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
|
m_cyc_i: in std_logic;
|
m_cyc_i: in std_logic;
|
m_ack_o: out std_logic;
|
m_ack_o: out std_logic;
|
m_ack_oi: in std_logic := '-';
|
m_ack_oi: in std_logic := '-';
|
m_err_o: out std_logic;
|
m_err_o: out std_logic;
|
m_err_oi: in std_logic := '-';
|
m_err_oi: in std_logic := '-';
|
m_rty_o: out std_logic;
|
m_rty_o: out std_logic;
|
m_rty_oi: in std_logic := '-';
|
m_rty_oi: in std_logic := '-';
|
m_we_i: in std_logic;
|
m_we_i: in std_logic;
|
m_stb_i: in std_logic;
|
m_stb_i: in std_logic;
|
|
|
-- Slave bus interface
|
-- Slave bus interface
|
s_adr_o: out std_logic_vector (m_addr_width-2 downto 0);
|
s_adr_o: out std_logic_vector (m_addr_width-2 downto 0);
|
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
|
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
|
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic
|
s_stb_o: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
signal reset_core: std_logic_vector(0 downto 0);
|
signal reset_core: std_logic_vector(0 downto 0);
|
signal total: std_logic_vector(v_addr_width-1 downto 0);
|
signal total: std_logic_vector(v_addr_width-1 downto 0);
|
signal fifo_treshold: std_logic_vector(7 downto 0);
|
signal fifo_treshold: std_logic_vector(7 downto 0);
|
signal bpp: std_logic_vector(1 downto 0);
|
signal bpp: std_logic_vector(1 downto 0);
|
signal multi_scan: std_logic_vector(1 downto 0);
|
signal multi_scan: std_logic_vector(1 downto 0);
|
signal hbs: std_logic_vector(7 downto 0);
|
signal hbs: std_logic_vector(7 downto 0);
|
signal hss: std_logic_vector(7 downto 0);
|
signal hss: std_logic_vector(7 downto 0);
|
signal hse: std_logic_vector(7 downto 0);
|
signal hse: std_logic_vector(7 downto 0);
|
signal htotal: std_logic_vector(7 downto 0);
|
signal htotal: std_logic_vector(7 downto 0);
|
signal vbs: std_logic_vector(7 downto 0);
|
signal vbs: std_logic_vector(7 downto 0);
|
signal vss: std_logic_vector(7 downto 0);
|
signal vss: std_logic_vector(7 downto 0);
|
signal vse: std_logic_vector(7 downto 0);
|
signal vse: std_logic_vector(7 downto 0);
|
signal vtotal: std_logic_vector(7 downto 0);
|
signal vtotal: std_logic_vector(7 downto 0);
|
signal pps: std_logic_vector(7 downto 0);
|
signal pps: std_logic_vector(7 downto 0);
|
signal wait_state: std_logic_vector (3 downto 0);
|
signal wait_state: std_logic_vector (3 downto 0);
|
signal sync_pol: std_logic_vector (3 downto 0);
|
signal sync_pol: std_logic_vector (3 downto 0);
|
|
|
signal reset_core_do: std_logic_vector(bus_width-1 downto 0);
|
signal reset_core_do: std_logic_vector(bus_width-1 downto 0);
|
signal total0_do: std_logic_vector(bus_width-1 downto 0);
|
signal total0_do: std_logic_vector(bus_width-1 downto 0);
|
signal total1_do: std_logic_vector(bus_width-1 downto 0);
|
signal total1_do: std_logic_vector(bus_width-1 downto 0);
|
signal total2_do: std_logic_vector(bus_width-1 downto 0);
|
signal total2_do: std_logic_vector(bus_width-1 downto 0);
|
signal fifo_treshold_do: std_logic_vector(bus_width-1 downto 0);
|
signal fifo_treshold_do: std_logic_vector(bus_width-1 downto 0);
|
signal bpp_do: std_logic_vector(bus_width-1 downto 0);
|
signal bpp_do: std_logic_vector(bus_width-1 downto 0);
|
signal multi_scan_do: std_logic_vector(bus_width-1 downto 0);
|
signal multi_scan_do: std_logic_vector(bus_width-1 downto 0);
|
signal hbs_do: std_logic_vector(bus_width-1 downto 0);
|
signal hbs_do: std_logic_vector(bus_width-1 downto 0);
|
signal hss_do: std_logic_vector(bus_width-1 downto 0);
|
signal hss_do: std_logic_vector(bus_width-1 downto 0);
|
signal hse_do: std_logic_vector(bus_width-1 downto 0);
|
signal hse_do: std_logic_vector(bus_width-1 downto 0);
|
signal htotal_do: std_logic_vector(bus_width-1 downto 0);
|
signal htotal_do: std_logic_vector(bus_width-1 downto 0);
|
signal vbs_do: std_logic_vector(bus_width-1 downto 0);
|
signal vbs_do: std_logic_vector(bus_width-1 downto 0);
|
signal vss_do: std_logic_vector(bus_width-1 downto 0);
|
signal vss_do: std_logic_vector(bus_width-1 downto 0);
|
signal vse_do: std_logic_vector(bus_width-1 downto 0);
|
signal vse_do: std_logic_vector(bus_width-1 downto 0);
|
signal vtotal_do: std_logic_vector(bus_width-1 downto 0);
|
signal vtotal_do: std_logic_vector(bus_width-1 downto 0);
|
signal pps_do: std_logic_vector(bus_width-1 downto 0);
|
signal pps_do: std_logic_vector(bus_width-1 downto 0);
|
signal wait_state_do: std_logic_vector(bus_width-1 downto 0);
|
signal wait_state_do: std_logic_vector(bus_width-1 downto 0);
|
signal vm_do: std_logic_vector(bus_width-1 downto 0);
|
signal vm_do: std_logic_vector(bus_width-1 downto 0);
|
|
|
signal reset_core_sel: std_logic;
|
signal reset_core_sel: std_logic;
|
signal total0_sel: std_logic;
|
signal total0_sel: std_logic;
|
signal total1_sel: std_logic;
|
signal total1_sel: std_logic;
|
signal total2_sel: std_logic;
|
signal total2_sel: std_logic;
|
signal fifo_treshold_sel: std_logic;
|
signal fifo_treshold_sel: std_logic;
|
signal bpp_sel: std_logic;
|
signal bpp_sel: std_logic;
|
signal multi_scan_sel: std_logic;
|
signal multi_scan_sel: std_logic;
|
signal hbs_sel: std_logic;
|
signal hbs_sel: std_logic;
|
signal hss_sel: std_logic;
|
signal hss_sel: std_logic;
|
signal hse_sel: std_logic;
|
signal hse_sel: std_logic;
|
signal htotal_sel: std_logic;
|
signal htotal_sel: std_logic;
|
signal vbs_sel: std_logic;
|
signal vbs_sel: std_logic;
|
signal vss_sel: std_logic;
|
signal vss_sel: std_logic;
|
signal vse_sel: std_logic;
|
signal vse_sel: std_logic;
|
signal vtotal_sel: std_logic;
|
signal vtotal_sel: std_logic;
|
signal pps_sel: std_logic;
|
signal pps_sel: std_logic;
|
signal wait_state_sel: std_logic;
|
signal wait_state_sel: std_logic;
|
signal sync_pol_sel: std_logic;
|
signal sync_pol_sel: std_logic;
|
|
|
signal reset_core_ack: std_logic;
|
signal reset_core_ack: std_logic;
|
signal total0_ack: std_logic;
|
signal total0_ack: std_logic;
|
signal total1_ack: std_logic;
|
signal total1_ack: std_logic;
|
signal total2_ack: std_logic;
|
signal total2_ack: std_logic;
|
signal fifo_treshold_ack: std_logic;
|
signal fifo_treshold_ack: std_logic;
|
signal bpp_ack: std_logic;
|
signal bpp_ack: std_logic;
|
signal multi_scan_ack: std_logic;
|
signal multi_scan_ack: std_logic;
|
signal hbs_ack: std_logic;
|
signal hbs_ack: std_logic;
|
signal hss_ack: std_logic;
|
signal hss_ack: std_logic;
|
signal hse_ack: std_logic;
|
signal hse_ack: std_logic;
|
signal htotal_ack: std_logic;
|
signal htotal_ack: std_logic;
|
signal vbs_ack: std_logic;
|
signal vbs_ack: std_logic;
|
signal vss_ack: std_logic;
|
signal vss_ack: std_logic;
|
signal vse_ack: std_logic;
|
signal vse_ack: std_logic;
|
signal vtotal_ack: std_logic;
|
signal vtotal_ack: std_logic;
|
signal pps_ack: std_logic;
|
signal pps_ack: std_logic;
|
signal wait_state_ack: std_logic;
|
signal wait_state_ack: std_logic;
|
signal vm_ack: std_logic;
|
signal vm_ack: std_logic;
|
|
|
signal a_adr_o : std_logic_vector((v_addr_width-1) downto 0);
|
signal a_adr_o : std_logic_vector((v_addr_width-1) downto 0);
|
signal a_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
|
signal a_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
|
signal a_dat_o : std_logic_vector((v_mem_width-1) downto 0);
|
signal a_dat_o : std_logic_vector((v_mem_width-1) downto 0);
|
signal a_dat_i : std_logic_vector((v_mem_width-1) downto 0);
|
signal a_dat_i : std_logic_vector((v_mem_width-1) downto 0);
|
signal a_we_o : std_logic;
|
signal a_we_o : std_logic;
|
signal a_stb_o : std_logic;
|
signal a_stb_o : std_logic;
|
signal a_cyc_o : std_logic;
|
signal a_cyc_o : std_logic;
|
signal a_ack_i : std_logic;
|
signal a_ack_i : std_logic;
|
|
|
signal b_adr_o : std_logic_vector((v_addr_width-1) downto 0);
|
signal b_adr_o : std_logic_vector((v_addr_width-1) downto 0);
|
signal b_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
|
signal b_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
|
-- signal b_dat_o : std_logic_vector((v_mem_width-1) downto 0);
|
-- signal b_dat_o : std_logic_vector((v_mem_width-1) downto 0);
|
signal b_dat_i : std_logic_vector((v_mem_width-1) downto 0);
|
signal b_dat_i : std_logic_vector((v_mem_width-1) downto 0);
|
signal b_stb_o : std_logic;
|
signal b_stb_o : std_logic;
|
-- signal b_we_o : std_logic;
|
-- signal b_we_o : std_logic;
|
-- signal b_cyc_o : std_logic;
|
-- signal b_cyc_o : std_logic;
|
signal b_ack_i : std_logic;
|
signal b_ack_i : std_logic;
|
|
|
signal v_we_o: std_logic;
|
signal v_we_o: std_logic;
|
signal v_stb_o: std_logic;
|
signal v_stb_o: std_logic;
|
signal v_ack_i: std_logic;
|
signal v_ack_i: std_logic;
|
signal v_adr_o : std_logic_vector((v_addr_width-1) downto 0);
|
signal v_adr_o : std_logic_vector((v_addr_width-1) downto 0);
|
signal v_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
|
signal v_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
|
signal v_dat_o : std_logic_vector((v_mem_width-1) downto 0);
|
signal v_dat_o : std_logic_vector((v_mem_width-1) downto 0);
|
signal v_dat_i : std_logic_vector((v_mem_width-1) downto 0);
|
signal v_dat_i : std_logic_vector((v_mem_width-1) downto 0);
|
|
|
signal s_byen : std_logic_vector((v_addr_width/8)-1 downto 0);
|
signal s_byen : std_logic_vector((v_addr_width/8)-1 downto 0);
|
|
|
signal mux_signal: std_logic;
|
signal mux_signal: std_logic;
|
|
|
signal high_prior: std_logic;
|
signal high_prior: std_logic;
|
|
|
signal reset_engine: std_logic;
|
signal reset_engine: std_logic;
|
|
|
signal i_h_sync: std_logic;
|
signal i_h_sync: std_logic;
|
signal i_h_blank: std_logic;
|
signal i_h_blank: std_logic;
|
signal i_v_sync: std_logic;
|
signal i_v_sync: std_logic;
|
signal i_v_blank: std_logic;
|
signal i_v_blank: std_logic;
|
|
|
signal s_wrn : std_logic;
|
signal s_wrn : std_logic;
|
|
|
begin
|
begin
|
-- map all registers:
|
-- map all registers:
|
reset_core_reg: wb_out_reg
|
reset_core_reg: wb_out_reg
|
generic map( width => 1, bus_width => bus_width , offset => 4 )
|
generic map( width => 1, bus_width => bus_width , offset => 4 )
|
port map(
|
port map(
|
stb_i => reset_core_sel,
|
stb_i => reset_core_sel,
|
q => reset_core,
|
q => reset_core,
|
rst_val => "1",
|
rst_val => "1",
|
dat_oi => vm_do,
|
dat_oi => vm_do,
|
dat_o => reset_core_do,
|
dat_o => reset_core_do,
|
ack_oi => vm_ack,
|
ack_oi => vm_ack,
|
ack_o => reset_core_ack,
|
ack_o => reset_core_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
total0_reg: wb_out_reg
|
total0_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => total0_sel,
|
stb_i => total0_sel,
|
q => total(7 downto 0),
|
q => total(7 downto 0),
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => reset_core_do,
|
dat_oi => reset_core_do,
|
dat_o => total0_do,
|
dat_o => total0_do,
|
ack_oi => reset_core_ack,
|
ack_oi => reset_core_ack,
|
ack_o => total0_ack,
|
ack_o => total0_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
total1_reg: wb_out_reg
|
total1_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => total1_sel,
|
stb_i => total1_sel,
|
q => total(15 downto 8),
|
q => total(15 downto 8),
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => total0_do,
|
dat_oi => total0_do,
|
dat_o => total1_do,
|
dat_o => total1_do,
|
ack_oi => total0_ack,
|
ack_oi => total0_ack,
|
ack_o => total1_ack,
|
ack_o => total1_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
total2_reg: wb_out_reg
|
total2_reg: wb_out_reg
|
generic map( width => 4, bus_width => bus_width , offset => 0 )
|
generic map( width => 4, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => total2_sel,
|
stb_i => total2_sel,
|
q => total(19 downto 16),
|
q => total(19 downto 16),
|
rst_val => "0000",
|
rst_val => "0000",
|
dat_oi => total1_do,
|
dat_oi => total1_do,
|
dat_o => total2_do,
|
dat_o => total2_do,
|
ack_oi => total1_ack,
|
ack_oi => total1_ack,
|
ack_o => total2_ack,
|
ack_o => total2_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
fifo_treshold_reg: wb_out_reg
|
fifo_treshold_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => fifo_treshold_sel,
|
stb_i => fifo_treshold_sel,
|
q => fifo_treshold,
|
q => fifo_treshold,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => total2_do,
|
dat_oi => total2_do,
|
dat_o => fifo_treshold_do,
|
dat_o => fifo_treshold_do,
|
ack_oi => total2_ack,
|
ack_oi => total2_ack,
|
ack_o => fifo_treshold_ack,
|
ack_o => fifo_treshold_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
bpp_reg: wb_out_reg
|
bpp_reg: wb_out_reg
|
generic map( width => 2, bus_width => bus_width , offset => 0 )
|
generic map( width => 2, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => bpp_sel,
|
stb_i => bpp_sel,
|
q => bpp,
|
q => bpp,
|
rst_val => "00",
|
rst_val => "00",
|
dat_oi => fifo_treshold_do,
|
dat_oi => fifo_treshold_do,
|
dat_o => bpp_do,
|
dat_o => bpp_do,
|
ack_oi => fifo_treshold_ack,
|
ack_oi => fifo_treshold_ack,
|
ack_o => bpp_ack,
|
ack_o => bpp_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
multi_scan_reg: wb_out_reg
|
multi_scan_reg: wb_out_reg
|
generic map( width => 2, bus_width => bus_width , offset => 2 )
|
generic map( width => 2, bus_width => bus_width , offset => 2 )
|
port map(
|
port map(
|
stb_i => multi_scan_sel,
|
stb_i => multi_scan_sel,
|
q => multi_scan,
|
q => multi_scan,
|
rst_val => "00",
|
rst_val => "00",
|
dat_oi => bpp_do,
|
dat_oi => bpp_do,
|
dat_o => multi_scan_do,
|
dat_o => multi_scan_do,
|
ack_oi => bpp_ack,
|
ack_oi => bpp_ack,
|
ack_o => multi_scan_ack,
|
ack_o => multi_scan_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
hbs_reg: wb_out_reg
|
hbs_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => hbs_sel,
|
stb_i => hbs_sel,
|
q => hbs,
|
q => hbs,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => multi_scan_do,
|
dat_oi => multi_scan_do,
|
dat_o => hbs_do,
|
dat_o => hbs_do,
|
ack_oi => multi_scan_ack,
|
ack_oi => multi_scan_ack,
|
ack_o => hbs_ack,
|
ack_o => hbs_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
hss_reg: wb_out_reg
|
hss_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => hss_sel,
|
stb_i => hss_sel,
|
q => hss,
|
q => hss,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => hbs_do,
|
dat_oi => hbs_do,
|
dat_o => hss_do,
|
dat_o => hss_do,
|
ack_oi => hbs_ack,
|
ack_oi => hbs_ack,
|
ack_o => hss_ack,
|
ack_o => hss_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
hse_reg: wb_out_reg
|
hse_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => hse_sel,
|
stb_i => hse_sel,
|
q => hse,
|
q => hse,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => hss_do,
|
dat_oi => hss_do,
|
dat_o => hse_do,
|
dat_o => hse_do,
|
ack_oi => hss_ack,
|
ack_oi => hss_ack,
|
ack_o => hse_ack,
|
ack_o => hse_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
htotal_reg: wb_out_reg
|
htotal_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => htotal_sel,
|
stb_i => htotal_sel,
|
q => htotal,
|
q => htotal,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => hse_do,
|
dat_oi => hse_do,
|
dat_o => htotal_do,
|
dat_o => htotal_do,
|
ack_oi => hse_ack,
|
ack_oi => hse_ack,
|
ack_o => htotal_ack,
|
ack_o => htotal_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
vbs_reg: wb_out_reg
|
vbs_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => vbs_sel,
|
stb_i => vbs_sel,
|
q => vbs,
|
q => vbs,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => htotal_do,
|
dat_oi => htotal_do,
|
dat_o => vbs_do,
|
dat_o => vbs_do,
|
ack_oi => htotal_ack,
|
ack_oi => htotal_ack,
|
ack_o => vbs_ack,
|
ack_o => vbs_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
vss_reg: wb_out_reg
|
vss_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => vss_sel,
|
stb_i => vss_sel,
|
q => vss,
|
q => vss,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => vbs_do,
|
dat_oi => vbs_do,
|
dat_o => vss_do,
|
dat_o => vss_do,
|
ack_oi => vbs_ack,
|
ack_oi => vbs_ack,
|
ack_o => vss_ack,
|
ack_o => vss_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
vse_reg: wb_out_reg
|
vse_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => vse_sel,
|
stb_i => vse_sel,
|
q => vse,
|
q => vse,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => vss_do,
|
dat_oi => vss_do,
|
dat_o => vse_do,
|
dat_o => vse_do,
|
ack_oi => vss_ack,
|
ack_oi => vss_ack,
|
ack_o => vse_ack,
|
ack_o => vse_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
vtotal_reg: wb_out_reg
|
vtotal_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => vtotal_sel,
|
stb_i => vtotal_sel,
|
q => vtotal,
|
q => vtotal,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => vse_do,
|
dat_oi => vse_do,
|
dat_o => vtotal_do,
|
dat_o => vtotal_do,
|
ack_oi => vse_ack,
|
ack_oi => vse_ack,
|
ack_o => vtotal_ack,
|
ack_o => vtotal_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
pps_reg: wb_out_reg
|
pps_reg: wb_out_reg
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
generic map( width => 8, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => pps_sel,
|
stb_i => pps_sel,
|
q => pps,
|
q => pps,
|
rst_val => "00000000",
|
rst_val => "00000000",
|
dat_oi => vtotal_do,
|
dat_oi => vtotal_do,
|
dat_o => pps_do,
|
dat_o => pps_do,
|
ack_oi => vtotal_ack,
|
ack_oi => vtotal_ack,
|
ack_o => pps_ack,
|
ack_o => pps_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
wait_state_reg: wb_out_reg
|
wait_state_reg: wb_out_reg
|
generic map( width => 4, bus_width => bus_width , offset => 0 )
|
generic map( width => 4, bus_width => bus_width , offset => 0 )
|
port map(
|
port map(
|
stb_i => wait_state_sel,
|
stb_i => wait_state_sel,
|
q => wait_state,
|
q => wait_state,
|
rst_val => "0000",
|
rst_val => "0000",
|
dat_oi => pps_do,
|
dat_oi => pps_do,
|
dat_o => wait_state_do,
|
dat_o => wait_state_do,
|
ack_oi => pps_ack,
|
ack_oi => pps_ack,
|
ack_o => wait_state_ack,
|
ack_o => wait_state_ack,
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
sync_pol_reg: wb_out_reg
|
sync_pol_reg: wb_out_reg
|
generic map( width => 4, bus_width => bus_width , offset => 4 )
|
generic map( width => 4, bus_width => bus_width , offset => 4 )
|
port map(
|
port map(
|
stb_i => sync_pol_sel,
|
stb_i => sync_pol_sel,
|
q => sync_pol,
|
q => sync_pol,
|
rst_val => "0000",
|
rst_val => "0000",
|
dat_oi => wait_state_do,
|
dat_oi => wait_state_do,
|
dat_o => dat_o, -- END OF THE CHAIN
|
dat_o => dat_o, -- END OF THE CHAIN
|
ack_oi => wait_state_ack,
|
ack_oi => wait_state_ack,
|
ack_o => ack_o, -- END OF THE CHAIN
|
ack_o => ack_o, -- END OF THE CHAIN
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
|
|
|
reset_engine <= rst_i or reset_core(0);
|
reset_engine <= rst_i or reset_core(0);
|
|
|
v_e: video_engine
|
v_e: video_engine
|
generic map ( v_mem_width => v_mem_width, v_addr_width => v_addr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
|
generic map ( v_mem_width => v_mem_width, v_addr_width => v_addr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
|
port map (
|
port map (
|
clk => clk_i,
|
clk => clk_i,
|
clk_en => clk_en,
|
clk_en => clk_en,
|
reset => reset_engine,
|
reset => reset_engine,
|
total => total,
|
total => total,
|
fifo_treshold => fifo_treshold,
|
fifo_treshold => fifo_treshold,
|
bpp => bpp,
|
bpp => bpp,
|
multi_scan => multi_scan,
|
multi_scan => multi_scan,
|
hbs => hbs,
|
hbs => hbs,
|
hss => hss,
|
hss => hss,
|
hse => hse,
|
hse => hse,
|
htotal => htotal,
|
htotal => htotal,
|
vbs => vbs,
|
vbs => vbs,
|
vss => vss,
|
vss => vss,
|
vse => vse,
|
vse => vse,
|
vtotal => vtotal,
|
vtotal => vtotal,
|
pps => pps,
|
pps => pps,
|
|
|
high_prior => high_prior,
|
high_prior => high_prior,
|
|
|
v_mem_rd => b_stb_o,
|
v_mem_rd => b_stb_o,
|
v_mem_rdy => b_ack_i,
|
v_mem_rdy => b_ack_i,
|
v_mem_addr => b_adr_o,
|
v_mem_addr => b_adr_o,
|
v_mem_data => b_dat_i,
|
v_mem_data => b_dat_i,
|
|
|
h_sync => i_h_sync,
|
h_sync => i_h_sync,
|
h_blank => i_h_blank,
|
h_blank => i_h_blank,
|
v_sync => i_v_sync,
|
v_sync => i_v_sync,
|
v_blank => i_v_blank,
|
v_blank => i_v_blank,
|
h_tc => h_tc,
|
h_tc => h_tc,
|
v_tc => v_tc,
|
v_tc => v_tc,
|
blank => blank,
|
blank => blank,
|
video_out => video_out
|
video_out => video_out
|
);
|
);
|
|
|
h_sync <= i_h_sync xor sync_pol(0);
|
h_sync <= i_h_sync xor sync_pol(0);
|
v_sync <= i_v_sync xor sync_pol(1);
|
v_sync <= i_v_sync xor sync_pol(1);
|
h_blank <= i_h_blank;-- xor sync_pol(2);
|
h_blank <= i_h_blank;-- xor sync_pol(2);
|
v_blank <= i_v_blank;-- xor sync_pol(3);
|
v_blank <= i_v_blank;-- xor sync_pol(3);
|
|
|
resize: wb_bus_upsize
|
resize: wb_bus_upsize
|
generic map (
|
generic map (
|
m_bus_width => bus_width, s_bus_width => v_mem_width, m_addr_width => v_addr_width+1
|
m_bus_width => bus_width, s_bus_width => v_mem_width, m_addr_width => v_addr_width+1
|
)
|
)
|
port map (
|
port map (
|
m_adr_i => adr_i,
|
m_adr_i => adr_i,
|
-- m_sel_i => (others => '1'),
|
-- m_sel_i => (others => '1'),
|
m_dat_i => dat_i,
|
m_dat_i => dat_i,
|
m_dat_oi => dat_oi, -- Beginning of the chain
|
m_dat_oi => dat_oi, -- Beginning of the chain
|
m_cyc_i => cyc_i,
|
m_cyc_i => cyc_i,
|
m_dat_o => vm_do,
|
m_dat_o => vm_do,
|
m_ack_o => vm_ack,
|
m_ack_o => vm_ack,
|
m_ack_oi => ack_oi, -- Beginning of the chain
|
m_ack_oi => ack_oi, -- Beginning of the chain
|
m_we_i => we_i,
|
m_we_i => we_i,
|
m_stb_i => vmem_stb_i,
|
m_stb_i => vmem_stb_i,
|
|
|
s_adr_o => a_adr_o,
|
s_adr_o => a_adr_o,
|
s_sel_o => a_sel_o,
|
s_sel_o => a_sel_o,
|
s_dat_i => a_dat_i,
|
s_dat_i => a_dat_i,
|
s_dat_o => a_dat_o,
|
s_dat_o => a_dat_o,
|
s_cyc_o => a_cyc_o,
|
s_cyc_o => a_cyc_o,
|
s_ack_i => a_ack_i,
|
s_ack_i => a_ack_i,
|
s_we_o => a_we_o,
|
s_we_o => a_we_o,
|
s_stb_o => a_stb_o
|
s_stb_o => a_stb_o
|
);
|
);
|
|
|
|
|
arbiter: wb_arbiter
|
arbiter: wb_arbiter
|
port map (
|
port map (
|
rst_i => reset_engine,
|
rst_i => reset_engine,
|
|
|
a_we_i => a_we_o,
|
a_we_i => a_we_o,
|
a_cyc_i => a_cyc_o,
|
a_cyc_i => a_cyc_o,
|
a_stb_i => a_stb_o,
|
a_stb_i => a_stb_o,
|
a_ack_o => a_ack_i,
|
a_ack_o => a_ack_i,
|
a_ack_oi => '-',
|
a_ack_oi => '-',
|
|
|
b_we_i => '0',
|
b_we_i => '0',
|
b_cyc_i => b_stb_o,
|
b_cyc_i => b_stb_o,
|
b_stb_i => b_stb_o,
|
b_stb_i => b_stb_o,
|
b_ack_o => b_ack_i,
|
b_ack_o => b_ack_i,
|
b_ack_oi => '0', -- maybe not needed at all
|
b_ack_oi => '0', -- maybe not needed at all
|
|
|
s_we_o => v_we_o,
|
s_we_o => v_we_o,
|
s_stb_o => v_stb_o,
|
s_stb_o => v_stb_o,
|
s_ack_i => v_ack_i,
|
s_ack_i => v_ack_i,
|
|
|
mux_signal => mux_signal,
|
mux_signal => mux_signal,
|
|
|
priority => high_prior
|
priority => high_prior
|
);
|
);
|
|
|
b_sel_o <= (others => '1');
|
b_sel_o <= (others => '1');
|
|
|
bus_mux: process is
|
bus_mux: process is
|
begin
|
begin
|
wait on mux_signal, v_dat_i, a_adr_o, a_dat_o, b_adr_o, a_sel_o, b_sel_o;
|
wait on mux_signal, v_dat_i, a_adr_o, a_dat_o, b_adr_o, a_sel_o, b_sel_o;
|
if (mux_signal = '0') then
|
if (mux_signal = '0') then
|
v_adr_o <= a_adr_o;
|
v_adr_o <= a_adr_o;
|
v_sel_o <= a_sel_o;
|
v_sel_o <= a_sel_o;
|
v_dat_o <= a_dat_o;
|
v_dat_o <= a_dat_o;
|
a_dat_i <= v_dat_i;
|
a_dat_i <= v_dat_i;
|
b_dat_i <= (others => '-');
|
b_dat_i <= (others => '-');
|
else
|
else
|
v_adr_o <= b_adr_o;
|
v_adr_o <= b_adr_o;
|
v_sel_o <= b_sel_o;
|
v_sel_o <= b_sel_o;
|
v_dat_o <= (others => '-');
|
v_dat_o <= (others => '-');
|
b_dat_i <= v_dat_i;
|
b_dat_i <= v_dat_i;
|
a_dat_i <= (others => '-');
|
a_dat_i <= (others => '-');
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
mem_driver: wb_async_slave
|
mem_driver: wb_async_slave
|
generic map (width => v_mem_width, addr_width => v_addr_width)
|
generic map (width => v_mem_width, addr_width => v_addr_width)
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
rst_i => reset_engine,
|
rst_i => reset_engine,
|
|
|
wait_state => wait_state,
|
wait_state => wait_state,
|
|
|
adr_i => v_adr_o,
|
adr_i => v_adr_o,
|
sel_i => v_sel_o,
|
sel_i => v_sel_o,
|
dat_o => v_dat_i,
|
dat_o => v_dat_i,
|
dat_i => v_dat_o,
|
dat_i => v_dat_o,
|
-- dat_oi => (others => '0'), -- may not be needed
|
-- dat_oi => (others => '0'), -- may not be needed
|
we_i => v_we_o,
|
we_i => v_we_o,
|
stb_i => v_stb_o,
|
stb_i => v_stb_o,
|
ack_o => v_ack_i,
|
ack_o => v_ack_i,
|
ack_oi => '0', -- may not be needed
|
ack_oi => '0', -- may not be needed
|
|
|
a_data => s_data,
|
a_data => s_data,
|
a_addr => s_addr,
|
a_addr => s_addr,
|
a_rdn => s_oen,
|
a_rdn => s_oen,
|
a_wrn => s_wrn,
|
a_wrn => s_wrn,
|
a_cen => s_cen,
|
a_cen => s_cen,
|
a_byen => s_byen
|
a_byen => s_byen
|
);
|
);
|
|
|
s_wrln <= s_wrn or s_byen(0);
|
s_wrln <= s_wrn or s_byen(0);
|
s_wrhn <= s_wrn or s_byen(1);
|
s_wrhn <= s_wrn or s_byen(1);
|
|
|
addr_decoder: process is
|
addr_decoder: process is
|
begin
|
begin
|
wait on reg_stb_i, adr_i;
|
wait on reg_stb_i, adr_i;
|
|
|
reset_core_sel <= '0';
|
reset_core_sel <= '0';
|
total0_sel <= '0';
|
total0_sel <= '0';
|
total1_sel <= '0';
|
total1_sel <= '0';
|
total2_sel <= '0';
|
total2_sel <= '0';
|
fifo_treshold_sel <= '0';
|
fifo_treshold_sel <= '0';
|
bpp_sel <= '0';
|
bpp_sel <= '0';
|
multi_scan_sel <= '0';
|
multi_scan_sel <= '0';
|
hbs_sel <= '0';
|
hbs_sel <= '0';
|
hss_sel <= '0';
|
hss_sel <= '0';
|
hse_sel <= '0';
|
hse_sel <= '0';
|
htotal_sel <= '0';
|
htotal_sel <= '0';
|
vbs_sel <= '0';
|
vbs_sel <= '0';
|
vss_sel <= '0';
|
vss_sel <= '0';
|
vse_sel <= '0';
|
vse_sel <= '0';
|
vtotal_sel <= '0';
|
vtotal_sel <= '0';
|
pps_sel <= '0';
|
pps_sel <= '0';
|
wait_state_sel <= '0';
|
wait_state_sel <= '0';
|
sync_pol_sel <= '0';
|
sync_pol_sel <= '0';
|
|
|
if (reg_stb_i = '1') then
|
if (reg_stb_i = '1') then
|
case (adr_i(4 downto 0)) is
|
case (adr_i(4 downto 0)) is
|
when "00000" => total0_sel <= '1';
|
when "00000" => total0_sel <= '1';
|
when "00001" => total1_sel <= '1';
|
when "00001" => total1_sel <= '1';
|
when "00010" => total2_sel <= '1';
|
when "00010" => total2_sel <= '1';
|
when "00011" => fifo_treshold_sel <= '1';
|
when "00011" => fifo_treshold_sel <= '1';
|
|
|
when "00100" => hbs_sel <= '1';
|
when "00100" => hbs_sel <= '1';
|
when "00101" => hss_sel <= '1';
|
when "00101" => hss_sel <= '1';
|
when "00110" => hse_sel <= '1';
|
when "00110" => hse_sel <= '1';
|
when "00111" => htotal_sel <= '1';
|
when "00111" => htotal_sel <= '1';
|
|
|
when "01000" => vbs_sel <= '1';
|
when "01000" => vbs_sel <= '1';
|
when "01001" => vss_sel <= '1';
|
when "01001" => vss_sel <= '1';
|
when "01010" => vse_sel <= '1';
|
when "01010" => vse_sel <= '1';
|
when "01011" => vtotal_sel <= '1';
|
when "01011" => vtotal_sel <= '1';
|
|
|
when "01100" => pps_sel <= '1';
|
when "01100" => pps_sel <= '1';
|
when "01101" => wait_state_sel <= '1'; sync_pol_sel <= '1';
|
when "01101" => wait_state_sel <= '1'; sync_pol_sel <= '1';
|
when "01110" => bpp_sel <= '1'; multi_scan_sel <= '1'; reset_core_sel <= '1';
|
when "01110" => bpp_sel <= '1'; multi_scan_sel <= '1'; reset_core_sel <= '1';
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- TEST SIGNALS
|
-- TEST SIGNALS
|
T_v_we_o <= v_we_o;
|
T_v_we_o <= v_we_o;
|
T_v_stb_o <= v_stb_o;
|
T_v_stb_o <= v_stb_o;
|
T_v_ack_i <= v_ack_i;
|
T_v_ack_i <= v_ack_i;
|
T_v_adr_o <= v_adr_o;
|
T_v_adr_o <= v_adr_o;
|
T_v_sel_o <= v_sel_o;
|
T_v_sel_o <= v_sel_o;
|
T_v_dat_o <= v_dat_o;
|
T_v_dat_o <= v_dat_o;
|
T_v_dat_i <= v_dat_i;
|
T_v_dat_i <= v_dat_i;
|
|
|
end vga_core;
|
end vga_core;
|
|
|
|
|
