library ieee,wb_tk,wb_vga;
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library ieee,wb_tk,wb_vga;
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use ieee.NUMERIC_STD.all;
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use ieee.NUMERIC_STD.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use wb_tk.technology.all;
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use wb_tk.technology.all;
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use wb_tk.wb_test.all;
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use wb_tk.wb_test.all;
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use wb_tk.all;
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use wb_tk.all;
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use wb_vga.all;
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use wb_vga.all;
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entity accel_tb is
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entity accel_tb is
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generic(
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generic(
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accel_size : POSITIVE := 9;
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accel_size : POSITIVE := 9;
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video_addr_width : POSITIVE := 20;
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video_addr_width : POSITIVE := 20;
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video_data_width : POSITIVE := 16;
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video_data_width : POSITIVE := 16;
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data_width : POSITIVE := 16 );
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data_width : POSITIVE := 16 );
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end accel_tb;
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end accel_tb;
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architecture TB of accel_tb is
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architecture TB of accel_tb is
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component accel
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component accel
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generic(
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generic(
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accel_size : POSITIVE := accel_size;
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accel_size : POSITIVE := accel_size;
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video_addr_width : POSITIVE := video_addr_width;
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video_addr_width : POSITIVE := video_addr_width;
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video_data_width : POSITIVE := video_data_width;
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video_data_width : POSITIVE := video_data_width;
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data_width : POSITIVE := data_width
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data_width : POSITIVE := data_width
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- Slave interface to the CPU side
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-- Slave interface to the CPU side
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we_i: in std_logic;
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we_i: in std_logic;
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cyc_i: in std_logic;
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cyc_i: in std_logic;
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sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
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sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
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cur_stb_i: in std_logic;
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cur_stb_i: in std_logic;
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ext_stb_i: in std_logic;
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ext_stb_i: in std_logic;
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acc_stb_i: in std_logic;
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acc_stb_i: in std_logic;
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mem_stb_i: in std_logic;
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mem_stb_i: in std_logic;
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adr_i: in std_logic_vector(accel_size-1 downto 0);
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adr_i: in std_logic_vector(accel_size-1 downto 0);
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dat_i: in std_logic_vector(data_width-1 downto 0);
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dat_i: in std_logic_vector(data_width-1 downto 0);
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dat_o: out std_logic_vector(data_width-1 downto 0);
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dat_o: out std_logic_vector(data_width-1 downto 0);
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dat_oi: in std_logic_vector(data_width-1 downto 0);
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dat_oi: in std_logic_vector(data_width-1 downto 0);
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ack_o: out std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic;
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ack_oi: in std_logic;
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-- Master interface to the video memory side.
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-- Master interface to the video memory side.
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v_we_o: out std_logic;
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v_we_o: out std_logic;
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v_cyc_o: out std_logic;
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v_cyc_o: out std_logic;
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v_sel_o: out std_logic;
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v_sel_o: out std_logic;
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v_adr_o: out std_logic_vector (video_addr_width-1 downto 0);
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v_adr_o: out std_logic_vector (video_addr_width-1 downto 0);
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v_dat_o: out std_logic_vector (video_data_width-1 downto 0);
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v_dat_o: out std_logic_vector (video_data_width-1 downto 0);
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v_dat_i: in std_logic_vector (video_data_width-1 downto 0);
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v_dat_i: in std_logic_vector (video_data_width-1 downto 0);
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v_ack_i: in std_logic
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v_ack_i: in std_logic
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);
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);
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end component;
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end component;
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-- Stimulus signals - signals mapped to the input and inout ports of tested entity
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-- Stimulus signals - signals mapped to the input and inout ports of tested entity
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signal clk_i : std_logic;
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signal clk_i : std_logic;
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signal rst_i : std_logic;
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signal rst_i : std_logic;
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signal we_i : std_logic;
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signal we_i : std_logic;
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signal cyc_i : std_logic;
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signal cyc_i : std_logic;
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signal sel_i: std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
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signal sel_i: std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
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signal cur_stb_i : std_logic;
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signal cur_stb_i : std_logic;
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signal ext_stb_i : std_logic;
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signal ext_stb_i : std_logic;
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signal acc_stb_i : std_logic;
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signal acc_stb_i : std_logic;
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signal mem_stb_i : std_logic;
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signal mem_stb_i : std_logic;
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signal adr_i : std_logic_vector((accel_size-1) downto 0);
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signal adr_i : std_logic_vector((accel_size-1) downto 0);
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signal dat_i : std_logic_vector((data_width-1) downto 0);
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signal dat_i : std_logic_vector((data_width-1) downto 0);
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signal dat_oi : std_logic_vector((data_width-1) downto 0);
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signal dat_oi : std_logic_vector((data_width-1) downto 0);
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signal ack_oi : std_logic;
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signal ack_oi : std_logic;
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signal v_dat_i : std_logic_vector((video_data_width-1) downto 0);
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signal v_dat_i : std_logic_vector((video_data_width-1) downto 0);
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signal v_ack_i : std_logic;
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signal v_ack_i : std_logic;
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-- Observed signals - signals mapped to the output ports of tested entity
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-- Observed signals - signals mapped to the output ports of tested entity
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signal dat_o : std_logic_vector((data_width-1) downto 0);
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signal dat_o : std_logic_vector((data_width-1) downto 0);
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signal ack_o : std_logic;
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signal ack_o : std_logic;
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signal v_we_o : std_logic;
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signal v_we_o : std_logic;
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signal v_sel_o : std_logic;
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signal v_sel_o : std_logic;
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signal v_cyc_o : std_logic;
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signal v_cyc_o : std_logic;
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signal v_adr_o : std_logic_vector((video_addr_width-1) downto 0);
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signal v_adr_o : std_logic_vector((video_addr_width-1) downto 0);
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signal v_dat_o : std_logic_vector((video_data_width-1) downto 0);
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signal v_dat_o : std_logic_vector((video_data_width-1) downto 0);
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begin
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begin
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-- Unit Under Test port map
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-- Unit Under Test port map
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UUT : accel
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UUT : accel
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port map
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port map
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(clk_i => clk_i,
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(clk_i => clk_i,
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rst_i => rst_i,
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rst_i => rst_i,
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we_i => we_i,
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we_i => we_i,
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cyc_i => cyc_i,
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cyc_i => cyc_i,
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sel_i => sel_i,
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sel_i => sel_i,
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cur_stb_i => cur_stb_i,
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cur_stb_i => cur_stb_i,
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ext_stb_i => ext_stb_i,
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ext_stb_i => ext_stb_i,
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acc_stb_i => acc_stb_i,
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acc_stb_i => acc_stb_i,
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mem_stb_i => mem_stb_i,
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mem_stb_i => mem_stb_i,
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adr_i => adr_i,
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adr_i => adr_i,
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dat_i => dat_i,
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dat_i => dat_i,
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dat_o => dat_o,
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dat_o => dat_o,
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dat_oi => dat_oi,
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dat_oi => dat_oi,
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ack_o => ack_o,
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ack_o => ack_o,
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ack_oi => ack_oi,
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ack_oi => ack_oi,
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v_we_o => v_we_o,
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v_we_o => v_we_o,
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v_cyc_o => v_cyc_o,
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v_cyc_o => v_cyc_o,
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v_sel_o => v_sel_o,
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v_sel_o => v_sel_o,
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v_adr_o => v_adr_o,
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v_adr_o => v_adr_o,
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v_dat_o => v_dat_o,
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v_dat_o => v_dat_o,
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v_dat_i => v_dat_i,
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v_dat_i => v_dat_i,
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v_ack_i => v_ack_i );
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v_ack_i => v_ack_i );
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clk: process is
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clk: process is
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begin
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begin
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clk_i <= '0';
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clk_i <= '0';
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wait for 25ns;
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wait for 25ns;
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clk_i <= '1';
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clk_i <= '1';
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wait for 25ns;
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wait for 25ns;
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end process;
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end process;
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reset: process is
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reset: process is
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begin
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begin
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rst_i <= '1';
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rst_i <= '1';
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wait for 150ns;
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wait for 150ns;
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rst_i <= '0';
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rst_i <= '0';
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wait;
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wait;
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end process;
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end process;
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memory: process is
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memory: process is
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begin
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begin
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v_ack_i <= '0';
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v_ack_i <= '0';
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v_dat_i <= (others => 'U');
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v_dat_i <= (others => 'U');
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if (v_sel_o /= '1') then wait until v_sel_o = '1'; end if;
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if (v_sel_o /= '1') then wait until v_sel_o = '1'; end if;
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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v_ack_i <= '1';
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v_ack_i <= '1';
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if (v_we_o = '1') then
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if (v_we_o = '1') then
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v_dat_i <= v_adr_o(v_dat_i'RANGE);
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v_dat_i <= v_adr_o(v_dat_i'RANGE);
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else
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else
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v_dat_i <= (others => 'U');
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v_dat_i <= (others => 'U');
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end if;
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end if;
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait for 15ns;
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wait for 15ns;
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end process;
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end process;
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dat_oi <= (others => 'U');
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dat_oi <= (others => 'U');
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ack_oi <= 'U';
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ack_oi <= 'U';
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master: process is
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master: process is
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variable init: boolean := true;
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variable init: boolean := true;
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begin
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begin
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if (init) then
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if (init) then
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we_i <= '0';
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we_i <= '0';
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cyc_i <= '0';
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cyc_i <= '0';
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cur_stb_i <= '0';
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cur_stb_i <= '0';
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ext_stb_i <= '0';
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ext_stb_i <= '0';
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acc_stb_i <= '0';
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acc_stb_i <= '0';
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mem_stb_i <= '0';
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mem_stb_i <= '0';
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adr_i <= (others => '0');
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adr_i <= (others => '0');
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dat_i <= (others => '0');
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dat_i <= (others => '0');
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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-- Set Cursor to 0
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-- Set Cursor to 0
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000");
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-- Accel index 0 is 0
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-- Accel index 0 is 0
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000000","0000000000000000");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000000","0000000000000000");
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-- Accel index 1 is 1
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-- Accel index 1 is 1
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000001","0000000000000001");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000001","0000000000000001");
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-- Accel index 2 is 3
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-- Accel index 2 is 3
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000010","0000000000000011");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000010","0000000000000011");
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-- Accel index 3 is -1
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-- Accel index 3 is -1
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000011","1111111111111111");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,acc_stb_i,ack_o,"000000011","1111111111111111");
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end if;
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end if;
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init := false;
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init := false;
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000001");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000001");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000001000");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000001000");
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-- Set Cursor to 16
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-- Set Cursor to 16
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010000");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000000","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000001","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010001");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000010001");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000010","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,mem_stb_i,ack_o,"000000011","1111000011110000");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000011000");
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chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000011000");
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-- Set Cursor to 0
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-- Set Cursor to 0
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000");
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,cur_stb_i,ack_o,"000000000","0000000000000000");
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|
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wait;
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wait;
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end process;
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end process;
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end TB;
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end TB;
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|
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configuration TB_accel of accel_tb is
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configuration TB_accel of accel_tb is
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for TB
|
for TB
|
for UUT : accel
|
for UUT : accel
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use entity wb_vga.accel(accel);
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use entity wb_vga.accel(accel);
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end for;
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end for;
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end for;
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end for;
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end TB_accel;
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end TB_accel;
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|
|
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