library ieee,wb_tk,wb_vga;
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library ieee,wb_tk,wb_vga;
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use ieee.NUMERIC_STD.all;
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use ieee.NUMERIC_STD.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use wb_tk.technology.all;
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use wb_tk.technology.all;
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use wb_tk.wb_test.all;
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use wb_tk.wb_test.all;
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use wb_tk.all;
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use wb_tk.all;
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use wb_vga.all;
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use wb_vga.all;
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entity wb_pal_ram_tb is
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entity wb_pal_ram_tb is
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generic(
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generic(
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cpu_dat_width: positive := 32;
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cpu_dat_width: positive := 32;
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cpu_adr_width: positive := 8;
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cpu_adr_width: positive := 8;
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v_dat_width: positive := 16;
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v_dat_width: positive := 16;
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v_adr_width: positive := 8
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v_adr_width: positive := 8
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);
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);
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end wb_pal_ram_tb;
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end wb_pal_ram_tb;
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architecture TB of wb_pal_ram_tb is
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architecture TB of wb_pal_ram_tb is
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component wb_pal_ram
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component wb_pal_ram
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generic (
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generic (
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cpu_dat_width: positive := cpu_dat_width;
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cpu_dat_width: positive := cpu_dat_width;
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cpu_adr_width: positive := cpu_adr_width;
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cpu_adr_width: positive := cpu_adr_width;
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v_dat_width: positive := v_dat_width;
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v_dat_width: positive := v_dat_width;
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v_adr_width: positive := v_adr_width
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v_adr_width: positive := v_adr_width
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);
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);
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port (
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port (
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-- Wishbone interface to CPU (write-only support)
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-- Wishbone interface to CPU (write-only support)
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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cyc_i: in std_logic;
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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ack_oi: in std_logic := '-';
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err_o: out std_logic;
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err_o: out std_logic;
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err_oi: in std_logic := '-';
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err_oi: in std_logic := '-';
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-- rty_o: out std_logic;
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-- rty_o: out std_logic;
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-- rty_oi: in std_logic := '-';
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-- rty_oi: in std_logic := '-';
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we_i: in std_logic;
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we_i: in std_logic;
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stb_i: in std_logic;
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stb_i: in std_logic;
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-- Interface to the video output
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-- Interface to the video output
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blank: in std_logic;
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blank: in std_logic;
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v_dat_i: in std_logic_vector(v_adr_width-1 downto 0);
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v_dat_i: in std_logic_vector(v_adr_width-1 downto 0);
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v_dat_o: out std_logic_vector(v_dat_width-1 downto 0)
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v_dat_o: out std_logic_vector(v_dat_width-1 downto 0)
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);
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);
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end component;
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end component;
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-- Wishbone interface to CPU (write-only support)
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-- Wishbone interface to CPU (write-only support)
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signal clk_i: std_logic;
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signal clk_i: std_logic;
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signal rst_i: std_logic := '0';
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signal rst_i: std_logic := '0';
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signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
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signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
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signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
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signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
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signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
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signal cyc_i: std_logic;
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signal cyc_i: std_logic;
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signal ack_o: std_logic;
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signal ack_o: std_logic;
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signal ack_oi: std_logic := '-';
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signal ack_oi: std_logic := '-';
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signal err_o: std_logic;
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signal err_o: std_logic;
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signal err_oi: std_logic := '-';
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signal err_oi: std_logic := '-';
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signal we_i: std_logic;
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signal we_i: std_logic;
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signal stb_i: std_logic;
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signal stb_i: std_logic;
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-- Interface to the video output
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-- Interface to the video output
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signal blank: std_logic;
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signal blank: std_logic;
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signal v_dat_i: std_logic_vector(v_adr_width-1 downto 0);
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signal v_dat_i: std_logic_vector(v_adr_width-1 downto 0);
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signal v_dat_o: std_logic_vector(v_dat_width-1 downto 0);
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signal v_dat_o: std_logic_vector(v_dat_width-1 downto 0);
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begin
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begin
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-- Unit Under Test port map
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-- Unit Under Test port map
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UUT : wb_pal_ram
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UUT : wb_pal_ram
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port map (
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port map (
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clk_i => clk_i,
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clk_i => clk_i,
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rst_i => rst_i,
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rst_i => rst_i,
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adr_i => adr_i,
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adr_i => adr_i,
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dat_i => dat_i,
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dat_i => dat_i,
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dat_oi => dat_oi,
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dat_oi => dat_oi,
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dat_o => dat_o,
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dat_o => dat_o,
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cyc_i => cyc_i,
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cyc_i => cyc_i,
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ack_o => ack_o,
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ack_o => ack_o,
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ack_oi => ack_oi,
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ack_oi => ack_oi,
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err_o => err_o,
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err_o => err_o,
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err_oi => err_oi,
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err_oi => err_oi,
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we_i => we_i,
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we_i => we_i,
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stb_i => stb_i,
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stb_i => stb_i,
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blank => blank,
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blank => blank,
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v_dat_i => v_dat_i,
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v_dat_i => v_dat_i,
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v_dat_o => v_dat_o
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v_dat_o => v_dat_o
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);
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);
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clk: process is
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clk: process is
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begin
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begin
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clk_i <= '0';
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clk_i <= '0';
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wait for 25ns;
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wait for 25ns;
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clk_i <= '1';
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clk_i <= '1';
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wait for 25ns;
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wait for 25ns;
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end process;
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end process;
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reset: process is
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reset: process is
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begin
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begin
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rst_i <= '1';
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rst_i <= '1';
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wait for 150ns;
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wait for 150ns;
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rst_i <= '0';
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rst_i <= '0';
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wait;
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wait;
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end process;
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end process;
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gen_v_output: process is
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gen_v_output: process is
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variable addr: std_logic_vector(v_adr_width-1 downto 0) := (others => '0');
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variable addr: std_logic_vector(v_adr_width-1 downto 0) := (others => '0');
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begin
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begin
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blank <= '0';
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blank <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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v_dat_i <= addr;
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v_dat_i <= addr;
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-- if (addr = "1111") then
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-- if (addr = "1111") then
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-- blank <= '1';
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-- blank <= '1';
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-- wait until clk_i'EVENT and clk_i = '1';
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-- wait until clk_i'EVENT and clk_i = '1';
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-- addr := (v_adr_width'RANGE => '0');
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-- addr := (v_adr_width'RANGE => '0');
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-- else
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-- else
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addr := add_one(addr);
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addr := add_one(addr);
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-- end if;
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-- end if;
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end process;
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end process;
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dat_oi <= (others => 'U');
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dat_oi <= (others => 'U');
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ack_oi <= 'U';
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ack_oi <= 'U';
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err_oi <= 'U';
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err_oi <= 'U';
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master: process is
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master: process is
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variable i: integer := 0;
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variable i: integer := 0;
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variable addr: std_logic_vector(cpu_adr_width-1 downto 0) := (others => '0');
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variable addr: std_logic_vector(cpu_adr_width-1 downto 0) := (others => '0');
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variable data: std_logic_vector(cpu_dat_width-1 downto 0) := (others => '0');
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variable data: std_logic_vector(cpu_dat_width-1 downto 0) := (others => '0');
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begin
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begin
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we_i <= '0';
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we_i <= '0';
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cyc_i <= '0';
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cyc_i <= '0';
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stb_i <= '0';
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stb_i <= '0';
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adr_i <= (others => '0');
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adr_i <= (others => '0');
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dat_i <= (others => '0');
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dat_i <= (others => '0');
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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for i in 0 to 511 loop
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for i in 0 to 511 loop
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,addr,data);
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wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,addr,data);
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addr := add_one(addr);
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addr := add_one(addr);
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data := add_one(data);
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data := add_one(data);
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end loop;
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end loop;
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wait;
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wait;
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end process;
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end process;
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end TB;
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end TB;
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configuration TB_wb_pal_ram of wb_pal_ram_tb is
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configuration TB_wb_pal_ram of wb_pal_ram_tb is
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for TB
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for TB
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for UUT : wb_pal_ram
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for UUT : wb_pal_ram
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use entity wb_vga.wb_pal_ram(wb_pal_ram);
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use entity wb_vga.wb_pal_ram(wb_pal_ram);
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end for;
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end for;
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end for;
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end for;
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end TB_wb_pal_ram;
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end TB_wb_pal_ram;
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