library ieee,exemplar;
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library ieee,exemplar;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use exemplar.exemplar_1164.all;
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use exemplar.exemplar_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library synopsys;
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library synopsys;
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use synopsys.std_logic_arith.all;
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use synopsys.std_logic_arith.all;
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library wb_tk;
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library wb_tk;
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use wb_tk.wb_test.all;
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use wb_tk.wb_test.all;
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library wb_vga;
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library wb_vga;
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use wb_vga.all;
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use wb_vga.all;
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use wb_vga.constants.all;
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use wb_vga.constants.all;
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entity vga_core_v2_tb is
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entity vga_core_v2_tb is
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generic (
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generic (
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v_dat_width: positive := 16;
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v_dat_width: positive := 16;
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v_adr_width : positive := 12;
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v_adr_width : positive := 12;
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cpu_dat_width: positive := 8;
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cpu_dat_width: positive := 8;
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cpu_adr_width: positive := 12;
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cpu_adr_width: positive := 12;
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-- cpu_dat_width: positive := 16;
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-- cpu_dat_width: positive := 16;
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-- cpu_adr_width: positive := 11;
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-- cpu_adr_width: positive := 11;
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fifo_size: positive := 256;
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fifo_size: positive := 256;
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accel_size: positive := 9;
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accel_size: positive := 9;
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v_pal_size: positive := 8;
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v_pal_size: positive := 8;
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v_pal_width: positive := 16
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v_pal_width: positive := 16
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);
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);
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end vga_core_v2_tb;
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end vga_core_v2_tb;
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architecture TB of vga_core_v2_tb is
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architecture TB of vga_core_v2_tb is
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-- Component declaration of the tested unit
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-- Component declaration of the tested unit
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component vga_core_v2
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component vga_core_v2
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generic (
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generic (
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v_dat_width: positive := v_dat_width;
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v_dat_width: positive := v_dat_width;
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v_adr_width : positive := v_adr_width;
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v_adr_width : positive := v_adr_width;
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cpu_dat_width: positive := cpu_dat_width;
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cpu_dat_width: positive := cpu_dat_width;
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cpu_adr_width: positive := cpu_adr_width;
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cpu_adr_width: positive := cpu_adr_width;
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fifo_size: positive := fifo_size;
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fifo_size: positive := fifo_size;
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accel_size: positive := accel_size;
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accel_size: positive := accel_size;
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v_pal_size: positive := v_pal_size;
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v_pal_size: positive := v_pal_size;
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v_pal_width: positive := v_pal_width
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v_pal_width: positive := v_pal_width
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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clk_en: in std_logic := '1';
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- CPU bus interface
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-- CPU bus interface
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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cyc_i: in std_logic;
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic;
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ack_oi: in std_logic;
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err_o: out std_logic;
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err_o: out std_logic;
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err_oi: in std_logic;
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err_oi: in std_logic;
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we_i: in std_logic;
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we_i: in std_logic;
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accel_stb_i: in std_logic;
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accel_stb_i: in std_logic;
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pal_stb_i: in std_logic;
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pal_stb_i: in std_logic;
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reg_stb_i: in std_logic;
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reg_stb_i: in std_logic;
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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-- video memory interface
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-- video memory interface
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v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
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v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
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v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
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v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
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v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
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v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
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v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
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v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
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v_cyc_o: out std_logic;
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v_cyc_o: out std_logic;
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v_ack_i: in std_logic;
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v_ack_i: in std_logic;
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v_we_o: out std_logic;
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v_we_o: out std_logic;
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v_stb_o: out std_logic;
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v_stb_o: out std_logic;
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-- sync blank and video signal outputs
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_sync: out std_logic;
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h_blank: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
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video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
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true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output
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true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output
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);
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);
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end component;
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end component;
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signal clk_i: std_logic;
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signal clk_i: std_logic;
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signal clk_en: std_logic := '1';
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signal clk_en: std_logic := '1';
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signal rst_i: std_logic := '0';
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signal rst_i: std_logic := '0';
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-- CPU bus interface
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-- CPU bus interface
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signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
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signal cyc_i: std_logic;
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signal cyc_i: std_logic;
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signal ack_o: std_logic;
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signal ack_o: std_logic;
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signal ack_oi: std_logic;
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signal ack_oi: std_logic;
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signal err_o: std_logic;
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signal err_o: std_logic;
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signal err_oi: std_logic;
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signal err_oi: std_logic;
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signal we_i: std_logic;
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signal we_i: std_logic;
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signal accel_stb_i: std_logic;
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signal accel_stb_i: std_logic;
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signal pal_stb_i: std_logic;
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signal pal_stb_i: std_logic;
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signal reg_stb_i: std_logic;
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signal reg_stb_i: std_logic;
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signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
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signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
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signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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-- video memory interface
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-- video memory interface
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signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0);
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signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0);
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signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0);
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signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0);
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signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0);
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signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0);
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signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0);
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signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0);
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signal v_cyc_o: std_logic;
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signal v_cyc_o: std_logic;
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signal v_ack_i: std_logic;
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signal v_ack_i: std_logic;
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signal v_we_o: std_logic;
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signal v_we_o: std_logic;
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signal v_stb_o: std_logic;
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signal v_stb_o: std_logic;
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-- sync blank and video signal outputs
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-- sync blank and video signal outputs
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signal h_sync: std_logic;
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signal h_sync: std_logic;
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signal h_blank: std_logic;
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signal h_blank: std_logic;
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signal v_sync: std_logic;
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signal v_sync: std_logic;
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signal v_blank: std_logic;
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signal v_blank: std_logic;
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signal h_tc: std_logic;
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signal h_tc: std_logic;
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signal v_tc: std_logic;
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signal v_tc: std_logic;
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signal blank: std_logic;
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signal blank: std_logic;
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signal video_out: std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
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signal video_out: std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
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signal true_color_out: std_logic_vector (v_pal_width-1 downto 0); -- true-color video output
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signal true_color_out: std_logic_vector (v_pal_width-1 downto 0); -- true-color video output
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constant reg_total0 : integer := 0;
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constant reg_total0 : integer := 0;
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constant reg_total1 : integer := 1;
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constant reg_total1 : integer := 1;
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constant reg_total2 : integer := 2;
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constant reg_total2 : integer := 2;
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constant reg_total3 : integer := 3;
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constant reg_total3 : integer := 3;
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constant reg_ofs0 : integer := 4;
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constant reg_ofs0 : integer := 4;
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constant reg_ofs1 : integer := 5;
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constant reg_ofs1 : integer := 5;
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constant reg_ofs2 : integer := 6;
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constant reg_ofs2 : integer := 6;
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constant reg_ofs3 : integer := 7;
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constant reg_ofs3 : integer := 7;
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constant reg_fifo_treshold : integer := 16;
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constant reg_fifo_treshold : integer := 16;
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constant reg_bpp : integer := 17;
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constant reg_bpp : integer := 17;
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constant reg_hbs : integer := 18;
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constant reg_hbs : integer := 18;
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constant reg_hss : integer := 19;
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constant reg_hss : integer := 19;
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constant reg_hse : integer := 20;
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constant reg_hse : integer := 20;
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constant reg_htotal : integer := 21;
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constant reg_htotal : integer := 21;
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constant reg_vbs : integer := 22;
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constant reg_vbs : integer := 22;
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constant reg_vss : integer := 23;
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constant reg_vss : integer := 23;
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constant reg_vse : integer := 24;
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constant reg_vse : integer := 24;
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constant reg_vtotal : integer := 25;
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constant reg_vtotal : integer := 25;
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constant reg_pps : integer := 26;
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constant reg_pps : integer := 26;
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constant reg_sync_pol : integer := 27;
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constant reg_sync_pol : integer := 27;
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constant reg_ws : integer := 32;
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constant reg_ws : integer := 32;
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constant reg_cur : integer := 40;
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constant reg_cur : integer := 40;
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constant reg_ext : integer := 44;
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constant reg_ext : integer := 44;
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constant val_total0 : std_logic_vector(7 downto 0) := "11111111";
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constant val_total0 : std_logic_vector(7 downto 0) := "11111111";
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constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
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constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
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constant val_total2 : std_logic_vector(7 downto 0) := "00000000";
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constant val_total2 : std_logic_vector(7 downto 0) := "00000000";
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constant val_total3 : std_logic_vector(7 downto 0) := "00000000";
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constant val_total3 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs0 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs0 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs1 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs1 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs2 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs2 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs3 : std_logic_vector(7 downto 0) := "00000000";
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constant val_ofs3 : std_logic_vector(7 downto 0) := "00000000";
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constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
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constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
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constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
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constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
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constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
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constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
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constant val_hss : std_logic_vector(7 downto 0) := "00001000";
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constant val_hss : std_logic_vector(7 downto 0) := "00001000";
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constant val_hse : std_logic_vector(7 downto 0) := "00001001";
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constant val_hse : std_logic_vector(7 downto 0) := "00001001";
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constant val_htotal : std_logic_vector(7 downto 0) := "00001010";
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constant val_htotal : std_logic_vector(7 downto 0) := "00001010";
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constant val_vbs : std_logic_vector(7 downto 0) := "00000001";
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constant val_vbs : std_logic_vector(7 downto 0) := "00000001";
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constant val_vss : std_logic_vector(7 downto 0) := "00000010";
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constant val_vss : std_logic_vector(7 downto 0) := "00000010";
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constant val_vse : std_logic_vector(7 downto 0) := "00000011";
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constant val_vse : std_logic_vector(7 downto 0) := "00000011";
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constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
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constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
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constant val_pps : std_logic_vector(7 downto 0) := "00000001";
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constant val_pps : std_logic_vector(7 downto 0) := "00000001";
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constant val_sync_pol : std_logic_vector(7 downto 0) := "10000000";
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constant val_sync_pol : std_logic_vector(7 downto 0) := "10000000";
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constant val_ws : std_logic_vector(7 downto 0) := "00000010";
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constant val_ws : std_logic_vector(7 downto 0) := "00000010";
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type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type
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type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type
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signal mem_data : data_array(0 to (2** v_adr_width-1) ); -- Local data
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signal mem_data : data_array(0 to (2** v_adr_width-1) ); -- Local data
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begin
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begin
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UUT : vga_core_v2
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UUT : vga_core_v2
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port map (
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port map (
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clk_i =>clk_i,
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clk_i =>clk_i,
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clk_en =>clk_en,
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clk_en =>clk_en,
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rst_i =>rst_i,
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rst_i =>rst_i,
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|
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-- CPU bus interface
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-- CPU bus interface
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dat_i =>dat_i,
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dat_i =>dat_i,
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dat_oi =>dat_oi,
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dat_oi =>dat_oi,
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dat_o =>dat_o,
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dat_o =>dat_o,
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cyc_i =>cyc_i,
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cyc_i =>cyc_i,
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ack_o =>ack_o,
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ack_o =>ack_o,
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ack_oi =>ack_oi,
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ack_oi =>ack_oi,
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err_o =>err_o,
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err_o =>err_o,
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err_oi =>err_oi,
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err_oi =>err_oi,
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we_i =>we_i,
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we_i =>we_i,
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accel_stb_i =>accel_stb_i,
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accel_stb_i =>accel_stb_i,
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pal_stb_i =>pal_stb_i,
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pal_stb_i =>pal_stb_i,
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reg_stb_i =>reg_stb_i,
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reg_stb_i =>reg_stb_i,
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adr_i =>adr_i,
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adr_i =>adr_i,
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sel_i =>sel_i,
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sel_i =>sel_i,
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|
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-- video memory interface
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-- video memory interface
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v_adr_o =>v_adr_o,
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v_adr_o =>v_adr_o,
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v_sel_o =>v_sel_o,
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v_sel_o =>v_sel_o,
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v_dat_i =>v_dat_i,
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v_dat_i =>v_dat_i,
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v_dat_o =>v_dat_o,
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v_dat_o =>v_dat_o,
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v_cyc_o =>v_cyc_o,
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v_cyc_o =>v_cyc_o,
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v_ack_i =>v_ack_i,
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v_ack_i =>v_ack_i,
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v_we_o =>v_we_o,
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v_we_o =>v_we_o,
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v_stb_o =>v_stb_o,
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v_stb_o =>v_stb_o,
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|
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-- sync blank and video outputs
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-- sync blank and video outputs
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h_sync =>h_sync,
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h_sync =>h_sync,
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h_blank =>h_blank,
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h_blank =>h_blank,
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v_sync =>v_sync,
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v_sync =>v_sync,
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v_blank =>v_blank,
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v_blank =>v_blank,
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h_tc =>h_tc,
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h_tc =>h_tc,
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v_tc =>v_tc,
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v_tc =>v_tc,
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blank =>blank,
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blank =>blank,
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video_out =>video_out,
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video_out =>video_out,
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true_color_out=>true_color_out
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true_color_out=>true_color_out
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);
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);
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|
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-- Add your stimulus here ...
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-- Add your stimulus here ...
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|
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clk_en <= '1';
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clk_en <= '1';
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-- Add your stimulus here ...
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-- Add your stimulus here ...
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clock: process is
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clock: process is
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begin
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begin
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wait for 25 ns;
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wait for 25 ns;
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clk_i <= '1';
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clk_i <= '1';
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wait for 25 ns;
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wait for 25 ns;
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clk_i <= '0';
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clk_i <= '0';
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end process;
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end process;
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|
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ack_oi <= '1';
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ack_oi <= '1';
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err_oi <= '1';
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err_oi <= '1';
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dat_oi <= (others => '0');
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dat_oi <= (others => '0');
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|
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setup: process is
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setup: process is
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begin
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begin
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sel_i <= (others => '1');
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sel_i <= (others => '1');
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we_i <= '0';
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we_i <= '0';
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reg_stb_i <= '0';
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reg_stb_i <= '0';
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accel_stb_i <= '0';
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accel_stb_i <= '0';
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pal_stb_i <= '0';
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pal_stb_i <= '0';
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cyc_i <= '0';
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cyc_i <= '0';
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rst_i <= '1';
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rst_i <= '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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rst_i <= '0';
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rst_i <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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|
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if (cpu_dat_width = 8) then
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if (cpu_dat_width = 8) then
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
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wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
|
|
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
|
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol);
|
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"00000001");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"00000001");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"00000010");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"00000010");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"00000100");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"00000100");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"00001000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"00001000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"00010000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"00010000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"00100000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"00100000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"01000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"01000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"10000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"10000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,16 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,16 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,17 ,"00000001");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,17 ,"00000001");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,18 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,18 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,19 ,"00000010");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,19 ,"00000010");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,20 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,20 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,21 ,"00000100");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,21 ,"00000100");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,22 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,22 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,23 ,"00001000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,23 ,"00001000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,24 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,24 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,25 ,"00010000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,25 ,"00010000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,26 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,26 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,27 ,"00100000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,27 ,"00100000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,28 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,28 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,29 ,"01000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,29 ,"01000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,30 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,30 ,"00000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,31 ,"10000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,31 ,"10000000");
|
end if;
|
end if;
|
if (cpu_dat_width = 16) then
|
if (cpu_dat_width = 16) then
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/2 ,val_total1 & val_total0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/2 ,val_total1 & val_total0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2/2 ,val_total3 & val_total2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2/2 ,val_total3 & val_total2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/2 ,val_ofs1 & val_ofs0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/2 ,val_ofs1 & val_ofs0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2/2 ,val_ofs3 & val_ofs2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2/2 ,val_ofs3 & val_ofs2);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/2 ,"00000000" & val_ws );
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/2 ,"00000000" & val_ws );
|
|
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
|
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/2 ,val_bpp & val_fifo_treshold);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/2 ,val_bpp & val_fifo_treshold);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs/2 ,val_hss & val_hbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs/2 ,val_hss & val_hbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/2 ,val_htotal & val_hse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/2 ,val_htotal & val_hse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs/2 ,val_vss & val_vbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs/2 ,val_vss & val_vbs);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/2 ,val_vtotal & val_vse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/2 ,val_vtotal & val_vse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps/2 ,val_sync_pol & val_pps);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps/2 ,val_sync_pol & val_pps);
|
|
|
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"0000000000000001");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"0000000000000001");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"0000000000000010");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"0000000000000010");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"0000000000000100");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"0000000000000100");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"0000000000001000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"0000000000001000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"0000000000010000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"0000000000010000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"0000000000100000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"0000000000100000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"0000000001000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"0000000001000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"0000000010000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"0000000010000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"0000000100000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"0000000100000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"0000001000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"0000001000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"0000010000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"0000010000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"0000100000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"0000100000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"0001000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"0001000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"0010000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"0010000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"0100000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"0100000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"1000000000000000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"1000000000000000");
|
|
|
wait for 90us;
|
wait for 90us;
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
|
|
-- Set Cursor to 0
|
-- Set Cursor to 0
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2 ,"0000000000000000");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2 ,"0000000000000000");
|
-- Accel index 0 is 0
|
-- Accel index 0 is 0
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,0,"0000000000000000");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,0,"0000000000000000");
|
-- Accel index 1 is 1
|
-- Accel index 1 is 1
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,1,"0000000000000001");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,1,"0000000000000001");
|
-- Accel index 2 is 3
|
-- Accel index 2 is 3
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2,"0000000000000011");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2,"0000000000000011");
|
-- Accel index 3 is -1
|
-- Accel index 3 is -1
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,3,"1111111111111111");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,3,"1111111111111111");
|
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000001");
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000001");
|
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000001000");
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000001000");
|
|
|
-- Set Cursor to 16
|
-- Set Cursor to 16
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010000");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010000");
|
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010001");
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010001");
|
|
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
|
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000011000");
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000011000");
|
|
|
-- Set Cursor to 0
|
-- Set Cursor to 0
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000000");
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000000");
|
|
|
|
|
end if;
|
end if;
|
if (cpu_dat_width = 32) then
|
if (cpu_dat_width = 32) then
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/4 ,val_total3 & val_total2 & val_total1 & val_total0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/4 ,val_total3 & val_total2 & val_total1 & val_total0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/4 ,val_ofs3 & val_ofs2 & val_ofs1 & val_ofs0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/4 ,val_ofs3 & val_ofs2 & val_ofs1 & val_ofs0);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/4 ,"000000000000000000000000" & val_ws );
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/4 ,"000000000000000000000000" & val_ws );
|
|
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
|
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/4 ,val_hss & val_hbs & val_bpp & val_fifo_treshold);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/4 ,val_hss & val_hbs & val_bpp & val_fifo_treshold);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/4 ,val_vss & val_vbs & val_htotal & val_hse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/4 ,val_vss & val_vbs & val_htotal & val_hse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/4 ,val_sync_pol & val_pps & val_vtotal & val_vse);
|
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/4 ,val_sync_pol & val_pps & val_vtotal & val_vse);
|
end if;
|
end if;
|
|
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
|
|
ram: process is
|
ram: process is
|
-- type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type
|
-- type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type
|
-- variable data : data_array(0 to (2** v_adr_width-1) ); -- Local data
|
-- variable data : data_array(0 to (2** v_adr_width-1) ); -- Local data
|
variable init: boolean := true;
|
variable init: boolean := true;
|
begin
|
begin
|
if (init) then
|
if (init) then
|
for i in mem_data'RANGE loop
|
for i in mem_data'RANGE loop
|
mem_data(i) <= CONV_STD_LOGIC_VECTOR(i,v_dat_width);
|
mem_data(i) <= CONV_STD_LOGIC_VECTOR(i,v_dat_width);
|
-- data(i) := (others => '0');
|
-- data(i) := (others => '0');
|
end loop;
|
end loop;
|
init := false;
|
init := false;
|
end if;
|
end if;
|
|
|
wait on clk_i, v_cyc_o, v_stb_o, v_we_o, v_dat_o;
|
wait on clk_i, v_cyc_o, v_stb_o, v_we_o, v_dat_o;
|
if (v_cyc_o = '1' and v_stb_o = '1') then
|
if (v_cyc_o = '1' and v_stb_o = '1') then
|
v_ack_i <= '1';
|
v_ack_i <= '1';
|
else
|
else
|
v_ack_i <= '0';
|
v_ack_i <= '0';
|
end if;
|
end if;
|
|
|
if (clk_i'EVENT and clk_i = '1' and v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '1') then
|
if (clk_i'EVENT and clk_i = '1' and v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '1') then
|
mem_data(CONV_INTEGER(v_adr_o)) <= v_dat_o;
|
mem_data(CONV_INTEGER(v_adr_o)) <= v_dat_o;
|
v_dat_i <= (others => 'U');
|
v_dat_i <= (others => 'U');
|
elsif (v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '0') then
|
elsif (v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '0') then
|
v_dat_i <= mem_data(CONV_INTEGER(v_adr_o));
|
v_dat_i <= mem_data(CONV_INTEGER(v_adr_o));
|
-- v_dat_i <= v_adr_o(v_dat_i'RANGE);
|
-- v_dat_i <= v_adr_o(v_dat_i'RANGE);
|
else
|
else
|
v_dat_i <= (others => 'U');
|
v_dat_i <= (others => 'U');
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end TB;
|
end TB;
|
|
|
|
|
