--
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--
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-- Wishbone bus toolkit.
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-- Wishbone bus toolkit.
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--
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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--
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--
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-- ELEMENTS:
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-- ELEMENTS:
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-- wb_async_master: async bus master to Wishbone bus bridge.
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-- wb_async_master: async bus master to Wishbone bus bridge.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- wb_async_master
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-- wb_async_master
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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library wb_tk;
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use wb_tk.technology.all;
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use wb_tk.technology.all;
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entity wb_async_master is
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entity wb_async_master is
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generic (
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generic (
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width: positive := 16;
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width: positive := 16;
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addr_width: positive := 20
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addr_width: positive := 20
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- interface to wb slave devices
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-- interface to wb slave devices
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s_adr_o: out std_logic_vector (addr_width-1 downto 0);
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s_adr_o: out std_logic_vector (addr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
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s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (width-1 downto 0);
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s_dat_i: in std_logic_vector (width-1 downto 0);
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s_dat_o: out std_logic_vector (width-1 downto 0);
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s_dat_o: out std_logic_vector (width-1 downto 0);
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s_cyc_o: out std_logic;
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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s_stb_o: out std_logic;
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-- interface to asyncron master device
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-- interface to asyncron master device
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_rdn: in std_logic := '1';
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a_rdn: in std_logic := '1';
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a_wrn: in std_logic := '1';
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a_wrn: in std_logic := '1';
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a_cen: in std_logic := '1';
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a_cen: in std_logic := '1';
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a_byen: in std_logic_vector ((width/8)-1 downto 0);
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a_byen: in std_logic_vector ((width/8)-1 downto 0);
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a_waitn: out std_logic
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a_waitn: out std_logic
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);
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);
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end wb_async_master;
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end wb_async_master;
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architecture wb_async_master of wb_async_master is
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architecture wb_async_master of wb_async_master is
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component d_ff
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component d_ff
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port ( d : in STD_LOGIC;
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port ( d : in STD_LOGIC;
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clk: in STD_LOGIC;
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clk: in STD_LOGIC;
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ena: in STD_LOGIC := '1';
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ena: in STD_LOGIC := '1';
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clr: in STD_LOGIC := '0';
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clr: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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q : out STD_LOGIC
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q : out STD_LOGIC
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);
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);
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end component;
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end component;
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signal wg_clk, wg_pre, wg_q: std_logic;
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signal wg_clk, wg_pre, wg_q: std_logic;
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signal i_cyc_o, i_stb_o, i_we_o: std_logic;
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signal i_cyc_o, i_stb_o, i_we_o: std_logic;
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signal i_waitn: std_logic;
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signal i_waitn: std_logic;
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begin
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begin
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ctrl: process is
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ctrl: process is
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begin
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begin
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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if (rst_i = '1') then
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if (rst_i = '1') then
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i_cyc_o <= '0';
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i_cyc_o <= '0';
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i_stb_o <= '0';
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i_stb_o <= '0';
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i_we_o <= '0';
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i_we_o <= '0';
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else
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else
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if (a_cen = '0') then
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if (a_cen = '0') then
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i_stb_o <= not (a_rdn and a_wrn);
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i_stb_o <= not (a_rdn and a_wrn);
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i_we_o <= not a_wrn;
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i_we_o <= not a_wrn;
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i_cyc_o <= '1';
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i_cyc_o <= '1';
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else
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else
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i_cyc_o <= '0';
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i_cyc_o <= '0';
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i_stb_o <= '0';
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i_stb_o <= '0';
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i_we_o <= '0';
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i_we_o <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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s_cyc_o <= i_cyc_o and not i_waitn;
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s_cyc_o <= i_cyc_o and not i_waitn;
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s_stb_o <= i_stb_o and not i_waitn;
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s_stb_o <= i_stb_o and not i_waitn;
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s_we_o <= i_we_o and not i_waitn;
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s_we_o <= i_we_o and not i_waitn;
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w_ff1: d_ff port map (
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w_ff1: d_ff port map (
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d => s_ack_i,
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d => s_ack_i,
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clk => clk_i,
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clk => clk_i,
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ena => '1',
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ena => '1',
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clr => rst_i,
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clr => rst_i,
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pre => '0',
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pre => '0',
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q => wg_q
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q => wg_q
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);
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);
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wg_clk <= not a_cen;
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wg_clk <= not a_cen;
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wg_pre <= wg_q or rst_i;
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wg_pre <= wg_q or rst_i;
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w_ff2: d_ff port map (
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w_ff2: d_ff port map (
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d => '0',
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d => '0',
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clk => wg_clk,
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clk => wg_clk,
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ena => '1',
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ena => '1',
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clr => '0',
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clr => '0',
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pre => wg_pre,
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pre => wg_pre,
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q => i_waitn
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q => i_waitn
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);
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);
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a_waitn <= i_waitn;
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a_waitn <= i_waitn;
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s_adr_o <= a_addr;
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s_adr_o <= a_addr;
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negate: for i in s_sel_o'RANGE generate s_sel_o(i) <= not a_byen(i); end generate;
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negate: for i in s_sel_o'RANGE generate s_sel_o(i) <= not a_byen(i); end generate;
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s_dat_o <= a_data;
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s_dat_o <= a_data;
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a_data_out: process is
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a_data_out: process is
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begin
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begin
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wait on s_dat_i, a_rdn, a_cen;
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wait on s_dat_i, a_rdn, a_cen;
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if (a_rdn = '0' and a_cen = '0') then
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if (a_rdn = '0' and a_cen = '0') then
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a_data <= s_dat_i;
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a_data <= s_dat_i;
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else
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else
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a_data <= (others => 'Z');
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a_data <= (others => 'Z');
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end if;
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end if;
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end process;
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end process;
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end wb_async_master;
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end wb_async_master;
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