--
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--
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-- Wishbone bus toolkit.
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-- Wishbone bus toolkit.
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--
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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--
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--
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-- ELEMENTS:
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-- ELEMENTS:
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-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
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-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- wb_async_slave
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-- wb_async_slave
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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library wb_tk;
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use wb_tk.technology.all;
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use wb_tk.technology.all;
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entity wb_async_slave is
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entity wb_async_slave is
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generic (
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generic (
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width: positive := 16;
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width: positive := 16;
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addr_width: positive := 20
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addr_width: positive := 20
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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rst_i: in std_logic := '0';
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-- interface for wait-state generator state-machine
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-- interface for wait-state generator state-machine
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wait_state: in std_logic_vector (3 downto 0);
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wait_state: in std_logic_vector (3 downto 0);
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-- interface to wishbone master device
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-- interface to wishbone master device
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
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sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
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dat_i: in std_logic_vector (width-1 downto 0);
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dat_i: in std_logic_vector (width-1 downto 0);
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dat_o: out std_logic_vector (width-1 downto 0);
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dat_o: out std_logic_vector (width-1 downto 0);
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dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
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dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
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we_i: in std_logic;
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we_i: in std_logic;
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stb_i: in std_logic;
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stb_i: in std_logic;
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ack_o: out std_logic := '0';
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ack_o: out std_logic := '0';
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ack_oi: in std_logic := '-';
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ack_oi: in std_logic := '-';
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-- interface to async slave
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-- interface to async slave
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_rdn: out std_logic := '1';
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a_rdn: out std_logic := '1';
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a_wrn: out std_logic := '1';
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a_wrn: out std_logic := '1';
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a_cen: out std_logic := '1';
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a_cen: out std_logic := '1';
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-- byte-enable signals
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-- byte-enable signals
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a_byen: out std_logic_vector ((width/8)-1 downto 0)
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a_byen: out std_logic_vector ((width/8)-1 downto 0)
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);
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);
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end wb_async_slave;
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end wb_async_slave;
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architecture wb_async_slave of wb_async_slave is
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architecture wb_async_slave of wb_async_slave is
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-- multiplexed access signals to memory
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-- multiplexed access signals to memory
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signal i_ack: std_logic;
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signal i_ack: std_logic;
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signal sm_ack: std_logic;
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signal sm_ack: std_logic;
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type states is (sm_idle, sm_wait, sm_deact);
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type states is (sm_idle, sm_wait, sm_deact);
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signal state: states;
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signal state: states;
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signal cnt: std_logic_vector(3 downto 0);
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signal cnt: std_logic_vector(3 downto 0);
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begin
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begin
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ack_o <= (stb_i and i_ack) or (not stb_i and ack_oi);
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ack_o <= (stb_i and i_ack) or (not stb_i and ack_oi);
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dat_o_gen: for i in dat_o'RANGE generate
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dat_o_gen: for i in dat_o'RANGE generate
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dat_o(i) <= (stb_i and a_data(i)) or (not stb_i and dat_oi(i));
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dat_o(i) <= (stb_i and a_data(i)) or (not stb_i and dat_oi(i));
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end generate;
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end generate;
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-- For 0WS operation i_ack is an async signal otherwise it's a sync one.
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-- For 0WS operation i_ack is an async signal otherwise it's a sync one.
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i_ack_gen: process is
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i_ack_gen: process is
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begin
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begin
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wait on sm_ack, stb_i, wait_state, state;
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wait on sm_ack, stb_i, wait_state, state;
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if (wait_state = "0000") then
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if (wait_state = "0000") then
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case (state) is
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case (state) is
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when sm_deact => i_ack <= '0';
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when sm_deact => i_ack <= '0';
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when others => i_ack <= stb_i;
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when others => i_ack <= stb_i;
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end case;
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end case;
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else
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else
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i_ack <= sm_ack;
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i_ack <= sm_ack;
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end if;
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end if;
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end process;
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end process;
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-- SRAM signal-handler process
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-- SRAM signal-handler process
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sram_signals: process is
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sram_signals: process is
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begin
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begin
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wait on state,we_i,a_data,adr_i,rst_i, stb_i, sel_i, dat_i;
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wait on state,we_i,a_data,adr_i,rst_i, stb_i, sel_i, dat_i;
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if (rst_i = '1') then
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if (rst_i = '1') then
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a_wrn <= '1';
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a_wrn <= '1';
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a_rdn <= '1';
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a_rdn <= '1';
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a_cen <= '1';
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a_cen <= '1';
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a_addr <= (others => '-');
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a_addr <= (others => '-');
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a_data <= (others => 'Z');
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a_data <= (others => 'Z');
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a_byen <= (others => '1');
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a_byen <= (others => '1');
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else
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else
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case (state) is
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case (state) is
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when sm_deact =>
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when sm_deact =>
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a_wrn <= '1';
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a_wrn <= '1';
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a_rdn <= '1';
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a_rdn <= '1';
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a_cen <= '1';
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a_cen <= '1';
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a_addr <= (others => '-');
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a_addr <= (others => '-');
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a_data <= (others => 'Z');
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a_data <= (others => 'Z');
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a_byen <= (others => '1');
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a_byen <= (others => '1');
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when others =>
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when others =>
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a_addr <= adr_i;
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a_addr <= adr_i;
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a_rdn <= not (not we_i and stb_i);
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a_rdn <= not (not we_i and stb_i);
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a_wrn <= not (we_i and stb_i);
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a_wrn <= not (we_i and stb_i);
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a_cen <= not stb_i;
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a_cen <= not stb_i;
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a_byen <= not sel_i;
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a_byen <= not sel_i;
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if (we_i = '1') then
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if (we_i = '1') then
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a_data <= dat_i;
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a_data <= dat_i;
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else
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else
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a_data <= (others => 'Z');
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a_data <= (others => 'Z');
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- Aysnc access state-machine.
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-- Aysnc access state-machine.
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async_sm: process is
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async_sm: process is
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-- variable cnt: std_logic_vector(3 downto 0) := "0000";
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-- variable cnt: std_logic_vector(3 downto 0) := "0000";
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-- variable state: states := init;
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-- variable state: states := init;
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begin
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begin
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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if (rst_i = '1') then
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if (rst_i = '1') then
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state <= sm_idle;
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state <= sm_idle;
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cnt <= ((0) => '1', others => '0');
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cnt <= ((0) => '1', others => '0');
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sm_ack <= '0';
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sm_ack <= '0';
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else
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else
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case (state) is
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case (state) is
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when sm_idle =>
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when sm_idle =>
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-- Check if anyone needs access to the memory.
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-- Check if anyone needs access to the memory.
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-- it's rdy signal will already be pulled low, so we only have to start the access
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-- it's rdy signal will already be pulled low, so we only have to start the access
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if (stb_i = '1') then
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if (stb_i = '1') then
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case wait_state is
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case wait_state is
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when "0000" =>
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when "0000" =>
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sm_ack <= '1';
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sm_ack <= '1';
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state <= sm_deact;
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state <= sm_deact;
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when "0001" =>
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when "0001" =>
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sm_ack <= '1';
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sm_ack <= '1';
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cnt <= "0001";
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cnt <= "0001";
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state <= sm_wait;
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state <= sm_wait;
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when others =>
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when others =>
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sm_ack <= '0';
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sm_ack <= '0';
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cnt <= "0001";
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cnt <= "0001";
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state <= sm_wait;
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state <= sm_wait;
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end case;
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end case;
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end if;
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end if;
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when sm_wait =>
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when sm_wait =>
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if (cnt = wait_state) then
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if (cnt = wait_state) then
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-- wait cycle completed.
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-- wait cycle completed.
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state <= sm_deact;
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state <= sm_deact;
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sm_ack <= '0';
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sm_ack <= '0';
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cnt <= "0000";
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cnt <= "0000";
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else
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else
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if (add_one(cnt) = wait_state) then
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if (add_one(cnt) = wait_state) then
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sm_ack <= '1';
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sm_ack <= '1';
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else
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else
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sm_ack <= '0';
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sm_ack <= '0';
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end if;
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end if;
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cnt <= add_one(cnt);
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cnt <= add_one(cnt);
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end if;
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end if;
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when sm_deact =>
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when sm_deact =>
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if (stb_i = '1') then
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if (stb_i = '1') then
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case wait_state is
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case wait_state is
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when "0000" =>
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when "0000" =>
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cnt <= "0000";
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cnt <= "0000";
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sm_ack <= '0';
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sm_ack <= '0';
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state <= sm_wait;
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state <= sm_wait;
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when others =>
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when others =>
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sm_ack <= '0';
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sm_ack <= '0';
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cnt <= "0000";
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cnt <= "0000";
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state <= sm_wait;
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state <= sm_wait;
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end case;
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end case;
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else
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else
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sm_ack <= '0';
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sm_ack <= '0';
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state <= sm_idle;
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state <= sm_idle;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end wb_async_slave;
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end wb_async_slave;
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