--
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--
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-- Wishbone bus toolkit.
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-- Wishbone bus toolkit.
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--
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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--
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--
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-- ELEMENTS:
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-- ELEMENTS:
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-- wb_ram: ram element.
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-- wb_ram: ram element.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- wb_ram
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-- wb_ram
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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library wb_tk;
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use wb_tk.technology.all;
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use wb_tk.technology.all;
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entity wb_ram is
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entity wb_ram is
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generic (
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generic (
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data_width: positive := 8;
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data_width: positive := 8;
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addr_width: positive := 10
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addr_width: positive := 10
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);
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);
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port (
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port (
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clk_i: in std_logic;
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clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- rst_i: in std_logic := '0';
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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-- sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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-- sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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dat_i: in std_logic_vector (data_width-1 downto 0);
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dat_i: in std_logic_vector (data_width-1 downto 0);
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dat_oi: in std_logic_vector (data_width-1 downto 0) := (others => '-');
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dat_oi: in std_logic_vector (data_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (data_width-1 downto 0);
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dat_o: out std_logic_vector (data_width-1 downto 0);
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cyc_i: in std_logic;
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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ack_oi: in std_logic := '-';
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-- err_o: out std_logic;
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-- err_o: out std_logic;
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-- err_oi: in std_logic := '-';
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-- err_oi: in std_logic := '-';
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-- rty_o: out std_logic;
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-- rty_o: out std_logic;
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-- rty_oi: in std_logic := '-';
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-- rty_oi: in std_logic := '-';
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we_i: in std_logic;
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we_i: in std_logic;
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stb_i: in std_logic
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stb_i: in std_logic
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);
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);
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end wb_ram;
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end wb_ram;
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architecture wb_ram of wb_ram is
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architecture wb_ram of wb_ram is
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component ram
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component ram
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generic (
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generic (
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data_width : positive;
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data_width : positive;
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addr_width : positive
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addr_width : positive
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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we : in std_logic;
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addr : in std_logic_vector(addr_width-1 downto 0);
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addr : in std_logic_vector(addr_width-1 downto 0);
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d_in : in std_logic_vector(data_width-1 downto 0);
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d_in : in std_logic_vector(data_width-1 downto 0);
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d_out : out std_logic_vector(data_width-1 downto 0)
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d_out : out std_logic_vector(data_width-1 downto 0)
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);
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);
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end component;
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end component;
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signal mem_we: std_logic;
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signal mem_we: std_logic;
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signal mem_dat_o: std_logic_vector(data_width-1 downto 0);
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signal mem_dat_o: std_logic_vector(data_width-1 downto 0);
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begin
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begin
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mem_we <= we_i and stb_i and cyc_i;
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mem_we <= we_i and stb_i and cyc_i;
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tech_ram: ram
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tech_ram: ram
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generic map (
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generic map (
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data_width => data_width,
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data_width => data_width,
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addr_width => addr_width
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addr_width => addr_width
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)
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)
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port map (
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port map (
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clk => clk_i,
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clk => clk_i,
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we => mem_we,
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we => mem_we,
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addr => adr_i,
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addr => adr_i,
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d_in => dat_i,
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d_in => dat_i,
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d_out => mem_dat_o
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d_out => mem_dat_o
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);
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);
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dat_o_gen: for i in dat_o'RANGE generate
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dat_o_gen: for i in dat_o'RANGE generate
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dat_o(i) <= (mem_dat_o(i) and stb_i and cyc_i and not we_i) or (dat_oi(i) and not (stb_i and cyc_i and not we_i));
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dat_o(i) <= (mem_dat_o(i) and stb_i and cyc_i and not we_i) or (dat_oi(i) and not (stb_i and cyc_i and not we_i));
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end generate;
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end generate;
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ack_o <= ('1' and stb_i and cyc_i) or (ack_oi and not (stb_i and cyc_i));
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ack_o <= ('1' and stb_i and cyc_i) or (ack_oi and not (stb_i and cyc_i));
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end wb_ram;
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end wb_ram;
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