////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
|
//
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// Filename: ddrsdramsim.cpp
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// Filename: ddrsdramsim.cpp
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//
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <assert.h>
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#include <assert.h>
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#include "ddrsdramsim.h"
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#include "ddrsdramsim.h"
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#define PREFIX "DDR3-SDRAM"
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#define PREFIX "DDR3-SDRAM"
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const unsigned ckCL = 6,
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const unsigned
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ckRESET = 64000, // 200us @ 320MHz
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ckCKE = 160000, // 500us @ 320MHz
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ckCL = 5,
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ckCWL = 5,
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ckCWL = 5,
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ckRP = 6,
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ckRP = 5,
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ckWR = 6,
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ckWR = 5,
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ckRAS = 15,
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ckRAS = 12,
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ckRC = 20,
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ckRC = 16,
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ckMRD = 4,
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ckMRD = 4,
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ckMOD = 12,
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ckMOD = 12,
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ckZQinit = 512,
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ckZQinit = 512,
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ckODT = ckCWL-2,
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ckODT = ckCWL-2,
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ckRFC = 64, // Clocks from refresh to activate
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ckXPR = 56, // Exit reset clocks from CKE HIGH to valid command
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ckREFI = 1560*NWIDTH, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckRFC = 52, // Clocks from refresh to activate
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ckREFI = 2496, // 7.8us @ 320MHz
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DDR_MR2 = 0x0040 | (((ckCWL-5)&7)<<3),
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DDR_MR2 = 0x0040 | (((ckCWL-5)&7)<<3),
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DDR_MR1 = 0x0044,
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DDR_MR1 = 0x0044,
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DDR_MR0 = 0x0000 | (((ckCL-4)&0x07)<<4) | ((ckCL>11)?0x4:0)
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DDR_MR0 = 0x0000 | (((ckCL-4)&0x07)<<4) | ((ckCL>11)?0x4:0)
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|((ckWR==16)?0
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|((ckWR==16)?0
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:(ckWR>=8)?((((ckWR-8)>>1)+8)<<9)
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:(ckWR>=8)?((((ckWR-8)>>1)+8)<<9)
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:((ckWR-5+1)<<9)),
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:((ckWR-5+1)<<9)),
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// Don't pull in any refreshes ...
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nREF = 1;
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nREF = 1;
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|
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BANKINFO::BANKINFO(void) {
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BANKINFO::BANKINFO(void) {
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m_state = 0; m_row = 0; m_wcounter = 0; m_min_time_before_precharge=0;
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m_state = 0; m_row = 0; m_wcounter = 0; m_min_time_before_precharge=0;
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}
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}
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void BANKINFO::tick(int cmd, unsigned addr) {
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void BANKINFO::tick(int cmd, unsigned addr) {
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if (m_wcounter)
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if (m_wcounter)
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m_wcounter--;
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m_wcounter--;
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switch(cmd) {
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switch(cmd) {
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case DDR_REFRESH:
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case DDR_REFRESH:
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assert(m_state == 0);
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assert(m_state == 0);
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break;
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break;
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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// assert((m_state&((1<<ckRP)-1)) == ((1<<ckRP)-1));
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// assert((m_state&((1<<ckRP)-1)) == ((1<<ckRP)-1));
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m_state &= -2;
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m_state &= -2;
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// While the specification allows precharging an already
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// While the specification allows precharging an already
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// precharged bank, we can keep that from happening
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// precharged bank, we can keep that from happening
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// here:
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// here:
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// assert(m_state&7);
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// assert(m_state&7);
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// Only problem is, this will currently break our
|
// Only problem is, this will currently break our
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// refresh logic.
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// refresh logic.
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/*
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/*
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if (m_min_time_before_precharge != 0) {
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if (m_min_time_before_precharge != 0) {
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printf("BANK-FAIL: TIME-BEFORE-PRECHARGE = %d (should be zero)\n", m_min_time_before_precharge);
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printf("BANK-FAIL: TIME-BEFORE-PRECHARGE = %d (should be zero)\n", m_min_time_before_precharge);
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assert(m_min_time_before_precharge == 0);
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assert(m_min_time_before_precharge == 0);
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} if (m_min_time_before_activate != 0) {
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} if (m_min_time_before_activate != 0) {
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printf("BANK-FAIL: TIME-BEFORE-ACTIVATE = %d (should be zero)\n", m_min_time_before_activate);
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printf("BANK-FAIL: TIME-BEFORE-ACTIVATE = %d (should be zero)\n", m_min_time_before_activate);
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assert(m_min_time_before_activate==0);
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assert(m_min_time_before_activate==0);
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}
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}
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*/
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*/
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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assert((m_state&((1<<ckRP)-1)) == 0);
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// assert((m_state&((1<<ckRP)-1)) == 0);
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if (((m_state&7)!=0)&&((addr&0x7fff) != m_row)) {
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if (((m_state&((1<<ckRP)-1))!=0)&&((addr&0x7fff) != m_row)) {
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printf("BANK-FAIL: Attempt to Activate an already active bank without closing it first (m_state = %x)\n", m_state);
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printf(PREFIX "::BANK-FAIL: Attempt to Activate an already active bank without closing it first (m_state = %x)\n", m_state);
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assert((m_state&7)==0);
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// assert((m_state&((1<<ckRP)-1))==0);
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} else if((m_state&((1<<ckRP)-1)) != 0) {
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printf(PREFIX "::DOUBLE-ACTIVATE!!\n");
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}
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}
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/*
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/*
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if (m_wcounter != 0) {
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if (m_wcounter != 0) {
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printf("BANK-FAIL: ACTIVATE too soon after write (wcounter = %d)\n", m_wcounter);
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printf("BANK-FAIL: ACTIVATE too soon after write (wcounter = %d)\n", m_wcounter);
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assert(m_wcounter == 0);
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assert(m_wcounter == 0);
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} if (m_min_time_before_activate!=0) {
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} if (m_min_time_before_activate!=0) {
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printf("BANK-FAIL: ACTIVATE too soon after last activate, (ctr=%d)\n", m_min_time_before_activate);
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printf("BANK-FAIL: ACTIVATE too soon after last activate, (ctr=%d)\n", m_min_time_before_activate);
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assert(m_min_time_before_activate==0);
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assert(m_min_time_before_activate==0);
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}
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}
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*/
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*/
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m_state = 1;
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m_state = 1;
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m_row = addr & 0x7fff;
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m_row = addr & 0x7fff;
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printf("BANK -- Setting address to %04x\n", m_row);
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printf(PREFIX "::BANK -- Setting address to %04x\n", m_row);
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m_min_time_before_precharge = ckRAS;
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m_min_time_before_precharge = ckRAS;
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m_min_time_before_activate = ckRC;
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m_min_time_before_activate = ckRC;
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break;
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break;
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case DDR_READ: case DDR_WRITE:
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case DDR_READ: case DDR_WRITE:
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if (DDR_READ)
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if (DDR_READ)
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assert(m_wcounter == 0);
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assert(m_wcounter == 0);
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else
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else
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m_wcounter = 3+4+4;
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m_wcounter = 3+4+4;
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if ((m_state&((1<<ckRP)-1)) != ((1<<ckRP)-1)) {
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if ((m_state&((1<<ckRP)-1)) != ((1<<ckRP)-1)) {
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printf(PREFIX "::R/W Error: m_state = %08x, ckRP = %d (%08x)\n",
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printf(PREFIX "::R/W Error: m_state = %08x, ckRP = %d (%08x)\n",
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m_state, ckRP, ((1<<ckRP)-1));
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m_state, ckRP, ((1<<ckRP)-1));
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assert((m_state&((1<<ckRP)-1)) == ((1<<ckRP)-1));
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// assert((m_state&((1<<ckRP)-1)) == ((1<<ckRP)-1));
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}
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}
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if (m_min_time_before_precharge)
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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m_min_time_before_activate--;
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break;
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break;
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case DDR_ZQS:
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case DDR_ZQS:
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assert((m_state&((1<<ckRP)-1)) == 0);
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assert((m_state&((1<<ckRP)-1)) == 0);
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if (m_min_time_before_precharge)
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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m_min_time_before_activate--;
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break;
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break;
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case DDR_NOOP:
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case DDR_NOOP:
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// NO BREAK: Fall through. On a NOOP we do the same
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// as if the chip were de-selected.
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default:
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m_state <<= 1;
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m_state <<= 1;
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m_state |= (m_state&2)>>1;
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m_state |= (m_state&2)>>1;
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m_state &= ((1<<ckRP)-1);
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m_state &= ((1<<ckRP)-1);
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// Else the chip was de-selected, and we only need
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// tick time away -- as in a NOOP.
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if (m_min_time_before_precharge)
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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m_min_time_before_activate--;
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break;
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break;
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default:
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|
break;
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|
}
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}
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}
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}
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|
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int gbl_state, gbl_counts;
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int gbl_state, gbl_counts;
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|
|
DDRSDRAMSIM::DDRSDRAMSIM(int lglen) {
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DDRSDRAMSIM::DDRSDRAMSIM(int lglen) {
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m_memlen = (1<<(lglen-2));
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m_memlen = (1<<(lglen-2));
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m_mem = new unsigned[m_memlen];
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m_mem = new unsigned[m_memlen];
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m_reset_state = 0;
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m_reset_state = 0;
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m_reset_counts= 0;
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m_reset_counts= 0;
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assert(NTIMESLOTS > ckCL+3);
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assert(NTIMESLOTS > ckCL+3);
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m_bus = new BUSTIMESLOT[NTIMESLOTS];
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m_bus = new BUSTIMESLOT[NTIMESLOTS];
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for(int i=0; i<NTIMESLOTS; i++)
|
for(int i=0; i<NTIMESLOTS; i++)
|
m_bus[i].m_used = 0;
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m_bus[i].m_used = 0;
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for(int i=0; i<NTIMESLOTS; i++)
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for(int i=0; i<NTIMESLOTS; i++)
|
m_bus[i].m_rtt = 0;
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m_bus[i].m_rtt = 0;
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m_busloc = 0;
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m_busloc = 0;
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}
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}
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|
|
unsigned DDRSDRAMSIM::apply(int reset_n, int cke,
|
unsigned DDRSDRAMSIM::apply(int reset_n, int cke,
|
int csn, int rasn, int casn, int wen,
|
int csn, int rasn, int casn, int wen,
|
int dqs, int dm, int odt, int busoe,
|
int dqs, int dm, int odt, int busoe,
|
int addr, int ba, int data) {
|
int addr, int ba, int data) {
|
BUSTIMESLOT *ts, *nxtts;
|
BUSTIMESLOT *ts, *nxtts;
|
int cmd = (reset_n?0:32)|(cke?0:16)|(csn?8:0)
|
int cmd = (reset_n?0:32)|(cke?0:16)|(csn?8:0)
|
|(rasn?4:0)|(casn?2:0)|(wen?1:0);
|
|(rasn?4:0)|(casn?2:0)|(wen?1:0);
|
|
|
if ((m_reset_state!=0)&&(reset_n==0)) {
|
if ((m_reset_state!=0)&&(reset_n==0)) {
|
m_reset_state = 0;
|
m_reset_state = 0;
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
} else if (m_reset_state < 16) {
|
} else if (m_reset_state < 16) {
|
// printf(PREFIX "::Reset-CMD = %02x,BA=%d,ADDR=%04x, counts = %d\n", cmd, ba, addr, m_reset_counts);
|
// printf(PREFIX "::Reset-CMD = %02x,BA=%d,ADDR=%04x, counts = %d\n", cmd, ba, addr, m_reset_counts);
|
switch(m_reset_state) {
|
switch(m_reset_state) {
|
case 0:
|
case 0:
|
m_reset_counts++;
|
m_reset_counts++;
|
if (reset_n) {
|
if (reset_n) {
|
assert(m_reset_counts > 40000*NWIDTH);
|
assert(m_reset_counts >= (int)ckRESET);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 1;
|
m_reset_state = 1;
|
} break;
|
} break;
|
case 1:
|
case 1:
|
m_reset_counts++;
|
m_reset_counts++;
|
if (cke) {
|
if (cke) {
|
assert(m_reset_counts > 100000*NWIDTH);
|
assert(m_reset_counts >= (int)ckCKE);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 2;
|
m_reset_state = 2;
|
} break;
|
} break;
|
case 2:
|
case 2:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
if (cmd != DDR_NOOP) {
|
if ((cmd != DDR_NOOP)&&(cmd&DDR_DESELECT)==0) {
|
assert(m_reset_counts > (int)(ckRFC+2*NWIDTH));
|
assert(m_reset_counts >= (int)ckXPR);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 3;
|
m_reset_state = 3;
|
assert(cmd == DDR_MRSET);
|
assert(cmd == DDR_MRSET);
|
// Set MR2
|
// Set MR2
|
assert(ba == 2);
|
assert(ba == 2);
|
printf(PREFIX "::Checking DDR-MR2(%04x) against %04x\n", addr, DDR_MR2);
|
printf(PREFIX "::Checking DDR-MR2(%04x) against %04x\n", addr, DDR_MR2);
|
assert(addr == DDR_MR2);
|
assert(addr == DDR_MR2);
|
} break;
|
} break;
|
case 3:
|
case 3:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
if (cmd != DDR_NOOP) {
|
if ((cmd != DDR_NOOP)&&(cmd&DDR_DESELECT)==0) {
|
assert(m_reset_counts >= (int)ckMRD);
|
assert(m_reset_counts >= (int)ckMRD);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 4;
|
m_reset_state = 4;
|
assert(cmd == DDR_MRSET);
|
assert(cmd == DDR_MRSET);
|
// Set MR1
|
// Set MR1
|
assert(ba == 1);
|
assert(ba == 1);
|
assert(addr == DDR_MR1);
|
assert(addr == DDR_MR1);
|
} break;
|
} break;
|
case 4:
|
case 4:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
if (cmd != DDR_NOOP) {
|
if ((cmd != DDR_NOOP)&&(cmd&DDR_DESELECT)==0) {
|
printf(PREFIX "::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
printf(PREFIX "::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
assert(m_reset_counts >= (int)ckMRD);
|
assert(m_reset_counts >= (int)ckMRD);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 5;
|
m_reset_state = 5;
|
assert(cmd == DDR_MRSET);
|
assert(cmd == DDR_MRSET);
|
// Set MR0
|
// Set MR0
|
assert(ba == 0);
|
assert(ba == 0);
|
assert(addr == DDR_MR0);
|
assert(addr == DDR_MR0);
|
} break;
|
} break;
|
case 5:
|
case 5:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
if (cmd != DDR_NOOP) {
|
if ((cmd != DDR_NOOP)&&(cmd&DDR_DESELECT)==0) {
|
printf(PREFIX "::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
printf(PREFIX "::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
assert(m_reset_counts >= (int)ckMOD);
|
assert(m_reset_counts >= (int)ckMOD);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 6;
|
m_reset_state = 6;
|
assert(cmd == DDR_ZQS);
|
assert(cmd == DDR_ZQS);
|
assert(addr == 0x400);
|
assert(addr == 0x400);
|
} break;
|
} break;
|
case 6:
|
case 6:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
if (cmd != DDR_NOOP) {
|
if ((cmd != DDR_NOOP)&&(cmd&DDR_DESELECT)==0) {
|
printf(PREFIX "::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
printf(PREFIX "::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
assert(m_reset_counts >= (int)ckZQinit);
|
assert(m_reset_counts >= (int)ckZQinit);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 7;
|
m_reset_state = 7;
|
assert(cmd == DDR_PRECHARGE);
|
assert(cmd == DDR_PRECHARGE);
|
assert(addr == 0x400);
|
assert(addr == 0x400);
|
} break;
|
} break;
|
case 7:
|
case 7:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
if (cmd != DDR_NOOP) {
|
if ((cmd != DDR_NOOP)&&(cmd&DDR_DESELECT)==0) {
|
printf(PREFIX "::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
printf(PREFIX "::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
|
assert(m_reset_counts >= (int)ckRP);
|
assert(m_reset_counts >= (int)ckRP);
|
m_reset_counts = 0;
|
m_reset_counts = 0;
|
m_reset_state = 8;
|
m_reset_state = 8;
|
assert(cmd == DDR_REFRESH);
|
assert(cmd == DDR_REFRESH);
|
m_clocks_since_refresh = 0;
|
m_clocks_since_refresh = 0;
|
} break;
|
} break;
|
case 8:
|
case 8:
|
m_reset_counts++;
|
m_reset_counts++;
|
assert(cke);
|
assert(cke);
|
assert(cmd == DDR_NOOP);
|
assert((cmd == DDR_NOOP)||(cmd&DDR_DESELECT));
|
if (m_reset_counts > (int)ckRFC) {
|
if (m_reset_counts > (int)ckRFC) {
|
m_reset_state = 16;
|
m_reset_state = 16;
|
printf(PREFIX ": Leaving reset state\n");
|
printf(PREFIX ": Leaving reset state\n");
|
}
|
}
|
break;
|
break;
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
|
|
gbl_state = m_reset_state;
|
gbl_state = m_reset_state;
|
gbl_counts= m_reset_counts;
|
gbl_counts= m_reset_counts;
|
m_nrefresh_issued = nREF;
|
m_nrefresh_issued = nREF;
|
m_clocks_since_refresh++;
|
m_clocks_since_refresh++;
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(cmd, 0);
|
m_bank[i].tick(cmd, 0);
|
} else if (!cke) {
|
} else if (!cke) {
|
assert(0&&"Clock not enabled!");
|
assert(0&&"Clock not enabled!");
|
} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
|
} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
|
if (DDR_REFRESH == cmd) {
|
if (DDR_REFRESH == cmd) {
|
m_clocks_since_refresh = 0;
|
m_clocks_since_refresh = 0;
|
if (m_nrefresh_issued >= (int)nREF)
|
if (m_nrefresh_issued >= (int)nREF)
|
m_nrefresh_issued = 1;
|
m_nrefresh_issued = 1;
|
else
|
else
|
m_nrefresh_issued++;
|
m_nrefresh_issued++;
|
} else {
|
} else {
|
m_clocks_since_refresh++;
|
m_clocks_since_refresh++;
|
assert(DDR_NOOP == cmd);
|
assert(DDR_NOOP == cmd);
|
}
|
}
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(cmd,0);
|
m_bank[i].tick(cmd,0);
|
|
|
if (m_nrefresh_issued == nREF)
|
if (m_nrefresh_issued == nREF)
|
printf(PREFIX "::Refresh cycle complete\n");
|
printf(PREFIX "::Refresh cycle complete\n");
|
} else {
|
} else {
|
// In operational mode!!
|
// In operational mode!!
|
|
|
m_clocks_since_refresh++;
|
m_clocks_since_refresh++;
|
if (m_clocks_since_refresh > (int)ckREFI) {
|
if (m_clocks_since_refresh > (int)ckREFI) {
|
printf(PREFIX "::ERROR! Clocks since refresh = %d, which isn\'t less than %d\n", m_clocks_since_refresh, ckREFI);
|
printf(PREFIX "::ERROR! Clocks since refresh = %d, which isn\'t less than %d\n", m_clocks_since_refresh, ckREFI);
|
}
|
}
|
assert(m_clocks_since_refresh <= (int)ckREFI);
|
assert(m_clocks_since_refresh <= (int)ckREFI);
|
switch(cmd) {
|
switch(cmd) {
|
case DDR_MRSET:
|
case DDR_MRSET:
|
assert(0&&"Modes should only be set in reset startup");
|
assert(0&&"Modes should only be set in reset startup");
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_MRSET,0);
|
m_bank[i].tick(DDR_MRSET,0);
|
break;
|
break;
|
case DDR_REFRESH:
|
case DDR_REFRESH:
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_REFRESH,0);
|
m_bank[i].tick(DDR_REFRESH,0);
|
m_clocks_since_refresh = 0;
|
m_clocks_since_refresh = 0;
|
assert(0 && "Internal err: Refresh should be handled above");
|
assert(0 && "Internal err: Refresh should be handled above");
|
break;
|
break;
|
case DDR_PRECHARGE:
|
case DDR_PRECHARGE:
|
if (addr & 0x400) {
|
if (addr & 0x400) {
|
// Precharge all
|
// Precharge all
|
printf(PREFIX "::Precharging all banks\n");
|
printf(PREFIX "::Precharging all banks\n");
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_PRECHARGE,0);
|
m_bank[i].tick(DDR_PRECHARGE,0);
|
} else {
|
} else {
|
printf(PREFIX "::Precharging bank [%d]\n", ba);
|
printf(PREFIX "::Precharging bank [%d]\n", ba);
|
m_bank[ba].tick(DDR_PRECHARGE,0);
|
m_bank[ba].tick(DDR_PRECHARGE,0);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (ba != i)
|
if (ba != i)
|
m_bank[i].tick(DDR_NOOP,0);
|
m_bank[i].tick(DDR_NOOP,0);
|
}
|
}
|
break;
|
break;
|
case DDR_ACTIVATE:
|
case DDR_ACTIVATE:
|
if (m_clocks_since_refresh < (int)ckRFC) {
|
if (m_clocks_since_refresh < (int)ckRFC) {
|
printf(PREFIX "::ACTIVATE -- not enough clocks since refresh, %d < %d should be true\n", m_clocks_since_refresh, ckRFC);
|
printf(PREFIX "::ACTIVATE -- not enough clocks since refresh, %d < %d should be true\n", m_clocks_since_refresh, ckRFC);
|
assert(m_clocks_since_refresh >= (int)ckRFC);
|
assert(m_clocks_since_refresh >= (int)ckRFC);
|
}
|
}
|
printf(PREFIX "::Activating bank %d, address %08x\n", ba, addr);
|
printf(PREFIX "::Activating bank %d, address %08x\n", ba, addr);
|
m_bank[ba].tick(DDR_ACTIVATE,addr);
|
m_bank[ba].tick(DDR_ACTIVATE,addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
|
if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
|
break;
|
break;
|
case DDR_WRITE:
|
case DDR_WRITE:
|
{
|
{
|
// This SIM doesn't handle out of order writes
|
// This SIM doesn't handle out of order writes
|
assert((addr&7)==0);
|
assert((addr&7)==0);
|
m_bank[ba].tick(DDR_WRITE, addr);
|
m_bank[ba].tick(DDR_WRITE, addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
unsigned caddr = m_bank[ba].m_row;
|
unsigned caddr = m_bank[ba].m_row;
|
caddr <<= 3;
|
caddr <<= 3;
|
caddr |= ba;
|
caddr |= ba;
|
caddr <<= 10;
|
caddr <<= 10;
|
caddr |= addr;
|
caddr |= addr;
|
caddr &= ~7;
|
caddr &= ~7;
|
caddr >>= 1;
|
caddr >>= 1;
|
|
|
BUSTIMESLOT *tp;
|
BUSTIMESLOT *tp;
|
int offset = m_busloc+ckCWL+1;
|
int offset = m_busloc+ckCWL+1;
|
|
|
tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
|
// printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
|
// printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
|
tp->m_addr = caddr ;
|
tp->m_addr = caddr ;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
|
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
tp->m_addr = caddr+1;
|
tp->m_addr = caddr+1;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
|
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
tp->m_addr = caddr+2;
|
tp->m_addr = caddr+2;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
|
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
tp->m_addr = caddr+3;
|
tp->m_addr = caddr+3;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
} break;
|
} break;
|
case DDR_READ:
|
case DDR_READ:
|
{
|
{
|
// This SIM doesn't handle out of order reads
|
// This SIM doesn't handle out of order reads
|
assert((addr&7)==0);
|
assert((addr&7)==0);
|
m_bank[ba].tick(DDR_READ, addr);
|
m_bank[ba].tick(DDR_READ, addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
unsigned caddr = m_bank[ba].m_row;
|
unsigned caddr = m_bank[ba].m_row;
|
caddr <<= 3;
|
caddr <<= 3;
|
caddr |= ba;
|
caddr |= ba;
|
caddr <<= 10;
|
caddr <<= 10;
|
caddr |= addr;
|
caddr |= addr;
|
caddr &= ~7;
|
caddr &= ~7;
|
caddr >>= 1;
|
caddr >>= 1;
|
|
|
BUSTIMESLOT *tp;
|
BUSTIMESLOT *tp;
|
|
|
printf(PREFIX"::READ(%03x:%d:%03x => %08x) Queuing %08x:%08x:%08x:%08x\n",
|
printf(PREFIX"::READ(%03x:%d:%03x => %08x) Queuing %08x:%08x:%08x:%08x\n",
|
m_bank[ba].m_row, ba, addr,
|
m_bank[ba].m_row, ba, addr,
|
caddr,
|
caddr,
|
m_mem[caddr ], m_mem[caddr+1],
|
m_mem[caddr ], m_mem[caddr+1],
|
m_mem[caddr+2], m_mem[caddr+3]);
|
m_mem[caddr+2], m_mem[caddr+3]);
|
int offset = (m_busloc+ckCL+1)&(NTIMESLOTS-1);
|
int offset = (m_busloc+ckCL+1)&(NTIMESLOTS-1);
|
tp = &m_bus[(offset)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr];
|
tp->m_data = m_mem[caddr];
|
tp->m_addr = caddr;
|
tp->m_addr = caddr;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr+1];
|
tp->m_data = m_mem[caddr+1];
|
tp->m_addr = caddr+1;
|
tp->m_addr = caddr+1;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr+2];
|
tp->m_data = m_mem[caddr+2];
|
tp->m_addr = caddr+2;
|
tp->m_addr = caddr+2;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr+3];
|
tp->m_data = m_mem[caddr+3];
|
tp->m_addr = caddr+3;
|
tp->m_addr = caddr+3;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
} break;
|
} break;
|
case DDR_ZQS:
|
case DDR_ZQS:
|
assert(0&&"Sim does not support ZQS outside of startup");
|
assert(0&&"Sim does not support ZQS outside of startup");
|
break;
|
break;
|
case DDR_NOOP:
|
case DDR_NOOP:
|
for(int i=0; i<NBANKS; i++)
|
default: // We are deselected
|
m_bank[i].tick(DDR_NOOP,addr);
|
|
break;
|
|
default: // We are deselecteda
|
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_NOOP,addr);
|
m_bank[i].tick(DDR_NOOP,addr);
|
break;
|
break;
|
}
|
}
|
|
|
if (false) {
|
if (false) {
|
bool flag = false;
|
bool flag = false;
|
for(int i=0; i<5; i++) {
|
for(int i=0; i<5; i++) {
|
int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
|
int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
|
nxtts = &m_bus[bl];
|
nxtts = &m_bus[bl];
|
if (nxtts->m_used) {
|
if (nxtts->m_used) {
|
flag = true;
|
flag = true;
|
break;
|
break;
|
}
|
}
|
} if (flag) {
|
} if (flag) {
|
printf(PREFIX "::DQS = %d BUSLOC = %d\n", dqs, (m_busloc+1)&(NTIMESLOTS-1));
|
printf(PREFIX "::DQS = %d BUSLOC = %d\n", dqs, (m_busloc+1)&(NTIMESLOTS-1));
|
for(int i=0; i<5; i++) {
|
for(int i=0; i<5; i++) {
|
int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
|
int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
|
nxtts = &m_bus[bl];
|
nxtts = &m_bus[bl];
|
printf("BUS[%2d] ", bl);
|
printf("BUS[%2d] ", bl);
|
if (nxtts->m_used)
|
if (nxtts->m_used)
|
printf(" USED");
|
printf(" USED");
|
if (nxtts->m_read)
|
if (nxtts->m_read)
|
printf(" READ");
|
printf(" READ");
|
if (nxtts->m_rtt)
|
if (nxtts->m_rtt)
|
printf(" RTT");
|
printf(" RTT");
|
printf("\n");
|
printf("\n");
|
}}
|
}}
|
}
|
}
|
|
|
ts = &m_bus[(m_busloc+1)&(NTIMESLOTS-1)];
|
ts = &m_bus[(m_busloc+1)&(NTIMESLOTS-1)];
|
if (dqs) {
|
if (dqs) {
|
/*
|
if ((!ts->m_rtt)||(!m_last_rtt)) {
|
if ((!ts->m_rtt)||(!m_last_rtt)) {
|
printf(PREFIX "ODT(dqs is true) m_rtt is %s and last_rtt is %s. Both should be true if DQS. (ERROR!)\n",
|
printf(PREFIX "ODT(dqs is true) m_rtt is %s and last_rtt is %s. Both should be true if DQS. (ERROR!)\n",
|
(ts->m_rtt)?"true":"false",
|
(ts->m_rtt)?"true":"false",
|
(m_last_rtt)?"true":"false");
|
(m_last_rtt)?"true":"false");
|
}
|
} */
|
|
assert((ts->m_rtt)&&(m_last_rtt));
|
assert((ts->m_rtt)&&(m_last_rtt));
|
} else if (!m_last_dqs)
|
} // else if (!m_last_dqs)
|
assert(!m_last_rtt);
|
// assert(!m_last_rtt);
|
}
|
}
|
|
|
m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
|
m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
|
|
|
ts = &m_bus[m_busloc];
|
ts = &m_bus[m_busloc];
|
nxtts = &m_bus[(m_busloc+1)&(NTIMESLOTS-1)];
|
nxtts = &m_bus[(m_busloc+1)&(NTIMESLOTS-1)];
|
unsigned vl = ts->m_data;
|
unsigned vl = ts->m_data;
|
|
|
assert( ((!ts->m_used)||(busoe))
|
/*
|
|| ((ts->m_used)&&(ts->m_read)&&(!busoe))
|
assert( ((!ts->m_used)||(busoe))
|
|| ((ts->m_used)&&(!ts->m_read)&&(busoe))
|
|| ((ts->m_used)&&(ts->m_read)&&(!busoe))
|
);
|
|| ((ts->m_used)&&(!ts->m_read)&&(busoe))
|
|
);
|
|
*/
|
|
|
m_last_dqs = dqs;
|
m_last_dqs = dqs;
|
m_last_rtt = ts->m_rtt;
|
m_last_rtt = ts->m_rtt;
|
|
|
if (ts->m_used) {
|
/*
|
if (ts->m_read)
|
if (ts->m_used) {
|
assert((!dqs)&&(!m_last_dqs));
|
if (ts->m_read)
|
else
|
assert((!dqs)&&(!m_last_dqs));
|
assert((dqs) && (m_last_dqs));
|
else
|
} else if (!nxtts->m_used)
|
assert((dqs) && (m_last_dqs));
|
assert(!dqs);
|
} else if (!nxtts->m_used)
|
|
assert(!dqs);
|
|
*/
|
|
|
assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
|
// assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
|
if ((ts->m_used)&&(!ts->m_read)&&(dm != 0x0f)) {
|
if ((ts->m_used)&&(!ts->m_read)&&(dm != 0x0f)) {
|
printf(PREFIX "::Setting MEM[%08x] = %08x (%02x)\n", ts->m_addr, data, dm);
|
printf(PREFIX "::Setting MEM[%08x] = %08x (%02x)\n", ts->m_addr, data, dm);
|
unsigned mask = 0;
|
unsigned mask = 0;
|
if (dm&0x08) mask = 0x0ff;
|
if (dm&0x08) mask = 0x0ff;
|
mask <<= 8; if (dm&0x004) mask |= 0x0ff;
|
mask <<= 8; if (dm&0x004) mask |= 0x0ff;
|
mask <<= 8; if (dm&0x002) mask |= 0x0ff;
|
mask <<= 8; if (dm&0x002) mask |= 0x0ff;
|
mask <<= 8; if (dm&0x001) mask |= 0x0ff;
|
mask <<= 8; if (dm&0x001) mask |= 0x0ff;
|
m_mem[ts->m_addr] = (data & (~mask)) | (m_mem[ts->m_addr]&mask);
|
m_mem[ts->m_addr] = (data & (~mask)) | (m_mem[ts->m_addr]&mask);
|
} else if ((ts->m_used)&&(ts->m_read)) {
|
} else if ((ts->m_used)&&(ts->m_read)) {
|
printf(PREFIX ":: %08x\n", vl);
|
printf(PREFIX ":: %08x\n", vl);
|
}
|
}
|
|
|
m_bus[(m_busloc+ckODT-1)&(NTIMESLOTS-1)].m_rtt = (odt)&&(reset_n);
|
m_bus[(m_busloc+ckODT-1)&(NTIMESLOTS-1)].m_rtt = (odt)&&(reset_n);
|
ts->m_used = 0;
|
ts->m_used = 0;
|
ts->m_read = 0;
|
ts->m_read = 0;
|
ts->m_addr = -1;
|
ts->m_addr = -1;
|
ts->m_rtt = 0;
|
ts->m_rtt = 0;
|
return (!busoe)?vl:data;
|
return (!busoe)?vl:data;
|
}
|
}
|
|
|
|
|
