////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: ddrsdramsim.cpp
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// Filename: ddrsdramsim.cpp
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//
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <assert.h>
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#include <assert.h>
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const unsigned ckCL = 5,
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const unsigned ckCL = 5,
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ckRC = 3,
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ckRC = 3,
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ckRFC = 320, // Clocks from refresh to activate
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ckRFC = 320, // Clocks from refresh to activate
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nREF = 4,
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nREF = 4,
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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#include "ddrsdramsim.h"
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#include "ddrsdramsim.h"
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void BANKINFO::tick(int cmd, unsigned addr) {
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void BANKINFO::tick(int cmd, unsigned addr) {
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switch(cmd) {
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switch(cmd) {
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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m_state = 6;
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m_state = 6;
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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m_state = 1;
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m_state = 1;
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m_row = addr & 0x7fff;
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m_row = addr & 0x7fff;
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break;
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break;
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case DDR_READ: case DDR_WRITE:
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case DDR_READ: case DDR_WRITE:
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printf("BANK::R/W Request, m_state = %d\n", m_state);
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printf("BANK::R/W Request, m_state = %d\n", m_state);
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assert((m_state&7) == 7);
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assert((m_state&7) == 7);
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break;
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break;
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case DDR_ZQS:
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case DDR_ZQS:
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assert((m_state&7) == 0);
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assert((m_state&7) == 0);
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break;
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break;
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case DDR_NOOP:
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case DDR_NOOP:
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m_state <<= 1;
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m_state <<= 1;
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m_state |= (m_state&2)>>1;
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m_state |= (m_state&2)>>1;
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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}
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}
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int gbl_state, gbl_counts;
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int gbl_state, gbl_counts;
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DDRSDRAMSIM::DDRSDRAMSIM(int lglen) {
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DDRSDRAMSIM::DDRSDRAMSIM(int lglen) {
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m_memlen = (1<<(lglen-2));
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m_memlen = (1<<(lglen-2));
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m_mem = new unsigned[m_memlen];
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m_mem = new unsigned[m_memlen];
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m_reset_state = 0;
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m_reset_state = 0;
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m_reset_counts= 0;
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m_reset_counts= 0;
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m_bus = new BUSTIMESLOT[NTIMESLOTS];
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m_bus = new BUSTIMESLOT[NTIMESLOTS];
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for(int i=0; i<NTIMESLOTS; i++)
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for(int i=0; i<NTIMESLOTS; i++)
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m_bus[i].m_used = 0;
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m_bus[i].m_used = 0;
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m_busloc = 0;
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m_busloc = 0;
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}
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}
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unsigned DDRSDRAMSIM::operator()(int reset_n, int cke,
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unsigned DDRSDRAMSIM::operator()(int reset_n, int cke,
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int csn, int rasn, int casn, int wen,
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int csn, int rasn, int casn, int wen,
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int dqs, int dm, int odt, int busoe,
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int dqs, int dm, int odt, int busoe,
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int addr, int ba, int data) {
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int addr, int ba, int data) {
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|
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int cmd = (reset_n?0:32)|(cke?0:16)|(csn?8:0)
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int cmd = (reset_n?0:32)|(cke?0:16)|(csn?8:0)
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|(rasn?4:0)|(casn?2:0)|(wen?1:0);
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|(rasn?4:0)|(casn?2:0)|(wen?1:0);
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if ((m_reset_state!=0)&&(reset_n==0)) {
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if ((m_reset_state!=0)&&(reset_n==0)) {
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m_reset_state = 0;
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m_reset_state = 0;
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m_reset_counts = 0;
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m_reset_counts = 0;
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} else if (m_reset_state < 16) {
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} else if (m_reset_state < 16) {
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switch(m_reset_state) {
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switch(m_reset_state) {
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case 0:
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case 0:
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m_reset_counts++;
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m_reset_counts++;
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if (reset_n) {
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if (reset_n) {
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assert(m_reset_counts > 40000);
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assert(m_reset_counts > 40000);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 1;
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m_reset_state = 1;
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} break;
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} break;
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case 1:
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case 1:
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m_reset_counts++;
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m_reset_counts++;
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if (cke) {
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if (cke) {
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assert(m_reset_counts > 100000);
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assert(m_reset_counts > 100000);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 2;
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m_reset_state = 2;
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} break;
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} break;
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case 2:
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case 2:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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assert(m_reset_counts > 147);
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assert(m_reset_counts > 147);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 3;
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m_reset_state = 3;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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assert(ba == 2);
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assert(ba == 2);
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assert(addr == 0x040);
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assert(addr == 0x040);
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} break;
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} break;
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case 3:
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case 3:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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// assert(m_reset_counts > 3);
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// assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 4;
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m_reset_state = 4;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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// assert(ba == 1);
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// assert(ba == 1);
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// assert(addr == 0x847);
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// assert(addr == 0x847);
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} break;
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} break;
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case 4:
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case 4:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 5;
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m_reset_state = 5;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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assert(ba == 0);
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assert(ba == 0);
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assert(addr == 0x210);
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assert(addr == 0x210);
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} break;
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} break;
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case 5:
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case 5:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 11);
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assert(m_reset_counts > 11);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 6;
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m_reset_state = 6;
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assert(cmd == DDR_ZQS);
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assert(cmd == DDR_ZQS);
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assert(addr == 0x400);
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assert(addr == 0x400);
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} break;
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} break;
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case 6:
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case 6:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 512);
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assert(m_reset_counts > 512);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 7;
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m_reset_state = 7;
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assert(cmd == DDR_PRECHARGE);
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assert(cmd == DDR_PRECHARGE);
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assert(addr == 0x400);
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assert(addr == 0x400);
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} break;
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} break;
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case 7:
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case 7:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 8;
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m_reset_state = 8;
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assert(cmd == DDR_REFRESH);
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assert(cmd == DDR_REFRESH);
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m_clocks_since_refresh = 0;
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m_clocks_since_refresh = 0;
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} break;
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} break;
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case 8:
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case 8:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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assert(cmd == DDR_NOOP);
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assert(cmd == DDR_NOOP);
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if (m_reset_counts > 140) {
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if (m_reset_counts > 140) {
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m_reset_state = 16;
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m_reset_state = 16;
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printf("DDR3-SDRAM: Leaving reset state\n");
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printf("DDR3-SDRAM: Leaving reset state\n");
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}
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}
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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|
|
gbl_state = m_reset_state;
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gbl_state = m_reset_state;
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gbl_counts= m_reset_counts;
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gbl_counts= m_reset_counts;
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m_nrefresh_issued = nREF;
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m_nrefresh_issued = nREF;
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m_clocks_since_refresh++;
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} else if (!cke) {
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} else if (!cke) {
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assert(0&&"Clock not enabled!");
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assert(0&&"Clock not enabled!");
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} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
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} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
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if (DDR_REFRESH == cmd) {
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if (DDR_REFRESH == cmd) {
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m_clocks_since_refresh = 0;
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m_clocks_since_refresh = 0;
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if (m_nrefresh_issued >= (int)nREF)
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if (m_nrefresh_issued >= (int)nREF)
|
m_nrefresh_issued = 0;
|
m_nrefresh_issued = 1;
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else
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else
|
m_nrefresh_issued++;
|
m_nrefresh_issued++;
|
} else {
|
} else {
|
m_clocks_since_refresh++;
|
m_clocks_since_refresh++;
|
assert(DDR_NOOP == cmd);
|
assert(DDR_NOOP == cmd);
|
}
|
}
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for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_REFRESH,0);
|
m_bank[i].tick(DDR_REFRESH,0);
|
|
|
|
if (m_nrefresh_issued == nREF)
|
|
printf("DDRSDRAM::Refresh cycle complete\n");
|
} else {
|
} else {
|
// In operational mode!!
|
// In operational mode!!
|
|
|
m_clocks_since_refresh++;
|
m_clocks_since_refresh++;
|
assert(m_clocks_since_refresh < (int)ckREFIn);
|
assert(m_clocks_since_refresh < (int)ckREFIn);
|
|
printf("Clocks to refresh should be %4d-%4d = %4d = 0x%04x\n",
|
|
ckREFIn, m_clocks_since_refresh,
|
|
ckREFIn- m_clocks_since_refresh,
|
|
ckREFIn- m_clocks_since_refresh);
|
switch(cmd) {
|
switch(cmd) {
|
case DDR_MRSET:
|
case DDR_MRSET:
|
assert(0&&"Modes should only be set in reset startup");
|
assert(0&&"Modes should only be set in reset startup");
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_MRSET,0);
|
m_bank[i].tick(DDR_MRSET,0);
|
break;
|
break;
|
case DDR_REFRESH:
|
case DDR_REFRESH:
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_REFRESH,0);
|
m_bank[i].tick(DDR_REFRESH,0);
|
m_clocks_since_refresh = 0;
|
m_clocks_since_refresh = 0;
|
assert(0 && "Internal err: Refresh should be handled above");
|
assert(0 && "Internal err: Refresh should be handled above");
|
break;
|
break;
|
case DDR_PRECHARGE:
|
case DDR_PRECHARGE:
|
if (addr & 0x40) {
|
if (addr & 0x40) {
|
// Precharge all
|
// Precharge all
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_PRECHARGE,0);
|
m_bank[i].tick(DDR_PRECHARGE,0);
|
} else {
|
} else {
|
m_bank[ba].tick(DDR_PRECHARGE,0);
|
m_bank[ba].tick(DDR_PRECHARGE,0);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (ba != i)
|
if (ba != i)
|
m_bank[i].tick(DDR_NOOP,0);
|
m_bank[i].tick(DDR_NOOP,0);
|
}
|
}
|
break;
|
break;
|
case DDR_ACTIVATE:
|
case DDR_ACTIVATE:
|
|
printf("DDRSIM::ACTIVE, clocks_since_refresh = %d >= %d\n", m_clocks_since_refresh, ckRFC);
|
|
assert(m_clocks_since_refresh >= (int)ckRFC);
|
m_bank[ba].tick(DDR_ACTIVATE,addr);
|
m_bank[ba].tick(DDR_ACTIVATE,addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
|
if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
|
break;
|
break;
|
case DDR_WRITE:
|
case DDR_WRITE:
|
{
|
{
|
// This SIM doesn't handle out of order writes
|
// This SIM doesn't handle out of order writes
|
assert((addr&7)==0);
|
assert((addr&7)==0);
|
m_bank[ba].tick(DDR_WRITE, addr);
|
m_bank[ba].tick(DDR_WRITE, addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
unsigned addr = m_bank[ba].m_row;
|
unsigned caddr = m_bank[ba].m_row;
|
addr <<= 13;
|
caddr <<= 13;
|
addr |= ba;
|
caddr |= ba;
|
addr <<= 10;
|
caddr <<= 10;
|
addr |= addr;
|
caddr |= addr;
|
addr &= ~3;
|
caddr &= ~7;
|
|
caddr >>= 1;
|
|
|
|
printf("DDRSDRAM::WRITE ADDR = %04x|%d|%04x|%d -> %06x\n",
|
|
m_bank[ba].m_row, ba, addr, 0, caddr);
|
|
|
BUSTIMESLOT *tp;
|
BUSTIMESLOT *tp;
|
|
int offset = m_busloc+ckCL+1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
|
tp->m_addr = addr ;
|
printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
|
|
tp->m_addr = caddr ;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
|
|
tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
tp->m_addr = addr+1;
|
tp->m_addr = caddr+1;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
|
|
tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
tp->m_addr = addr+2;
|
tp->m_addr = caddr+2;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
|
|
tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
tp->m_addr = addr+3;
|
tp->m_addr = caddr+3;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 0;
|
tp->m_read = 0;
|
} break;
|
} break;
|
case DDR_READ:
|
case DDR_READ:
|
{
|
{
|
// This SIM doesn't handle out of order reads
|
// This SIM doesn't handle out of order reads
|
assert((addr&7)==0);
|
assert((addr&7)==0);
|
m_bank[ba].tick(DDR_READ, addr);
|
m_bank[ba].tick(DDR_READ, addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
unsigned addr = m_bank[ba].m_row;
|
unsigned caddr = m_bank[ba].m_row;
|
addr <<= 13;
|
caddr <<= 13;
|
addr |= ba;
|
caddr |= ba;
|
addr <<= 10;
|
caddr <<= 10;
|
addr |= addr;
|
caddr |= addr;
|
addr &= ~3;
|
caddr &= ~7;
|
|
caddr >>= 1;
|
|
|
BUSTIMESLOT *tp;
|
BUSTIMESLOT *tp;
|
|
|
tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
|
tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[addr];
|
tp->m_data = m_mem[caddr];
|
tp->m_addr = addr;
|
tp->m_addr = caddr;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
|
tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[addr+1];
|
tp->m_data = m_mem[caddr+1];
|
tp->m_addr = addr+1;
|
tp->m_addr = caddr+1;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
|
tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[addr+2];
|
tp->m_data = m_mem[caddr+2];
|
tp->m_addr = addr+2;
|
tp->m_addr = caddr+2;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
|
tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[addr+3];
|
tp->m_data = m_mem[caddr+3];
|
tp->m_addr = addr+3;
|
tp->m_addr = caddr+3;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
} break;
|
} break;
|
case DDR_ZQS:
|
case DDR_ZQS:
|
assert(0&&"Sim does not support ZQS outside of startup");
|
assert(0&&"Sim does not support ZQS outside of startup");
|
break;
|
break;
|
case DDR_NOOP:
|
case DDR_NOOP:
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_NOOP,addr);
|
m_bank[i].tick(DDR_NOOP,addr);
|
break;
|
break;
|
default: // We are deselecteda
|
default: // We are deselecteda
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_NOOP,addr);
|
m_bank[i].tick(DDR_NOOP,addr);
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
|
m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
|
|
|
BUSTIMESLOT *ts = &m_bus[m_busloc];
|
BUSTIMESLOT *ts = &m_bus[m_busloc];
|
|
if (ts->m_used) {
|
|
printf("Current timeslot = %2d, used", m_busloc);
|
|
if (ts->m_read)
|
|
printf(", read");
|
|
printf("\n");
|
|
}
|
unsigned vl = ts->m_data;
|
unsigned vl = ts->m_data;
|
assert( ((!ts->m_used)||(busoe))
|
assert( ((!ts->m_used)||(busoe))
|
|| ((ts->m_used)&&(ts->m_read)));
|
|| ((ts->m_used)&&(ts->m_read)));
|
|
|
assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
|
assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
|
if ((ts->m_used)&&(!ts->m_read)&&(!dm))
|
if ((ts->m_used)&&(!ts->m_read)&&(!dm)) {
|
|
printf("Setting MEM[%08x] = %08x\n", ts->m_addr, data);
|
m_mem[ts->m_addr] = data;
|
m_mem[ts->m_addr] = data;
|
|
}
|
ts->m_used = 0;
|
ts->m_used = 0;
|
ts->m_read = 0;
|
ts->m_read = 0;
|
ts->m_addr = -1;
|
ts->m_addr = -1;
|
return (!busoe)?vl:data;
|
return (!busoe)?vl:data;
|
}
|
}
|
|
|
|
|
