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%%
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%%
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%% Filename: spec.tex
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%% Filename: spec.tex
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%%
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%% Project: A wishbone controlled DDR3 SDRAM memory controller.
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%% Project: A wishbone controlled DDR3 SDRAM memory controller.
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%%
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%%
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%% Purpose: This LaTeX file contains all of the documentation, or should I
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%% Purpose: This LaTeX file contains all of the documentation, or should I
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%% say all of the description necessary to produce the
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%% say all of the description necessary to produce the
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%% documentation, currently provided with the Wishbone controlled DDR3
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%% documentation, currently provided with the Wishbone controlled DDR3
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%% SDRAM core. For those interested in this core, this file is not nearly
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%% SDRAM core. For those interested in this core, this file is not nearly
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%% as interesting as the PDF file this file is used to create. Therefore,
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%% as interesting as the PDF file this file is used to create. Therefore,
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%% I recommend building and then reading that pdf file, spec.pdf, before
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%% I recommend building and then reading that pdf file, spec.pdf, before
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%% diving into what's going on within this file. You should be able to
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%% diving into what's going on within this file. You should be able to
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%% find the pdf file in this SVN distribution, together with this LaTeX
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%% find the pdf file in this SVN distribution, together with this LaTeX
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%% file and a copy of the GPL-3.0 license this file is distributed under.
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%% file and a copy of the GPL-3.0 license this file is distributed under.
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%% If not, just type 'make' in the doc directory and it (should) build the
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%% If not, just type 'make' in the doc directory and it (should) build the
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%% pdf file without a problem. (This, of course, assumes you have a valid
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%% pdf file without a problem. (This, of course, assumes you have a valid
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%% and working LaTeX distribution, together with dvips and Ghostscript.)
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%% and working LaTeX distribution, together with dvips and Ghostscript.)
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%%
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%%
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%%
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%%
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%% Creator: Dan Gisselquist, Ph.D.
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%% Creator: Dan Gisselquist, Ph.D.
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%% Gisselquist Technology, LLC
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%% Gisselquist Technology, LLC
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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%% Copyright (C) 2015-2016, Gisselquist Technology, LLC
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%% Copyright (C) 2015-2016, Gisselquist Technology, LLC
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%%
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of the GNU General Public License as published
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%% modify it under the terms of the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%% your option) any later version.
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%%
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% for more details.
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%% for more details.
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%%
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%%
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%% You should have received a copy of the GNU General Public License along
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%% You should have received a copy of the GNU General Public License along
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%% with this program. (It's in the $(ROOT)/doc directory, run make with no
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%% with this program. (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.) If not, see
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%% target there if the PDF file isn't present.) If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%%
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%% License: GPL, v3, as defined and found on www.gnu.org,
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%% License: GPL, v3, as defined and found on www.gnu.org,
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%% http://www.gnu.org/licenses/gpl.html
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%% http://www.gnu.org/licenses/gpl.html
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%%
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\usepackage{import}
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\usepackage{import}
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\project{WB DDR3 SDRAM Controller}
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\project{WB DDR3 SDRAM Controller}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.0}
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\revision{Rev.~0.0}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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Copyright (C) \theyear\today, Owner
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Copyright (C) \theyear\today, Owner
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This project is free software (firmware): you can redistribute it and/or
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of the GNU General Public License as published
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modify it under the terms of the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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your option) any later version.
|
|
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
for more details.
|
for more details.
|
|
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You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
|
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.0 & 6/20/2016 & D. Gisselquist & Initial Version\\\hline
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0.0 & 8/02/2016 & D. Gisselquist & (Pre-release) Initial Version\\\hline
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\end{revisionhistory}
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\end{revisionhistory}
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% Revision History
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% Revision History
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% Table of Contents, named Contents
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% Table of Contents, named Contents
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\tableofcontents
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\tableofcontents
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\listoffigures
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\listoffigures
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\listoftables
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\listoftables
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\begin{preface}
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\begin{preface}
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Now, just why am I building this? Because wishbone's been so good to me?
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Now, just why am I building this? Because wishbone's been so good to me?
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Because I've never used AXI? Because I dislike not being able to see
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Because I've never used AXI? Because I dislike not being able to see
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what goes on within a memory controller, and have no insight into why it's
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what goes on within a memory controller, and have no insight into why it's
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performance is as fast (or slow) as it is? Because Xilinx allows you to only
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performance is as fast (or slow) as it is? Because Xilinx allows you to only
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open 4 banks at a tim? Or is it because, when I went to purchase my first
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open 4 banks at a tim? Or is it because, when I went to purchase my first
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high speed FPGA circuit board, the vendor offered me the opportunity to
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high speed FPGA circuit board, the vendor offered me the opportunity to
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purchase a DMA controller with it? As a micro businessman, I really can't
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purchase a DMA controller with it? As a micro businessman, I really can't
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afford using someone else's stuff. Time is cheap, money isn't nearly so cheap.
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afford using someone else's stuff. Time is cheap, money isn't nearly so cheap.
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Hence, I offer my work to you as well. I hope you find it useful. Of course,
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Hence, I offer my work to you as well. I hope you find it useful. Of course,
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the normal caveats are available: I am available for hire, and I would be happy
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the normal caveats are available: I am available for hire, and I would be happy
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to modify this core or even the license it is distributed under, for an
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to modify this core or even the license it is distributed under, for an
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appropriate incentive.
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appropriate incentive.
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\end{preface}
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\end{preface}
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\chapter{Introduction}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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\setcounter{page}{1}
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|
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%
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%
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% Introduction
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% Introduction
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%
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%
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% This section contains the introduction to the core, describing both its
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% This section contains the introduction to the core, describing both its
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% use and its features.
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% use and its features.
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%
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%
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The purpose of this core is to provide a GPL Wishbone Core capable of commanding
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The purpose of this core is to provide a GPL Wishbone Core capable of commanding
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a DDR3 memory at full speed. A particular design goal is that consecutive
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a DDR3 memory at full speed. A particular design goal is that consecutive
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reads or writes should only take one additional clock per read/write.
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reads or writes should only take one additional clock per read/write.
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% What is old
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% What is old
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Since the DDR3 memory specification is dated as of August, 2009, memory chips
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Since the DDR3 memory specification is dated as of August, 2009, memory chips
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have been built to this specification. However, since DDR3 SDRAM's are rather
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have been built to this specification. However, since DDR3 SDRAM's are rather
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complex, and there is a lot of work required to manage them, controllers for
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complex, and there is a lot of work required to manage them, controllers for
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DDR3 SDRAM's remain primarily in the realm of proprietary.
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DDR3 SDRAM's remain primarily in the realm of proprietary.
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|
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% What does the old lack?
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% What does the old lack?
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Currently, there are no DDR3 controllers present on OpenCores. Sure,
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Currently, there are no DDR3 controllers present on OpenCores. Sure,
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there's a project named ``DDR3 SDRAM controller'', yet it has no data files
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there's a project named ``DDR3 SDRAM controller'', yet it has no data files
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present with it. This leaves the FPGA engineers with the choice of building
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present with it. This leaves the FPGA engineers with the choice of building
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a controller for a very complex interface, or using a proprietary core from
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a controller for a very complex interface, or using a proprietary core from
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Xilinx's Memory Interface Generator, for which there is no insight into how it
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Xilinx's Memory Interface Generator, for which there is no insight into how it
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works, and then retooling their bus from wishbone to AXI.
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works, and then retooling their bus from wishbone to AXI.
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% What is new
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% What is new
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This core is designed to meet that need: it is both open (GPL), as well as
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This core is designed to meet that need: it is both open (GPL), as well as
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wishbone compliant.
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wishbone compliant.
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% What does the new have that the old lacks
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% What does the new have that the old lacks
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Further, this core offers 32--bit granularity to an interface that would
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Further, this core offers 32--bit granularity to an interface that would
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otherwise offer only 128--bit granularity. This core also offers complete
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otherwise offer only 128--bit granularity. This core also offers complete
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pipelind performance.
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pipelind performance.
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% What performance gain can be expected?
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% What performance gain can be expected?
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Because of the pipeline performance, this core is very appropriate for filling
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Because of the pipeline performance, this core is very appropriate for filling
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cache lines. Because the core also offers non--pipelined performance, it is
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cache lines. Because the core also offers non--pipelined performance, it is
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also appropriate for random access from a CPU--whether by a write--through cache
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also appropriate for random access from a CPU--whether by a write--through cache
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or a CPU working without a cache.
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or a CPU working without a cache.
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\chapter{Architecture}
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\chapter{Architecture}
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|
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% This section describes the architecture of the block. A block level diagram
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% This section describes the architecture of the block. A block level diagram
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% should be included describing the top level of the design.
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% should be included describing the top level of the design.
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\section{Data Structures}
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There are two basic data structures within the core: the bank data structures,
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and the bus data structure(s). The first keeps track of the persistent state
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of each bank, while the second keeps track of I/O transactions that have been
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initiated but not completed.
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\section{Strategies}
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\section{Strategies}
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\subsection{Bank}
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\subsection{Bank}
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Currently, banks are activated (opened) when needed and only precharged
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Currently, banks are activated (opened) when needed and only precharged
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(closed) upon refresh request. Further, upon any read or write from one bank,
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(closed) upon refresh request. Further, upon any read or write from one bank,
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the next bank is activated as well, under the assumption that the next bank
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the next bank is activated as well, under the assumption that the next bank
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will be needed soon. This is necessary to allow pipeline access with no stalls
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will be needed soon. This is necessary to allow pipeline access with no stalls
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through the memory controller.
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through the memory controller.
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This means that, upon any bank miss, a bank precharge followed by bank activate
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This means that, upon any bank miss, a bank precharge followed by bank activate
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command will be necessary.
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command will be necessary.
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\subsection{Refresh}
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\subsection{Refresh}
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The current build will pause all operations for four subsequent refreshes,
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The current build will pause all operations for four subsequent refreshes,
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at roughly every 4 refresh intervals, and then allow operations to resume.
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at roughly every 4 refresh intervals, and then allow operations to resume.
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This pause is independent of anything going on, and includes a mandatory
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This pause is independent of anything going on, and includes a mandatory
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wait for any writes to finish, followed by a precharge command---regardless of
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wait for any writes to finish, followed by a precharge command---regardless of
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whether or not such is required.
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whether or not such is required.
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|
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This is non-optimal, and ripe for optimizing later. A better strategy might
|
This is non-optimal, and ripe for optimizing later. A better strategy might
|
be to do singular refreshes after any single refresh period assuming the bus
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be to do singular refreshes after any single refresh period assuming the bus
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is free, to only issue a precharge if the bus is busy, and to only wait
|
is free, to only issue a precharge if the bus is busy, and to only wait
|
prior to that precharge if a write is busy. This will be a later optimization.
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prior to that precharge if a write is busy. This will be a later optimization.
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\chapter{Operation}
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\chapter{Operation}
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% This section describes the operation of the core. Specific sequences, such
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% This section describes the operation of the core. Specific sequences, such
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% as startup sequences, as well as the modes and states of the block should be
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% as startup sequences, as well as the modes and states of the block should be
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% described.
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% described.
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%
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%
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When accessed from within an FPGA, this core should be simple to access:
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When accessed from within an FPGA, this core should be simple to access:
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Raise the {\tt i\_wb\_cyc} line at the beginning of every transaction.
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Raise the {\tt i\_wb\_cyc} line at the beginning of every transaction.
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Set {\tt i\_wb\_stb} (transaction strobe), {\tt i\_wb\_we} (Write enable,
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Set {\tt i\_wb\_stb} (transaction strobe), {\tt i\_wb\_we} (Write enable,
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true if writing or false otherwise), {\tt i\_wb\_addr} (address of value),
|
true if writing or false otherwise), {\tt i\_wb\_addr} (address of value),
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and {\tt i\_wb\_data} for every transaction. You may move to the next
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and {\tt i\_wb\_data} for every transaction. You may move to the next
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transaction any time {\tt i\_wb\_stb} is true on the same clock that
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transaction any time {\tt i\_wb\_stb} is true on the same clock that
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{\tt o\_wb\_stall} is false. Transactions will be pipelined internally. When
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{\tt o\_wb\_stall} is false. Transactions will be pipelined internally. When
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{\tt o\_wb\_ack} is true, a transaction has completed. If that transaction
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{\tt o\_wb\_ack} is true, a transaction has completed. If that transaction
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was a read transaction, {\tt o\_wb\_data}, will also be filled with the data
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was a read transaction, {\tt o\_wb\_data}, will also be filled with the data
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read from the memory device.
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read from the memory device.
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\chapter{Clocks}
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\chapter{Clocks}
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% This section specifies all of the clocks. All clocks, clock domain passes
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% This section specifies all of the clocks. All clocks, clock domain passes
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% and the clock relations should be described.
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% and the clock relations should be described.
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% Name | Source | Rates (MHz) | Remarks | Description
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% Name | Source | Rates (MHz) | Remarks | Description
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% | Max|Min|Resolution|
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% | Max|Min|Resolution|
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This design is centered around a DDR-1600 chip. In order to run this chip
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This design is centered around a DDR-1600 chip. In order to run this chip
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at speed, it requires a 200MHz clock. Xilinx recommends a 160~MHz clock for
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at speed, it requires a 200MHz clock. Xilinx recommends a 160~MHz clock for
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their design, so it should work at slower rates--I just don't know how much
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their design, so it should work at slower rates--I just don't know how much
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slower the design will continue to work for.
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slower the design will continue to work for.
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If you wish to slow down the design, adjust the parameter {\tt CKREFI4} to be
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If you wish to slow down the design, adjust the parameter {\tt CKREFI4} to be
|
the number of clocks expected in four timse 7.8~$\mu$s.
|
the number of clocks expected in four timse 7.8~$\mu$s.
|
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\chapter{Wishbone Datasheet}\label{chap:wishbone}
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\chapter{Wishbone Datasheet}\label{chap:wishbone}
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Tbl.~\ref{tbl:wishbone}
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Tbl.~\ref{tbl:wishbone}
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\begin{table}[htbp]
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\begin{table}[htbp]
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\begin{center}
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\begin{center}
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\begin{wishboneds}
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\begin{wishboneds}
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Revision level of wishbone & WB B4 spec \\\hline
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Revision level of wishbone & WB B4 spec \\\hline
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Type of interface & Slave, Read/Write, pipeline mode supported \\\hline
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Type of interface & Slave, Read/Write, pipeline mode supported \\\hline
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Port size & 32--bit \\\hline
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Port size & 32--bit \\\hline
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Port granularity & 32--bit \\\hline
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Port granularity & 32--bit \\\hline
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Maximum Operand Size & 32--bit \\\hline
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Maximum Operand Size & 32--bit \\\hline
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Data transfer ordering & (Irrelevant) \\\hline
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Data transfer ordering & (Irrelevant) \\\hline
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Clock constraints & Designed for 200MHz, DDR1600\\\hline
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Clock constraints & Designed for 200MHz, DDR1600\\\hline
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Signal Names & \begin{tabular}{ll}
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Signal Names & \begin{tabular}{ll}
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Signal Name & Wishbone Equivalent \\\hline
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Signal Name & Wishbone Equivalent \\\hline
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{\tt i\_wb\_clk} & {\tt CLK\_I} \\
|
{\tt i\_wb\_clk} & {\tt CLK\_I} \\
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{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
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{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
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{\tt i\_wb\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_stb} & {\tt STB\_I} \\
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{\tt i\_wb\_we} & {\tt WE\_I} \\
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{\tt i\_wb\_we} & {\tt WE\_I} \\
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{\tt i\_wb\_addr} & {\tt ADR\_I} \\
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{\tt i\_wb\_addr} & {\tt ADR\_I} \\
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{\tt i\_wb\_data} & {\tt DAT\_I} \\
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{\tt i\_wb\_data} & {\tt DAT\_I} \\
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{\tt o\_wb\_ack} & {\tt ACK\_O} \\
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{\tt o\_wb\_ack} & {\tt ACK\_O} \\
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{\tt o\_wb\_stall} & {\tt STALL\_O} \\
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{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
\end{tabular}\\\hline
|
\end{tabular}\\\hline
|
\end{wishboneds}
|
\end{wishboneds}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
is required by the wishbone specification, and so
|
is required by the wishbone specification, and so it is included here. The big
|
it is included here. The big thing to notice is that all accesses to the
|
thing to notice is that all accesses to the DDR3 SDRAM memory are via 32--bit
|
DDR3 SDRAM memory are via 32--bit reads and writes to this interface. You may
|
reads and writes to this interface. You may also wish to note that the memory
|
also wish to note that the scope supports pipeline reading and writing, to
|
interface supports pipeline reading and writing, to speed up any transfers. As
|
speed up reading the results out. As a result, the memory interface speed
|
a result, the memory interface speed should approach one transfer per clock
|
should approach one transfer per clock once the pipeline is loaded, although
|
once the pipeline is loaded, although there will be delays loading the pipeline.
|
there will be delays loading the pipeline.
|
Other than refresh cycles, once the pipeline is loaded it will continue its
|
|
transfer rate at one cycle per clock for as long as it is fed at that speed.
|
|
|
Further, the Wishbone specification this core communicates with has been
|
Further, the Wishbone specification this core communicates with has been
|
simplified in this manner: The {\tt STB\_I} signal has been constrained so that
|
simplified in this manner: The {\tt STB\_I} signal has been constrained so that
|
it will only be true if {\tt CYC\_I} is also true. To interface this core
|
it will only be true if {\tt CYC\_I} is also true. To interface this core
|
in an environment without this requirement, simply create the {\tt i\_wb\_stb}
|
in an environment without this requirement, simply create the {\tt i\_wb\_stb}
|
by anding {\tt STB\_I} together with {\tt CYC\_I} before sending the strobe
|
by anding {\tt STB\_I} together with {\tt CYC\_I} before sending the strobe
|
logic into the core.
|
logic into the core.
|
|
|
\chapter{I/O Ports}
|
\chapter{I/O Ports}
|
% This section specifies all of the core IO ports
|
% This section specifies all of the core IO ports
|
|
|
The wishbone ports to this core were discussed in the last chapter, and shown
|
The wishbone ports to this core were discussed in the last chapter, and shown
|
in Tbl.~\ref{tbl:wishbone}. The rest of the I/O ports to this core are listed
|
in Tbl.~\ref{tbl:wishbone}. The rest of the I/O ports to this core are listed
|
in Tbl.~\ref{tbl:ioports}.
|
in Tbl.~\ref{tbl:ioports}.
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{portlist}
|
\begin{portlist}
|
{\tt i\_clk\_200mhz} & 1 & Output & A 200 MHz clock input \\
|
{\tt i\_clk\_200mhz} & 1 & Output & A 200 MHz clock input \\
|
{\tt o\_ddr\_reset\_n} & 1 & Output & Active low reset command to the chip\\
|
{\tt o\_ddr\_reset\_n} & 1 & Output & Active low reset command to the chip\\
|
{\tt o\_ddr\_cke} & 1 & Output & Clock Enable \\
|
{\tt o\_ddr\_cke} & 1 & Output & Clock Enable \\
|
{\tt o\_ddr\_cs\_n} & 1 & Output & Chip select\\
|
{\tt o\_ddr\_cs\_n} & 1 & Output & Chip select\\
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{\tt o\_ddr\_ras\_n} & 1 & Output & RAS\# Command input \\
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{\tt o\_ddr\_ras\_n} & 1 & Output & RAS\# Command input \\
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{\tt o\_ddr\_cas\_n} & 1 & Output & RAS\# Command input \\
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{\tt o\_ddr\_cas\_n} & 1 & Output & RAS\# Command input \\
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{\tt o\_ddr\_we\_n} & 1 & Output & WE\# Command input \\
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{\tt o\_ddr\_we\_n} & 1 & Output & WE\# Command input \\
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{\tt o\_ddr\_dqs} & 1 & Output & True if the FPGA should drive the DQS on this clock, false otherwise. While not a DDR output, this needs to be converted to a DDR 2'b10 (if true) before it leaves the FPGA, or high impedence if false. \\
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{\tt o\_ddr\_dqs} & 1 & Output & True if the FPGA should drive the DQS on this clock, false otherwise. While not a DDR output, this needs to be converted to a DDR 2'b10 (if true) before it leaves the FPGA, or high impedence if false. \\
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{\tt o\_ddr\_dm} & 3 & Output & Data Mask, used to enable only those valid writes. Although a DDR output, we treat it as SDR since all transactions are 32--bits (or more).\\
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{\tt o\_ddr\_dm} & 3 & Output & Data Mask, used to enable only those valid writes. Although a DDR output, we treat it as SDR since all transactions are 32--bits (or more).\\
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{\tt o\_ddr\_odt} & 1 & Output & On--Die--Termination bit. This will be true any time the data lines are being driven\\
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{\tt o\_ddr\_odt} & 1 & Output & On--Die--Termination bit. This will be true any time the data lines are being driven\\
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{\tt o\_ddr\_bus\_dir} & 1 & Output & True if the FPGA will be driving the data bus lines during this clock, false otherwise\\
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{\tt o\_ddr\_bus\_dir} & 1 & Output & True if the FPGA will be driving the data bus lines during this clock, false otherwise\\
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{\tt o\_ddr\_ba} & 3 & Output & Bank Address, 0-7\\
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{\tt o\_ddr\_ba} & 3 & Output & Bank Address, 0-7\\
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{\tt o\_ddr\_addr} & 16 & Output & Command address, either row or column\\
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{\tt o\_ddr\_addr} & 16 & Output & Command address, either row or column\\
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{\tt o\_ddr\_data} & 32 & Output & The output to be sent to the chip. This will need to be bumped to DDR rates before it actually hits the chip. \\
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{\tt o\_ddr\_data} & 32 & Output & The output to be sent to the chip. This will need to be bumped to DDR rates before it actually hits the chip. \\
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{\tt i\_ddr\_data} & 32 & Input & The data input from the chip. This comes in at DDR rates, and needs a Xilinx primitive to bring it from 16'bits to 32'bits.\\
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{\tt i\_ddr\_data} & 32 & Input & The data input from the chip. This comes in at DDR rates, and needs a Xilinx primitive to bring it from 16'bits to 32'bits.\\
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\end{portlist}
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\end{portlist}
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\caption{List of IO ports that are not Wishbone Related}\label{tbl:ioports}
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\caption{List of IO ports that are not Wishbone Related}\label{tbl:ioports}
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\end{center}\end{table}
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\end{center}\end{table}
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% Appendices
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% Appendices
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% A. May be added to outline different specifications. (??)
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% A. May be added to outline different specifications. (??)
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% Index
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% Index
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\end{document}
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\end{document}
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